SparcISelLowering.cpp revision f5aeb1a8e4cf272c7348376d185ef8d8267653e0
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcTargetMachine.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/CallingConvLower.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24using namespace llvm; 25 26 27//===----------------------------------------------------------------------===// 28// Calling Convention Implementation 29//===----------------------------------------------------------------------===// 30 31#include "SparcGenCallingConv.inc" 32 33static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { 34 // CCValAssign - represent the assignment of the return value to locations. 35 SmallVector<CCValAssign, 16> RVLocs; 36 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 37 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 38 39 // CCState - Info about the registers and stack slot. 40 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs); 41 42 // Analize return values of ISD::RET 43 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32); 44 45 // If this is the first return lowered for this function, add the regs to the 46 // liveout set for the function. 47 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 48 for (unsigned i = 0; i != RVLocs.size(); ++i) 49 if (RVLocs[i].isRegLoc()) 50 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 51 } 52 53 SDValue Chain = Op.getOperand(0); 54 SDValue Flag; 55 56 // Copy the result values into the output registers. 57 for (unsigned i = 0; i != RVLocs.size(); ++i) { 58 CCValAssign &VA = RVLocs[i]; 59 assert(VA.isRegLoc() && "Can only return in registers!"); 60 61 // ISD::RET => ret chain, (regnum1,val1), ... 62 // So i*2+1 index only the regnums. 63 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 64 65 // Guarantee that all emitted copies are stuck together with flags. 66 Flag = Chain.getValue(1); 67 } 68 69 if (Flag.getNode()) 70 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag); 71 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain); 72} 73 74/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 75/// either one or two GPRs, including FP values. TODO: we should pass FP values 76/// in FP registers for fastcc functions. 77void 78SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, 79 SmallVectorImpl<SDValue> &ArgValues) { 80 MachineFunction &MF = DAG.getMachineFunction(); 81 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 82 83 static const unsigned ArgRegs[] = { 84 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 85 }; 86 87 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 88 unsigned ArgOffset = 68; 89 90 SDValue Root = DAG.getRoot(); 91 std::vector<SDValue> OutChains; 92 93 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 94 MVT ObjectVT = getValueType(I->getType()); 95 96 switch (ObjectVT.getSimpleVT()) { 97 default: assert(0 && "Unhandled argument type!"); 98 case MVT::i1: 99 case MVT::i8: 100 case MVT::i16: 101 case MVT::i32: 102 if (I->use_empty()) { // Argument is dead. 103 if (CurArgReg < ArgRegEnd) ++CurArgReg; 104 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 105 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 106 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 107 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 108 SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 109 if (ObjectVT != MVT::i32) { 110 unsigned AssertOp = ISD::AssertSext; 111 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 112 DAG.getValueType(ObjectVT)); 113 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 114 } 115 ArgValues.push_back(Arg); 116 } else { 117 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 118 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 119 SDValue Load; 120 if (ObjectVT == MVT::i32) { 121 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 122 } else { 123 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 124 125 // Sparc is big endian, so add an offset based on the ObjectVT. 126 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); 127 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 128 DAG.getConstant(Offset, MVT::i32)); 129 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 130 NULL, 0, ObjectVT); 131 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 132 } 133 ArgValues.push_back(Load); 134 } 135 136 ArgOffset += 4; 137 break; 138 case MVT::f32: 139 if (I->use_empty()) { // Argument is dead. 140 if (CurArgReg < ArgRegEnd) ++CurArgReg; 141 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 142 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 143 // FP value is passed in an integer register. 144 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 145 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 146 SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 147 148 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 149 ArgValues.push_back(Arg); 150 } else { 151 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 152 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 153 SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 154 ArgValues.push_back(Load); 155 } 156 ArgOffset += 4; 157 break; 158 159 case MVT::i64: 160 case MVT::f64: 161 if (I->use_empty()) { // Argument is dead. 162 if (CurArgReg < ArgRegEnd) ++CurArgReg; 163 if (CurArgReg < ArgRegEnd) ++CurArgReg; 164 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 165 } else { 166 SDValue HiVal; 167 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 168 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 169 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 170 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 171 } else { 172 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 173 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 174 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 175 } 176 177 SDValue LoVal; 178 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 179 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 180 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 181 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 182 } else { 183 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 184 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 185 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 186 } 187 188 // Compose the two halves together into an i64 unit. 189 SDValue WholeValue = 190 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 191 192 // If we want a double, do a bit convert. 193 if (ObjectVT == MVT::f64) 194 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 195 196 ArgValues.push_back(WholeValue); 197 } 198 ArgOffset += 8; 199 break; 200 } 201 } 202 203 // Store remaining ArgRegs to the stack if this is a varargs function. 204 if (F.isVarArg()) { 205 // Remember the vararg offset for the va_start implementation. 206 VarArgsFrameOffset = ArgOffset; 207 208 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 209 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 210 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 211 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 212 213 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 214 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 215 216 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 217 ArgOffset += 4; 218 } 219 } 220 221 if (!OutChains.empty()) 222 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 223 &OutChains[0], OutChains.size())); 224} 225 226static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { 227 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 228 SDValue Chain = Op.getOperand(0); 229 SDValue Callee = Op.getOperand(4); 230 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 231 232#if 0 233 // Analyze operands of the call, assigning locations to each operand. 234 SmallVector<CCValAssign, 16> ArgLocs; 235 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs); 236 CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32); 237 238 // Get the size of the outgoing arguments stack space requirement. 239 unsigned ArgsSize = CCInfo.getNextStackOffset(); 240 // FIXME: We can't use this until f64 is known to take two GPRs. 241#else 242 (void)CC_Sparc32; 243 244 // Count the size of the outgoing arguments. 245 unsigned ArgsSize = 0; 246 for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { 247 switch (Op.getOperand(i).getValueType().getSimpleVT()) { 248 default: assert(0 && "Unknown value type!"); 249 case MVT::i1: 250 case MVT::i8: 251 case MVT::i16: 252 case MVT::i32: 253 case MVT::f32: 254 ArgsSize += 4; 255 break; 256 case MVT::i64: 257 case MVT::f64: 258 ArgsSize += 8; 259 break; 260 } 261 } 262 if (ArgsSize > 4*6) 263 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 264 else 265 ArgsSize = 0; 266#endif 267 268 // Keep stack frames 8-byte aligned. 269 ArgsSize = (ArgsSize+7) & ~7; 270 271 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize)); 272 273 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 274 SmallVector<SDValue, 8> MemOpChains; 275 276#if 0 277 // Walk the register/memloc assignments, inserting copies/loads. 278 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 279 CCValAssign &VA = ArgLocs[i]; 280 281 // Arguments start after the 5 first operands of ISD::CALL 282 SDValue Arg = Op.getOperand(5+2*VA.getValNo()); 283 284 // Promote the value if needed. 285 switch (VA.getLocInfo()) { 286 default: assert(0 && "Unknown loc info!"); 287 case CCValAssign::Full: break; 288 case CCValAssign::SExt: 289 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 290 break; 291 case CCValAssign::ZExt: 292 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 293 break; 294 case CCValAssign::AExt: 295 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 296 break; 297 } 298 299 // Arguments that can be passed on register must be kept at 300 // RegsToPass vector 301 if (VA.isRegLoc()) { 302 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 303 continue; 304 } 305 306 assert(VA.isMemLoc()); 307 308 // Create a store off the stack pointer for this argument. 309 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 310 // FIXME: VERIFY THAT 68 IS RIGHT. 311 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); 312 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 313 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 314 } 315 316#else 317 static const unsigned ArgRegs[] = { 318 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 319 }; 320 unsigned ArgOffset = 68; 321 322 for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { 323 SDValue Val = Op.getOperand(i); 324 MVT ObjectVT = Val.getValueType(); 325 SDValue ValToStore(0, 0); 326 unsigned ObjSize; 327 switch (ObjectVT.getSimpleVT()) { 328 default: assert(0 && "Unhandled argument type!"); 329 case MVT::i32: 330 ObjSize = 4; 331 332 if (RegsToPass.size() >= 6) { 333 ValToStore = Val; 334 } else { 335 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); 336 } 337 break; 338 case MVT::f32: 339 ObjSize = 4; 340 if (RegsToPass.size() >= 6) { 341 ValToStore = Val; 342 } else { 343 // Convert this to a FP value in an int reg. 344 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 345 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); 346 } 347 break; 348 case MVT::f64: 349 ObjSize = 8; 350 // Otherwise, convert this to a FP value in int regs. 351 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 352 // FALL THROUGH 353 case MVT::i64: 354 ObjSize = 8; 355 if (RegsToPass.size() >= 6) { 356 ValToStore = Val; // Whole thing is passed in memory. 357 break; 358 } 359 360 // Split the value into top and bottom part. Top part goes in a reg. 361 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 362 DAG.getConstant(1, MVT::i32)); 363 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 364 DAG.getConstant(0, MVT::i32)); 365 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); 366 367 if (RegsToPass.size() >= 6) { 368 ValToStore = Lo; 369 ArgOffset += 4; 370 ObjSize = 4; 371 } else { 372 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo)); 373 } 374 break; 375 } 376 377 if (ValToStore.getNode()) { 378 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 379 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); 380 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 381 MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 382 } 383 ArgOffset += ObjSize; 384 } 385#endif 386 387 // Emit all stores, make sure the occur before any copies into physregs. 388 if (!MemOpChains.empty()) 389 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 390 &MemOpChains[0], MemOpChains.size()); 391 392 // Build a sequence of copy-to-reg nodes chained together with token 393 // chain and flag operands which copy the outgoing args into registers. 394 // The InFlag in necessary since all emited instructions must be 395 // stuck together. 396 SDValue InFlag; 397 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 398 unsigned Reg = RegsToPass[i].first; 399 // Remap I0->I7 -> O0->O7. 400 if (Reg >= SP::I0 && Reg <= SP::I7) 401 Reg = Reg-SP::I0+SP::O0; 402 403 Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag); 404 InFlag = Chain.getValue(1); 405 } 406 407 // If the callee is a GlobalAddress node (quite common, every direct call is) 408 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 409 // Likewise ExternalSymbol -> TargetExternalSymbol. 410 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 411 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 412 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 413 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 414 415 std::vector<MVT> NodeTys; 416 NodeTys.push_back(MVT::Other); // Returns a chain 417 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 418 SDValue Ops[] = { Chain, Callee, InFlag }; 419 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2); 420 InFlag = Chain.getValue(1); 421 422 Chain = DAG.getCALLSEQ_END(Chain, 423 DAG.getConstant(ArgsSize, MVT::i32), 424 DAG.getConstant(0, MVT::i32), InFlag); 425 InFlag = Chain.getValue(1); 426 427 // Assign locations to each value returned by this call. 428 SmallVector<CCValAssign, 16> RVLocs; 429 CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs); 430 431 RVInfo.AnalyzeCallResult(Op.getNode(), RetCC_Sparc32); 432 SmallVector<SDValue, 8> ResultVals; 433 434 // Copy all of the result registers out of their specified physreg. 435 for (unsigned i = 0; i != RVLocs.size(); ++i) { 436 unsigned Reg = RVLocs[i].getLocReg(); 437 438 // Remap I0->I7 -> O0->O7. 439 if (Reg >= SP::I0 && Reg <= SP::I7) 440 Reg = Reg-SP::I0+SP::O0; 441 442 Chain = DAG.getCopyFromReg(Chain, Reg, 443 RVLocs[i].getValVT(), InFlag).getValue(1); 444 InFlag = Chain.getValue(2); 445 ResultVals.push_back(Chain.getValue(0)); 446 } 447 448 ResultVals.push_back(Chain); 449 450 // Merge everything together with a MERGE_VALUES node. 451 return DAG.getMergeValues(Op.getNode()->getVTList(), &ResultVals[0], 452 ResultVals.size()); 453} 454 455 456 457//===----------------------------------------------------------------------===// 458// TargetLowering Implementation 459//===----------------------------------------------------------------------===// 460 461/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 462/// condition. 463static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 464 switch (CC) { 465 default: assert(0 && "Unknown integer condition code!"); 466 case ISD::SETEQ: return SPCC::ICC_E; 467 case ISD::SETNE: return SPCC::ICC_NE; 468 case ISD::SETLT: return SPCC::ICC_L; 469 case ISD::SETGT: return SPCC::ICC_G; 470 case ISD::SETLE: return SPCC::ICC_LE; 471 case ISD::SETGE: return SPCC::ICC_GE; 472 case ISD::SETULT: return SPCC::ICC_CS; 473 case ISD::SETULE: return SPCC::ICC_LEU; 474 case ISD::SETUGT: return SPCC::ICC_GU; 475 case ISD::SETUGE: return SPCC::ICC_CC; 476 } 477} 478 479/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 480/// FCC condition. 481static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 482 switch (CC) { 483 default: assert(0 && "Unknown fp condition code!"); 484 case ISD::SETEQ: 485 case ISD::SETOEQ: return SPCC::FCC_E; 486 case ISD::SETNE: 487 case ISD::SETUNE: return SPCC::FCC_NE; 488 case ISD::SETLT: 489 case ISD::SETOLT: return SPCC::FCC_L; 490 case ISD::SETGT: 491 case ISD::SETOGT: return SPCC::FCC_G; 492 case ISD::SETLE: 493 case ISD::SETOLE: return SPCC::FCC_LE; 494 case ISD::SETGE: 495 case ISD::SETOGE: return SPCC::FCC_GE; 496 case ISD::SETULT: return SPCC::FCC_UL; 497 case ISD::SETULE: return SPCC::FCC_ULE; 498 case ISD::SETUGT: return SPCC::FCC_UG; 499 case ISD::SETUGE: return SPCC::FCC_UGE; 500 case ISD::SETUO: return SPCC::FCC_U; 501 case ISD::SETO: return SPCC::FCC_O; 502 case ISD::SETONE: return SPCC::FCC_LG; 503 case ISD::SETUEQ: return SPCC::FCC_UE; 504 } 505} 506 507 508SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 509 : TargetLowering(TM) { 510 511 // Set up the register classes. 512 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 513 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 514 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 515 516 // Turn FP extload into load/fextend 517 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 518 // Sparc doesn't have i1 sign extending load 519 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 520 // Turn FP truncstore into trunc + store. 521 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 522 523 // Custom legalize GlobalAddress nodes into LO/HI parts. 524 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 525 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 526 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 527 528 // Sparc doesn't have sext_inreg, replace them with shl/sra 529 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 530 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 532 533 // Sparc has no REM or DIVREM operations. 534 setOperationAction(ISD::UREM, MVT::i32, Expand); 535 setOperationAction(ISD::SREM, MVT::i32, Expand); 536 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 537 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 538 539 // Custom expand fp<->sint 540 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 541 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 542 543 // Expand fp<->uint 544 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 545 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 546 547 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 548 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 549 550 // Sparc has no select or setcc: expand to SELECT_CC. 551 setOperationAction(ISD::SELECT, MVT::i32, Expand); 552 setOperationAction(ISD::SELECT, MVT::f32, Expand); 553 setOperationAction(ISD::SELECT, MVT::f64, Expand); 554 setOperationAction(ISD::SETCC, MVT::i32, Expand); 555 setOperationAction(ISD::SETCC, MVT::f32, Expand); 556 setOperationAction(ISD::SETCC, MVT::f64, Expand); 557 558 // Sparc doesn't have BRCOND either, it has BR_CC. 559 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 560 setOperationAction(ISD::BRIND, MVT::Other, Expand); 561 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 562 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 563 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 564 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 565 566 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 567 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 568 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 569 570 // SPARC has no intrinsics for these particular operations. 571 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 572 573 setOperationAction(ISD::FSIN , MVT::f64, Expand); 574 setOperationAction(ISD::FCOS , MVT::f64, Expand); 575 setOperationAction(ISD::FREM , MVT::f64, Expand); 576 setOperationAction(ISD::FSIN , MVT::f32, Expand); 577 setOperationAction(ISD::FCOS , MVT::f32, Expand); 578 setOperationAction(ISD::FREM , MVT::f32, Expand); 579 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 580 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 581 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 582 setOperationAction(ISD::ROTL , MVT::i32, Expand); 583 setOperationAction(ISD::ROTR , MVT::i32, Expand); 584 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 585 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 586 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 587 setOperationAction(ISD::FPOW , MVT::f64, Expand); 588 setOperationAction(ISD::FPOW , MVT::f32, Expand); 589 setOperationAction(ISD::FLOG , MVT::f64, Expand); 590 setOperationAction(ISD::FLOG , MVT::f32, Expand); 591 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 592 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 593 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 594 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 595 setOperationAction(ISD::FEXP , MVT::f64, Expand); 596 setOperationAction(ISD::FEXP , MVT::f32, Expand); 597 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 598 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 599 600 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 601 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 602 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 603 604 // FIXME: Sparc provides these multiplies, but we don't have them yet. 605 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 606 607 // We don't have line number support yet. 608 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 609 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 610 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 611 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 612 613 // RET must be custom lowered, to meet ABI requirements 614 setOperationAction(ISD::RET , MVT::Other, Custom); 615 616 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 617 setOperationAction(ISD::VASTART , MVT::Other, Custom); 618 // VAARG needs to be lowered to not do unaligned accesses for doubles. 619 setOperationAction(ISD::VAARG , MVT::Other, Custom); 620 621 // Use the default implementation. 622 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 623 setOperationAction(ISD::VAEND , MVT::Other, Expand); 624 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 625 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 626 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 627 628 // No debug info support yet. 629 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 630 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 632 setOperationAction(ISD::DECLARE, MVT::Other, Expand); 633 634 setStackPointerRegisterToSaveRestore(SP::O6); 635 636 if (TM.getSubtarget<SparcSubtarget>().isV9()) 637 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 638 639 computeRegisterProperties(); 640} 641 642const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 643 switch (Opcode) { 644 default: return 0; 645 case SPISD::CMPICC: return "SPISD::CMPICC"; 646 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 647 case SPISD::BRICC: return "SPISD::BRICC"; 648 case SPISD::BRFCC: return "SPISD::BRFCC"; 649 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 650 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 651 case SPISD::Hi: return "SPISD::Hi"; 652 case SPISD::Lo: return "SPISD::Lo"; 653 case SPISD::FTOI: return "SPISD::FTOI"; 654 case SPISD::ITOF: return "SPISD::ITOF"; 655 case SPISD::CALL: return "SPISD::CALL"; 656 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 657 } 658} 659 660/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 661/// be zero. Op is expected to be a target specific node. Used by DAG 662/// combiner. 663void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 664 const APInt &Mask, 665 APInt &KnownZero, 666 APInt &KnownOne, 667 const SelectionDAG &DAG, 668 unsigned Depth) const { 669 APInt KnownZero2, KnownOne2; 670 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 671 672 switch (Op.getOpcode()) { 673 default: break; 674 case SPISD::SELECT_ICC: 675 case SPISD::SELECT_FCC: 676 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 677 Depth+1); 678 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 679 Depth+1); 680 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 681 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 682 683 // Only known if known in both the LHS and RHS. 684 KnownOne &= KnownOne2; 685 KnownZero &= KnownZero2; 686 break; 687 } 688} 689 690// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 691// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 692static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 693 ISD::CondCode CC, unsigned &SPCC) { 694 if (isa<ConstantSDNode>(RHS) && 695 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 && 696 CC == ISD::SETNE && 697 ((LHS.getOpcode() == SPISD::SELECT_ICC && 698 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 699 (LHS.getOpcode() == SPISD::SELECT_FCC && 700 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 701 isa<ConstantSDNode>(LHS.getOperand(0)) && 702 isa<ConstantSDNode>(LHS.getOperand(1)) && 703 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 && 704 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) { 705 SDValue CMPCC = LHS.getOperand(3); 706 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 707 LHS = CMPCC.getOperand(0); 708 RHS = CMPCC.getOperand(1); 709 } 710} 711 712static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) { 713 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 714 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 715 SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 716 SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 717 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 718} 719 720static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) { 721 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 722 Constant *C = N->getConstVal(); 723 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 724 SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 725 SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 726 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 727} 728 729static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 730 // Convert the fp value to integer in an FP register. 731 assert(Op.getValueType() == MVT::i32); 732 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 733 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 734} 735 736static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 737 assert(Op.getOperand(0).getValueType() == MVT::i32); 738 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 739 // Convert the int value to FP in an FP register. 740 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 741} 742 743static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 744 SDValue Chain = Op.getOperand(0); 745 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 746 SDValue LHS = Op.getOperand(2); 747 SDValue RHS = Op.getOperand(3); 748 SDValue Dest = Op.getOperand(4); 749 unsigned Opc, SPCC = ~0U; 750 751 // If this is a br_cc of a "setcc", and if the setcc got lowered into 752 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 753 LookThroughSetCC(LHS, RHS, CC, SPCC); 754 755 // Get the condition flag. 756 SDValue CompareFlag; 757 if (LHS.getValueType() == MVT::i32) { 758 std::vector<MVT> VTs; 759 VTs.push_back(MVT::i32); 760 VTs.push_back(MVT::Flag); 761 SDValue Ops[2] = { LHS, RHS }; 762 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 763 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 764 Opc = SPISD::BRICC; 765 } else { 766 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 767 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 768 Opc = SPISD::BRFCC; 769 } 770 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 771 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 772} 773 774static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 775 SDValue LHS = Op.getOperand(0); 776 SDValue RHS = Op.getOperand(1); 777 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 778 SDValue TrueVal = Op.getOperand(2); 779 SDValue FalseVal = Op.getOperand(3); 780 unsigned Opc, SPCC = ~0U; 781 782 // If this is a select_cc of a "setcc", and if the setcc got lowered into 783 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 784 LookThroughSetCC(LHS, RHS, CC, SPCC); 785 786 SDValue CompareFlag; 787 if (LHS.getValueType() == MVT::i32) { 788 std::vector<MVT> VTs; 789 VTs.push_back(LHS.getValueType()); // subcc returns a value 790 VTs.push_back(MVT::Flag); 791 SDValue Ops[2] = { LHS, RHS }; 792 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 793 Opc = SPISD::SELECT_ICC; 794 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 795 } else { 796 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 797 Opc = SPISD::SELECT_FCC; 798 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 799 } 800 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 801 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 802} 803 804static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 805 SparcTargetLowering &TLI) { 806 // vastart just stores the address of the VarArgsFrameIndex slot into the 807 // memory location argument. 808 SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32, 809 DAG.getRegister(SP::I6, MVT::i32), 810 DAG.getConstant(TLI.getVarArgsFrameOffset(), 811 MVT::i32)); 812 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 813 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); 814} 815 816static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 817 SDNode *Node = Op.getNode(); 818 MVT VT = Node->getValueType(0); 819 SDValue InChain = Node->getOperand(0); 820 SDValue VAListPtr = Node->getOperand(1); 821 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 822 SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); 823 // Increment the pointer, VAList, to the next vaarg 824 SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, 825 DAG.getConstant(VT.getSizeInBits()/8, 826 MVT::i32)); 827 // Store the incremented VAList to the legalized pointer 828 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 829 VAListPtr, SV, 0); 830 // Load the actual argument out of the pointer VAList, unless this is an 831 // f64 load. 832 if (VT != MVT::f64) 833 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 834 835 // Otherwise, load it as i64, then do a bitconvert. 836 SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 837 838 // Bit-Convert the value to f64. 839 SDValue Ops[2] = { 840 DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 841 V.getValue(1) 842 }; 843 return DAG.getMergeValues(Ops, 2); 844} 845 846static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 847 SDValue Chain = Op.getOperand(0); // Legalize the chain. 848 SDValue Size = Op.getOperand(1); // Legalize the size. 849 850 unsigned SPReg = SP::O6; 851 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 852 SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 853 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 854 855 // The resultant pointer is actually 16 words from the bottom of the stack, 856 // to provide a register spill area. 857 SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 858 DAG.getConstant(96, MVT::i32)); 859 SDValue Ops[2] = { NewVal, Chain }; 860 return DAG.getMergeValues(Ops, 2); 861} 862 863 864SDValue SparcTargetLowering:: 865LowerOperation(SDValue Op, SelectionDAG &DAG) { 866 switch (Op.getOpcode()) { 867 default: assert(0 && "Should not custom lower this!"); 868 // Frame & Return address. Currently unimplemented 869 case ISD::RETURNADDR: return SDValue(); 870 case ISD::FRAMEADDR: return SDValue(); 871 case ISD::GlobalTLSAddress: 872 assert(0 && "TLS not implemented for Sparc."); 873 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 874 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG); 875 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 876 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 877 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 878 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 879 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 880 case ISD::VAARG: return LowerVAARG(Op, DAG); 881 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 882 case ISD::CALL: return LowerCALL(Op, DAG); 883 case ISD::RET: return LowerRET(Op, DAG); 884 } 885} 886 887MachineBasicBlock * 888SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 889 MachineBasicBlock *BB) { 890 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 891 unsigned BROpcode; 892 unsigned CC; 893 // Figure out the conditional branch opcode to use for this select_cc. 894 switch (MI->getOpcode()) { 895 default: assert(0 && "Unknown SELECT_CC!"); 896 case SP::SELECT_CC_Int_ICC: 897 case SP::SELECT_CC_FP_ICC: 898 case SP::SELECT_CC_DFP_ICC: 899 BROpcode = SP::BCOND; 900 break; 901 case SP::SELECT_CC_Int_FCC: 902 case SP::SELECT_CC_FP_FCC: 903 case SP::SELECT_CC_DFP_FCC: 904 BROpcode = SP::FBCOND; 905 break; 906 } 907 908 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 909 910 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 911 // control-flow pattern. The incoming instruction knows the destination vreg 912 // to set, the condition code register to branch on, the true/false values to 913 // select between, and a branch opcode to use. 914 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 915 MachineFunction::iterator It = BB; 916 ++It; 917 918 // thisMBB: 919 // ... 920 // TrueVal = ... 921 // [f]bCC copy1MBB 922 // fallthrough --> copy0MBB 923 MachineBasicBlock *thisMBB = BB; 924 MachineFunction *F = BB->getParent(); 925 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 926 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 927 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 928 F->insert(It, copy0MBB); 929 F->insert(It, sinkMBB); 930 // Update machine-CFG edges by transferring all successors of the current 931 // block to the new block which will contain the Phi node for the select. 932 sinkMBB->transferSuccessors(BB); 933 // Next, add the true and fallthrough blocks as its successors. 934 BB->addSuccessor(copy0MBB); 935 BB->addSuccessor(sinkMBB); 936 937 // copy0MBB: 938 // %FalseValue = ... 939 // # fallthrough to sinkMBB 940 BB = copy0MBB; 941 942 // Update machine-CFG edges 943 BB->addSuccessor(sinkMBB); 944 945 // sinkMBB: 946 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 947 // ... 948 BB = sinkMBB; 949 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 950 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 951 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 952 953 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 954 return BB; 955} 956 957