SparcISelLowering.h revision 7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPARC_ISELLOWERING_H
16#define SPARC_ISELLOWERING_H
17
18#include "Sparc.h"
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22  class SparcSubtarget;
23
24  namespace SPISD {
25    enum {
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27      CMPICC,      // Compare two GPR operands, set icc+xcc.
28      CMPFCC,      // Compare two FP operands, set fcc.
29      BRICC,       // Branch to dest on icc condition
30      BRXCC,       // Branch to dest on xcc condition (64-bit only).
31      BRFCC,       // Branch to dest on fcc condition
32      SELECT_ICC,  // Select between two values using the current ICC flags.
33      SELECT_XCC,  // Select between two values using the current XCC flags.
34      SELECT_FCC,  // Select between two values using the current FCC flags.
35
36      Hi, Lo,      // Hi/Lo operations, typically on a global address.
37
38      FTOI,        // FP to Int within a FP register.
39      ITOF,        // Int to FP within a FP register.
40      FTOX,        // FP to Int64 within a FP register.
41      XTOF,        // Int64 to FP within a FP register.
42
43      CALL,        // A call instruction.
44      RET_FLAG,    // Return with a flag operand.
45      GLOBAL_BASE_REG, // Global base reg for PIC.
46      FLUSHW,      // FLUSH register windows to stack.
47
48      TLS_ADD,     // For Thread Local Storage (TLS).
49      TLS_LD,
50      TLS_CALL
51    };
52  }
53
54  class SparcTargetLowering : public TargetLowering {
55    const SparcSubtarget *Subtarget;
56  public:
57    SparcTargetLowering(TargetMachine &TM);
58    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
59
60    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
61    /// in Mask are known to be either zero or one and return them in the
62    /// KnownZero/KnownOne bitsets.
63    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
64                                                APInt &KnownZero,
65                                                APInt &KnownOne,
66                                                const SelectionDAG &DAG,
67                                                unsigned Depth = 0) const;
68
69    virtual MachineBasicBlock *
70      EmitInstrWithCustomInserter(MachineInstr *MI,
71                                  MachineBasicBlock *MBB) const;
72
73    virtual const char *getTargetNodeName(unsigned Opcode) const;
74
75    ConstraintType getConstraintType(const std::string &Constraint) const;
76    std::pair<unsigned, const TargetRegisterClass*>
77    getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
78
79    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
80    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
81
82    /// getSetCCResultType - Return the ISD::SETCC ValueType
83    virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
84
85    virtual SDValue
86      LowerFormalArguments(SDValue Chain,
87                           CallingConv::ID CallConv,
88                           bool isVarArg,
89                           const SmallVectorImpl<ISD::InputArg> &Ins,
90                           SDLoc dl, SelectionDAG &DAG,
91                           SmallVectorImpl<SDValue> &InVals) const;
92    SDValue LowerFormalArguments_32(SDValue Chain,
93                                    CallingConv::ID CallConv,
94                                    bool isVarArg,
95                                    const SmallVectorImpl<ISD::InputArg> &Ins,
96                                    SDLoc dl, SelectionDAG &DAG,
97                                    SmallVectorImpl<SDValue> &InVals) const;
98    SDValue LowerFormalArguments_64(SDValue Chain,
99                                    CallingConv::ID CallConv,
100                                    bool isVarArg,
101                                    const SmallVectorImpl<ISD::InputArg> &Ins,
102                                    SDLoc dl, SelectionDAG &DAG,
103                                    SmallVectorImpl<SDValue> &InVals) const;
104
105    virtual SDValue
106      LowerCall(TargetLowering::CallLoweringInfo &CLI,
107                SmallVectorImpl<SDValue> &InVals) const;
108    SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
109                         SmallVectorImpl<SDValue> &InVals) const;
110    SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
111                         SmallVectorImpl<SDValue> &InVals) const;
112
113    virtual SDValue
114      LowerReturn(SDValue Chain,
115                  CallingConv::ID CallConv, bool isVarArg,
116                  const SmallVectorImpl<ISD::OutputArg> &Outs,
117                  const SmallVectorImpl<SDValue> &OutVals,
118                  SDLoc dl, SelectionDAG &DAG) const;
119    SDValue LowerReturn_32(SDValue Chain,
120                           CallingConv::ID CallConv, bool IsVarArg,
121                           const SmallVectorImpl<ISD::OutputArg> &Outs,
122                           const SmallVectorImpl<SDValue> &OutVals,
123                           SDLoc DL, SelectionDAG &DAG) const;
124    SDValue LowerReturn_64(SDValue Chain,
125                           CallingConv::ID CallConv, bool IsVarArg,
126                           const SmallVectorImpl<ISD::OutputArg> &Outs,
127                           const SmallVectorImpl<SDValue> &OutVals,
128                           SDLoc DL, SelectionDAG &DAG) const;
129
130    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
131    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
132    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
133    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
134
135    unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
136    SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
137    SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
138                         SelectionDAG &DAG) const;
139    SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
140
141    SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
142                                 SDValue Arg, SDLoc DL,
143                                 SelectionDAG &DAG) const;
144    SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
145                        const char *LibFuncName,
146                        unsigned numArgs) const;
147    SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
148                             unsigned &SPCC,
149                             SDLoc DL,
150                             SelectionDAG &DAG) const;
151
152    bool ShouldShrinkFPConstant(EVT VT) const {
153      // Do not shrink FP constpool if VT == MVT::f128.
154      // (ldd, call _Q_fdtoq) is more expensive than two ldds.
155      return VT != MVT::f128;
156    }
157
158    virtual void ReplaceNodeResults(SDNode *N,
159                                    SmallVectorImpl<SDValue>& Results,
160                                    SelectionDAG &DAG) const;
161  };
162} // end namespace llvm
163
164#endif    // SPARC_ISELLOWERING_H
165