SparcISelLowering.h revision db486a6d5311944f61b92db9f6074944dbbdb242 
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPARC_ISELLOWERING_H
16#define SPARC_ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "Sparc.h"
20
21namespace llvm {
22  namespace SPISD {
23    enum {
24      FIRST_NUMBER = ISD::BUILTIN_OP_END,
25      CMPICC,      // Compare two GPR operands, set icc.
26      CMPFCC,      // Compare two FP operands, set fcc.
27      BRICC,       // Branch to dest on icc condition
28      BRFCC,       // Branch to dest on fcc condition
29      SELECT_ICC,  // Select between two values using the current ICC flags.
30      SELECT_FCC,  // Select between two values using the current FCC flags.
31
32      Hi, Lo,      // Hi/Lo operations, typically on a global address.
33
34      FTOI,        // FP to Int within a FP register.
35      ITOF,        // Int to FP within a FP register.
36
37      CALL,        // A call instruction.
38      RET_FLAG,    // Return with a flag operand.
39      GLOBAL_BASE_REG // Global base reg for PIC
40    };
41  }
42
43  class SparcTargetLowering : public TargetLowering {
44    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
45  public:
46    SparcTargetLowering(TargetMachine &TM);
47    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
48
49    int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
50
51    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
52    /// in Mask are known to be either zero or one and return them in the
53    /// KnownZero/KnownOne bitsets.
54    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
55                                                const APInt &Mask,
56                                                APInt &KnownZero,
57                                                APInt &KnownOne,
58                                                const SelectionDAG &DAG,
59                                                unsigned Depth = 0) const;
60
61    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
62                                                   MachineBasicBlock *MBB) const;
63
64    virtual const char *getTargetNodeName(unsigned Opcode) const;
65
66    ConstraintType getConstraintType(const std::string &Constraint) const;
67    std::pair<unsigned, const TargetRegisterClass*>
68    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
69    std::vector<unsigned>
70    getRegClassForInlineAsmConstraint(const std::string &Constraint,
71                                      EVT VT) const;
72
73    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
74
75    /// getFunctionAlignment - Return the Log2 alignment of this function.
76    virtual unsigned getFunctionAlignment(const Function *F) const;
77
78    virtual SDValue
79      LowerFormalArguments(SDValue Chain,
80                           CallingConv::ID CallConv,
81                           bool isVarArg,
82                           const SmallVectorImpl<ISD::InputArg> &Ins,
83                           DebugLoc dl, SelectionDAG &DAG,
84                           SmallVectorImpl<SDValue> &InVals);
85
86    virtual SDValue
87      LowerCall(SDValue Chain, SDValue Callee,
88                CallingConv::ID CallConv, bool isVarArg,
89                bool isTailCall,
90                const SmallVectorImpl<ISD::OutputArg> &Outs,
91                const SmallVectorImpl<ISD::InputArg> &Ins,
92                DebugLoc dl, SelectionDAG &DAG,
93                SmallVectorImpl<SDValue> &InVals);
94
95    virtual SDValue
96      LowerReturn(SDValue Chain,
97                  CallingConv::ID CallConv, bool isVarArg,
98                  const SmallVectorImpl<ISD::OutputArg> &Outs,
99                  DebugLoc dl, SelectionDAG &DAG);
100
101    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
102    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
103  };
104} // end namespace llvm
105
106#endif    // SPARC_ISELLOWERING_H
107