SparcISelLowering.h revision f37812e906a3abbdb8353e2eb9e8223ff9036b68 
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPARC_ISELLOWERING_H
16#define SPARC_ISELLOWERING_H
17
18#include "Sparc.h"
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22  class SparcSubtarget;
23
24  namespace SPISD {
25    enum {
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27      CMPICC,      // Compare two GPR operands, set icc.
28      CMPFCC,      // Compare two FP operands, set fcc.
29      BRICC,       // Branch to dest on icc condition
30      BRFCC,       // Branch to dest on fcc condition
31      SELECT_ICC,  // Select between two values using the current ICC flags.
32      SELECT_FCC,  // Select between two values using the current FCC flags.
33
34      Hi, Lo,      // Hi/Lo operations, typically on a global address.
35
36      FTOI,        // FP to Int within a FP register.
37      ITOF,        // Int to FP within a FP register.
38
39      CALL,        // A call instruction.
40      RET_FLAG,    // Return with a flag operand.
41      GLOBAL_BASE_REG, // Global base reg for PIC
42      FLUSHW       // FLUSH register windows to stack
43    };
44  }
45
46  class SparcTargetLowering : public TargetLowering {
47    const SparcSubtarget *Subtarget;
48  public:
49    SparcTargetLowering(TargetMachine &TM);
50    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
51
52    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
53    /// in Mask are known to be either zero or one and return them in the
54    /// KnownZero/KnownOne bitsets.
55    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
56                                                APInt &KnownZero,
57                                                APInt &KnownOne,
58                                                const SelectionDAG &DAG,
59                                                unsigned Depth = 0) const;
60
61    virtual MachineBasicBlock *
62      EmitInstrWithCustomInserter(MachineInstr *MI,
63                                  MachineBasicBlock *MBB) const;
64
65    virtual const char *getTargetNodeName(unsigned Opcode) const;
66
67    ConstraintType getConstraintType(const std::string &Constraint) const;
68    std::pair<unsigned, const TargetRegisterClass*>
69    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
70
71    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
72
73    virtual SDValue
74      LowerFormalArguments(SDValue Chain,
75                           CallingConv::ID CallConv,
76                           bool isVarArg,
77                           const SmallVectorImpl<ISD::InputArg> &Ins,
78                           DebugLoc dl, SelectionDAG &DAG,
79                           SmallVectorImpl<SDValue> &InVals) const;
80    SDValue LowerFormalArguments_32(SDValue Chain,
81                                    CallingConv::ID CallConv,
82                                    bool isVarArg,
83                                    const SmallVectorImpl<ISD::InputArg> &Ins,
84                                    DebugLoc dl, SelectionDAG &DAG,
85                                    SmallVectorImpl<SDValue> &InVals) const;
86    SDValue LowerFormalArguments_64(SDValue Chain,
87                                    CallingConv::ID CallConv,
88                                    bool isVarArg,
89                                    const SmallVectorImpl<ISD::InputArg> &Ins,
90                                    DebugLoc dl, SelectionDAG &DAG,
91                                    SmallVectorImpl<SDValue> &InVals) const;
92
93    virtual SDValue
94      LowerCall(TargetLowering::CallLoweringInfo &CLI,
95                SmallVectorImpl<SDValue> &InVals) const;
96
97    virtual SDValue
98      LowerReturn(SDValue Chain,
99                  CallingConv::ID CallConv, bool isVarArg,
100                  const SmallVectorImpl<ISD::OutputArg> &Outs,
101                  const SmallVectorImpl<SDValue> &OutVals,
102                  DebugLoc dl, SelectionDAG &DAG) const;
103
104    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
105    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
106
107    unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
108  };
109} // end namespace llvm
110
111#endif    // SPARC_ISELLOWERING_H
112