SparcInstr64Bit.td revision 53d4bcf35e7bc362e9340085264c2f4acd3c912b 
1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains instruction definitions and patterns needed for 64-bit
11// code generation on SPARC v9.
12//
13// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
14// also be used in 32-bit code running on a SPARC v9 CPU.
15//
16//===----------------------------------------------------------------------===//
17
18let Predicates = [Is64Bit] in {
19// The same integer registers are used for i32 and i64 values.
20// When registers hold i32 values, the high bits are don't care.
21// This give us free trunc and anyext.
22def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
24
25} // Predicates = [Is64Bit]
26
27
28//===----------------------------------------------------------------------===//
29// 64-bit Shift Instructions.
30//===----------------------------------------------------------------------===//
31//
32// The 32-bit shift instructions are still available. The left shift srl
33// instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
34//
35// The srl instructions only shift the low 32 bits and clear the high 32 bits.
36// Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
37
38let Predicates = [Is64Bit] in {
39
40def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
42
43def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
45
46defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
47defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
48defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
49
50} // Predicates = [Is64Bit]
51
52
53//===----------------------------------------------------------------------===//
54// 64-bit Immediates.
55//===----------------------------------------------------------------------===//
56//
57// All 32-bit immediates can be materialized with sethi+or, but 64-bit
58// immediates may require more code. There may be a point where it is
59// preferable to use a constant pool load instead, depending on the
60// microarchitecture.
61
62// The %g0 register is constant 0.
63// This is useful for stx %g0, [...], for example.
64def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>;
65
66// Single-instruction patterns.
67
68// The ALU instructions want their simm13 operands as i32 immediates.
69def as_i32imm : SDNodeXForm<imm, [{
70  return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
71}]>;
72def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
73def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
74
75// Double-instruction patterns.
76
77// All unsigned i32 immediates can be handled by sethi+or.
78def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
79def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
80      Requires<[Is64Bit]>;
81
82// All negative i33 immediates can be handled by sethi+xor.
83def nimm33 : PatLeaf<(imm), [{
84  int64_t Imm = N->getSExtValue();
85  return Imm < 0 && isInt<33>(Imm);
86}]>;
87// Bits 10-31 inverted. Same as assembler's %hix.
88def HIX22 : SDNodeXForm<imm, [{
89  uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
90  return CurDAG->getTargetConstant(Val, MVT::i32);
91}]>;
92// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
93def LOX10 : SDNodeXForm<imm, [{
94  return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
95}]>;
96def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
97      Requires<[Is64Bit]>;
98
99// More possible patterns:
100//
101//   (sllx sethi, n)
102//   (sllx simm13, n)
103//
104// 3 instrs:
105//
106//   (xor (sllx sethi), simm13)
107//   (sllx (xor sethi, simm13))
108//
109// 4 instrs:
110//
111//   (or sethi, (sllx sethi))
112//   (xnor sethi, (sllx sethi))
113//
114// 5 instrs:
115//
116//   (or (sllx sethi), (or sethi, simm13))
117//   (xnor (sllx sethi), (or sethi, simm13))
118//   (or (sllx sethi), (sllx sethi))
119//   (xnor (sllx sethi), (sllx sethi))
120//
121// Worst case is 6 instrs:
122//
123//   (or (sllx (or sethi, simmm13)), (or sethi, simm13))
124
125// Bits 42-63, same as assembler's %hh.
126def HH22 : SDNodeXForm<imm, [{
127  uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
128  return CurDAG->getTargetConstant(Val, MVT::i32);
129}]>;
130// Bits 32-41, same as assembler's %hm.
131def HM10 : SDNodeXForm<imm, [{
132  uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
133  return CurDAG->getTargetConstant(Val, MVT::i32);
134}]>;
135def : Pat<(i64 imm:$val),
136          (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
137                (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
138      Requires<[Is64Bit]>;
139
140
141//===----------------------------------------------------------------------===//
142// 64-bit Integer Arithmetic and Logic.
143//===----------------------------------------------------------------------===//
144
145let Predicates = [Is64Bit] in {
146
147// Register-register instructions.
148
149def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
150def : Pat<(or  i64:$a, i64:$b), (ORrr  $a, $b)>;
151def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
152
153def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
154def : Pat<(or  i64:$a, (not i64:$b)), (ORNrr  $a, $b)>;
155def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
156
157def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
158def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
159
160// Add/sub with carry were renamed to addc/subc in SPARC v9.
161def : Pat<(adde i64:$a, i64:$b), (ADDXrr $a, $b)>;
162def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
163
164def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
165def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
166
167def : Pat<(SPcmpicc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
168
169// Register-immediate instructions.
170
171def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
172def : Pat<(or  i64:$a, (i64 simm13:$b)), (ORri  $a, (as_i32imm $b))>;
173def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
174
175def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
176def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
177
178def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (SUBCCri $a, (as_i32imm $b))>;
179
180} // Predicates = [Is64Bit]
181
182
183//===----------------------------------------------------------------------===//
184// 64-bit Loads and Stores.
185//===----------------------------------------------------------------------===//
186//
187// All the 32-bit loads and stores are available. The extending loads are sign
188// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
189// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
190// Word).
191//
192// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
193
194let Predicates = [Is64Bit] in {
195
196// 64-bit loads.
197def LDXrr  : F3_1<3, 0b001011,
198                  (outs I64Regs:$dst), (ins MEMrr:$addr),
199                  "ldx [$addr], $dst",
200                  [(set i64:$dst, (load ADDRrr:$addr))]>;
201def LDXri  : F3_2<3, 0b001011,
202                  (outs I64Regs:$dst), (ins MEMri:$addr),
203                  "ldx [$addr], $dst",
204                  [(set i64:$dst, (load ADDRri:$addr))]>;
205
206// Extending loads to i64.
207def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
208def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
209def : Pat<(i64 (extloadi8 ADDRrr:$addr)),  (LDUBrr ADDRrr:$addr)>;
210def : Pat<(i64 (extloadi8 ADDRri:$addr)),  (LDUBri ADDRri:$addr)>;
211def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
212def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
213
214def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
215def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
216def : Pat<(i64 (extloadi16 ADDRrr:$addr)),  (LDUHrr ADDRrr:$addr)>;
217def : Pat<(i64 (extloadi16 ADDRri:$addr)),  (LDUHri ADDRri:$addr)>;
218def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
219def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
220
221def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
222def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
223def : Pat<(i64 (extloadi32 ADDRrr:$addr)),  (LDrr ADDRrr:$addr)>;
224def : Pat<(i64 (extloadi32 ADDRri:$addr)),  (LDri ADDRri:$addr)>;
225
226// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
227def LDSWrr : F3_1<3, 0b001011,
228                 (outs I64Regs:$dst), (ins MEMrr:$addr),
229                 "ldsw [$addr], $dst",
230                 [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
231def LDSWri : F3_2<3, 0b001011,
232                 (outs I64Regs:$dst), (ins MEMri:$addr),
233                 "ldsw [$addr], $dst",
234                 [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
235
236// 64-bit stores.
237def STXrr  : F3_1<3, 0b001110,
238                 (outs), (ins MEMrr:$addr, I64Regs:$src),
239                 "stx $src, [$addr]",
240                 [(store i64:$src, ADDRrr:$addr)]>;
241def STXri  : F3_2<3, 0b001110,
242                 (outs), (ins MEMri:$addr, I64Regs:$src),
243                 "stx $src, [$addr]",
244                 [(store i64:$src, ADDRri:$addr)]>;
245
246// Truncating stores from i64 are identical to the i32 stores.
247def : Pat<(truncstorei8  i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
248def : Pat<(truncstorei8  i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
249def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
250def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
251def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr  ADDRrr:$addr, $src)>;
252def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri  ADDRri:$addr, $src)>;
253
254} // Predicates = [Is64Bit]
255
256
257//===----------------------------------------------------------------------===//
258// 64-bit Conditionals.
259//===----------------------------------------------------------------------===//
260//
261// Flag-setting instructions like subcc and addcc set both icc and xcc flags.
262// The icc flags correspond to the 32-bit result, and the xcc are for the
263// full 64-bit result.
264//
265// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
266// 64-bit compares. See LowerBR_CC.
267
268let Predicates = [Is64Bit] in {
269
270let Uses = [ICC] in
271def BPXCC : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
272                     "bp$cc %xcc, $dst",
273                     [(SPbrxcc bb:$dst, imm:$cc)]>;
274
275// Conditional moves on %xcc.
276let Uses = [ICC], Constraints = "$f = $rd" in {
277def MOVXCCrr : Pseudo<(outs IntRegs:$rd),
278                      (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
279                      "mov$cond %xcc, $rs2, $rd",
280                      [(set i32:$rd,
281                       (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
282def MOVXCCri : Pseudo<(outs IntRegs:$rd),
283                      (ins i32imm:$i, IntRegs:$f, CCOp:$cond),
284                      "mov$cond %xcc, $i, $rd",
285                      [(set i32:$rd,
286                       (SPselecticc simm11:$i, i32:$f, imm:$cond))]>;
287} // Uses, Constraints
288
289def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
290          (MOVXCCrr $t, $f, imm:$cond)>;
291def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
292          (MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
293
294} // Predicates = [Is64Bit]
295