SparcInstrInfo.cpp revision 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 
1//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Sparc implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcInstrInfo.h"
15#include "SparcSubtarget.h"
16#include "Sparc.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "SparcGenInstrInfo.inc"
21using namespace llvm;
22
23SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
24  : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
25    RI(ST, *this), Subtarget(ST) {
26}
27
28static bool isZeroImm(const MachineOperand &op) {
29  return op.isImm() && op.getImm() == 0;
30}
31
32/// Return true if the instruction is a register to register move and
33/// leave the source and dest operands in the passed parameters.
34///
35bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
36                                 unsigned &SrcReg, unsigned &DstReg,
37                                 unsigned &SrcSR, unsigned &DstSR) const {
38  SrcSR = DstSR = 0; // No sub-registers.
39
40  // We look for 3 kinds of patterns here:
41  // or with G0 or 0
42  // add with G0 or 0
43  // fmovs or FpMOVD (pseudo double move).
44  if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
45    if (MI.getOperand(1).getReg() == SP::G0) {
46      DstReg = MI.getOperand(0).getReg();
47      SrcReg = MI.getOperand(2).getReg();
48      return true;
49    } else if (MI.getOperand(2).getReg() == SP::G0) {
50      DstReg = MI.getOperand(0).getReg();
51      SrcReg = MI.getOperand(1).getReg();
52      return true;
53    }
54  } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
55             isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
56    DstReg = MI.getOperand(0).getReg();
57    SrcReg = MI.getOperand(1).getReg();
58    return true;
59  } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
60             MI.getOpcode() == SP::FMOVD) {
61    SrcReg = MI.getOperand(1).getReg();
62    DstReg = MI.getOperand(0).getReg();
63    return true;
64  }
65  return false;
66}
67
68/// isLoadFromStackSlot - If the specified machine instruction is a direct
69/// load from a stack slot, return the virtual or physical register number of
70/// the destination along with the FrameIndex of the loaded stack slot.  If
71/// not, return 0.  This predicate must return 0 if the instruction has
72/// any side effects other than loading from the stack slot.
73unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74                                             int &FrameIndex) const {
75  if (MI->getOpcode() == SP::LDri ||
76      MI->getOpcode() == SP::LDFri ||
77      MI->getOpcode() == SP::LDDFri) {
78    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
79        MI->getOperand(2).getImm() == 0) {
80      FrameIndex = MI->getOperand(1).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83  }
84  return 0;
85}
86
87/// isStoreToStackSlot - If the specified machine instruction is a direct
88/// store to a stack slot, return the virtual or physical register number of
89/// the source reg along with the FrameIndex of the loaded stack slot.  If
90/// not, return 0.  This predicate must return 0 if the instruction has
91/// any side effects other than storing to the stack slot.
92unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
93                                            int &FrameIndex) const {
94  if (MI->getOpcode() == SP::STri ||
95      MI->getOpcode() == SP::STFri ||
96      MI->getOpcode() == SP::STDFri) {
97    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
98        MI->getOperand(1).getImm() == 0) {
99      FrameIndex = MI->getOperand(0).getIndex();
100      return MI->getOperand(2).getReg();
101    }
102  }
103  return 0;
104}
105
106unsigned
107SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
108                             MachineBasicBlock *FBB,
109                             const SmallVectorImpl<MachineOperand> &Cond)const{
110  // Can only insert uncond branches so far.
111  assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
112  BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
113  return 1;
114}
115
116bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
117                                     MachineBasicBlock::iterator I,
118                                     unsigned DestReg, unsigned SrcReg,
119                                     const TargetRegisterClass *DestRC,
120                                     const TargetRegisterClass *SrcRC) const {
121  if (DestRC != SrcRC) {
122    // Not yet supported!
123    return false;
124  }
125
126  if (DestRC == SP::IntRegsRegisterClass)
127    BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
128  else if (DestRC == SP::FPRegsRegisterClass)
129    BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg);
130  else if (DestRC == SP::DFPRegsRegisterClass)
131    BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
132      .addReg(SrcReg);
133  else
134    // Can't copy this register
135    return false;
136
137  return true;
138}
139
140void SparcInstrInfo::
141storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
142                    unsigned SrcReg, bool isKill, int FI,
143                    const TargetRegisterClass *RC) const {
144  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
145  if (RC == SP::IntRegsRegisterClass)
146    BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0)
147      .addReg(SrcReg, false, false, isKill);
148  else if (RC == SP::FPRegsRegisterClass)
149    BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0)
150      .addReg(SrcReg, false, false, isKill);
151  else if (RC == SP::DFPRegsRegisterClass)
152    BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
153      .addReg(SrcReg, false, false, isKill);
154  else
155    assert(0 && "Can't store this register to stack slot");
156}
157
158void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
159                                       bool isKill,
160                                       SmallVectorImpl<MachineOperand> &Addr,
161                                       const TargetRegisterClass *RC,
162                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
163  unsigned Opc = 0;
164  if (RC == SP::IntRegsRegisterClass)
165    Opc = SP::STri;
166  else if (RC == SP::FPRegsRegisterClass)
167    Opc = SP::STFri;
168  else if (RC == SP::DFPRegsRegisterClass)
169    Opc = SP::STDFri;
170  else
171    assert(0 && "Can't load this register");
172  MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
173  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
174    MachineOperand &MO = Addr[i];
175    if (MO.isReg())
176      MIB.addReg(MO.getReg());
177    else if (MO.isImm())
178      MIB.addImm(MO.getImm());
179    else {
180      assert(MO.isFI());
181      MIB.addFrameIndex(MO.getIndex());
182    }
183  }
184  MIB.addReg(SrcReg, false, false, isKill);
185  NewMIs.push_back(MIB);
186  return;
187}
188
189void SparcInstrInfo::
190loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
191                     unsigned DestReg, int FI,
192                     const TargetRegisterClass *RC) const {
193  if (RC == SP::IntRegsRegisterClass)
194    BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
195  else if (RC == SP::FPRegsRegisterClass)
196    BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
197  else if (RC == SP::DFPRegsRegisterClass)
198    BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
199  else
200    assert(0 && "Can't load this register from stack slot");
201}
202
203void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
204                                        SmallVectorImpl<MachineOperand> &Addr,
205                                        const TargetRegisterClass *RC,
206                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
207  unsigned Opc = 0;
208  if (RC == SP::IntRegsRegisterClass)
209    Opc = SP::LDri;
210  else if (RC == SP::FPRegsRegisterClass)
211    Opc = SP::LDFri;
212  else if (RC == SP::DFPRegsRegisterClass)
213    Opc = SP::LDDFri;
214  else
215    assert(0 && "Can't load this register");
216  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
217  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
218    MachineOperand &MO = Addr[i];
219    if (MO.isReg())
220      MIB.addReg(MO.getReg());
221    else if (MO.isImm())
222      MIB.addImm(MO.getImm());
223    else {
224      assert(MO.isFI());
225      MIB.addFrameIndex(MO.getIndex());
226    }
227  }
228  NewMIs.push_back(MIB);
229  return;
230}
231
232MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
233                                                    MachineInstr* MI,
234                                          const SmallVectorImpl<unsigned> &Ops,
235                                                    int FI) const {
236  if (Ops.size() != 1) return NULL;
237
238  unsigned OpNum = Ops[0];
239  bool isFloat = false;
240  MachineInstr *NewMI = NULL;
241  switch (MI->getOpcode()) {
242  case SP::ORrr:
243    if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
244        MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
245      if (OpNum == 0)    // COPY -> STORE
246        NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
247                                   .addReg(MI->getOperand(2).getReg());
248      else               // COPY -> LOAD
249        NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg())
250                      .addFrameIndex(FI).addImm(0);
251    }
252    break;
253  case SP::FMOVS:
254    isFloat = true;
255    // FALLTHROUGH
256  case SP::FMOVD:
257    if (OpNum == 0) { // COPY -> STORE
258      unsigned SrcReg = MI->getOperand(1).getReg();
259      bool isKill = MI->getOperand(1).isKill();
260      NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri))
261        .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
262    } else {             // COPY -> LOAD
263      unsigned DstReg = MI->getOperand(0).getReg();
264      bool isDead = MI->getOperand(0).isDead();
265      NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri))
266        .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);
267    }
268    break;
269  }
270
271  return NewMI;
272}
273