SparcInstrInfo.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Sparc implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcInstrInfo.h"
15#include "Sparc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcSubtarget.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineMemOperand.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/TargetRegistry.h"
26
27#define GET_INSTRINFO_CTOR_DTOR
28#include "SparcGenInstrInfo.inc"
29
30using namespace llvm;
31
32
33// Pin the vtable to this file.
34void SparcInstrInfo::anchor() {}
35
36SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
37  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
38    RI(ST), Subtarget(ST) {
39}
40
41/// isLoadFromStackSlot - If the specified machine instruction is a direct
42/// load from a stack slot, return the virtual or physical register number of
43/// the destination along with the FrameIndex of the loaded stack slot.  If
44/// not, return 0.  This predicate must return 0 if the instruction has
45/// any side effects other than loading from the stack slot.
46unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
47                                             int &FrameIndex) const {
48  if (MI->getOpcode() == SP::LDri ||
49      MI->getOpcode() == SP::LDXri ||
50      MI->getOpcode() == SP::LDFri ||
51      MI->getOpcode() == SP::LDDFri ||
52      MI->getOpcode() == SP::LDQFri) {
53    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
54        MI->getOperand(2).getImm() == 0) {
55      FrameIndex = MI->getOperand(1).getIndex();
56      return MI->getOperand(0).getReg();
57    }
58  }
59  return 0;
60}
61
62/// isStoreToStackSlot - If the specified machine instruction is a direct
63/// store to a stack slot, return the virtual or physical register number of
64/// the source reg along with the FrameIndex of the loaded stack slot.  If
65/// not, return 0.  This predicate must return 0 if the instruction has
66/// any side effects other than storing to the stack slot.
67unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
68                                            int &FrameIndex) const {
69  if (MI->getOpcode() == SP::STri ||
70      MI->getOpcode() == SP::STXri ||
71      MI->getOpcode() == SP::STFri ||
72      MI->getOpcode() == SP::STDFri ||
73      MI->getOpcode() == SP::STQFri) {
74    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
75        MI->getOperand(1).getImm() == 0) {
76      FrameIndex = MI->getOperand(0).getIndex();
77      return MI->getOperand(2).getReg();
78    }
79  }
80  return 0;
81}
82
83static bool IsIntegerCC(unsigned CC)
84{
85  return  (CC <= SPCC::ICC_VC);
86}
87
88
89static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
90{
91  switch(CC) {
92  case SPCC::ICC_A:    return SPCC::ICC_N;
93  case SPCC::ICC_N:    return SPCC::ICC_A;
94  case SPCC::ICC_NE:   return SPCC::ICC_E;
95  case SPCC::ICC_E:    return SPCC::ICC_NE;
96  case SPCC::ICC_G:    return SPCC::ICC_LE;
97  case SPCC::ICC_LE:   return SPCC::ICC_G;
98  case SPCC::ICC_GE:   return SPCC::ICC_L;
99  case SPCC::ICC_L:    return SPCC::ICC_GE;
100  case SPCC::ICC_GU:   return SPCC::ICC_LEU;
101  case SPCC::ICC_LEU:  return SPCC::ICC_GU;
102  case SPCC::ICC_CC:   return SPCC::ICC_CS;
103  case SPCC::ICC_CS:   return SPCC::ICC_CC;
104  case SPCC::ICC_POS:  return SPCC::ICC_NEG;
105  case SPCC::ICC_NEG:  return SPCC::ICC_POS;
106  case SPCC::ICC_VC:   return SPCC::ICC_VS;
107  case SPCC::ICC_VS:   return SPCC::ICC_VC;
108
109  case SPCC::FCC_A:    return SPCC::FCC_N;
110  case SPCC::FCC_N:    return SPCC::FCC_A;
111  case SPCC::FCC_U:    return SPCC::FCC_O;
112  case SPCC::FCC_O:    return SPCC::FCC_U;
113  case SPCC::FCC_G:    return SPCC::FCC_ULE;
114  case SPCC::FCC_LE:   return SPCC::FCC_UG;
115  case SPCC::FCC_UG:   return SPCC::FCC_LE;
116  case SPCC::FCC_ULE:  return SPCC::FCC_G;
117  case SPCC::FCC_L:    return SPCC::FCC_UGE;
118  case SPCC::FCC_GE:   return SPCC::FCC_UL;
119  case SPCC::FCC_UL:   return SPCC::FCC_GE;
120  case SPCC::FCC_UGE:  return SPCC::FCC_L;
121  case SPCC::FCC_LG:   return SPCC::FCC_UE;
122  case SPCC::FCC_UE:   return SPCC::FCC_LG;
123  case SPCC::FCC_NE:   return SPCC::FCC_E;
124  case SPCC::FCC_E:    return SPCC::FCC_NE;
125  }
126  llvm_unreachable("Invalid cond code");
127}
128
129bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
130                                   MachineBasicBlock *&TBB,
131                                   MachineBasicBlock *&FBB,
132                                   SmallVectorImpl<MachineOperand> &Cond,
133                                   bool AllowModify) const
134{
135
136  MachineBasicBlock::iterator I = MBB.end();
137  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
138  while (I != MBB.begin()) {
139    --I;
140
141    if (I->isDebugValue())
142      continue;
143
144    // When we see a non-terminator, we are done.
145    if (!isUnpredicatedTerminator(I))
146      break;
147
148    // Terminator is not a branch.
149    if (!I->isBranch())
150      return true;
151
152    // Handle Unconditional branches.
153    if (I->getOpcode() == SP::BA) {
154      UnCondBrIter = I;
155
156      if (!AllowModify) {
157        TBB = I->getOperand(0).getMBB();
158        continue;
159      }
160
161      while (std::next(I) != MBB.end())
162        std::next(I)->eraseFromParent();
163
164      Cond.clear();
165      FBB = 0;
166
167      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
168        TBB = 0;
169        I->eraseFromParent();
170        I = MBB.end();
171        UnCondBrIter = MBB.end();
172        continue;
173      }
174
175      TBB = I->getOperand(0).getMBB();
176      continue;
177    }
178
179    unsigned Opcode = I->getOpcode();
180    if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
181      return true; // Unknown Opcode.
182
183    SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
184
185    if (Cond.empty()) {
186      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
187      if (AllowModify && UnCondBrIter != MBB.end() &&
188          MBB.isLayoutSuccessor(TargetBB)) {
189
190        // Transform the code
191        //
192        //    brCC L1
193        //    ba L2
194        // L1:
195        //    ..
196        // L2:
197        //
198        // into
199        //
200        //   brnCC L2
201        // L1:
202        //   ...
203        // L2:
204        //
205        BranchCode = GetOppositeBranchCondition(BranchCode);
206        MachineBasicBlock::iterator OldInst = I;
207        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
208          .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
209        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
210          .addMBB(TargetBB);
211
212        OldInst->eraseFromParent();
213        UnCondBrIter->eraseFromParent();
214
215        UnCondBrIter = MBB.end();
216        I = MBB.end();
217        continue;
218      }
219      FBB = TBB;
220      TBB = I->getOperand(0).getMBB();
221      Cond.push_back(MachineOperand::CreateImm(BranchCode));
222      continue;
223    }
224    // FIXME: Handle subsequent conditional branches.
225    // For now, we can't handle multiple conditional branches.
226    return true;
227  }
228  return false;
229}
230
231unsigned
232SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
233                             MachineBasicBlock *FBB,
234                             const SmallVectorImpl<MachineOperand> &Cond,
235                             DebugLoc DL) const {
236  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
237  assert((Cond.size() == 1 || Cond.size() == 0) &&
238         "Sparc branch conditions should have one component!");
239
240  if (Cond.empty()) {
241    assert(!FBB && "Unconditional branch with multiple successors!");
242    BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
243    return 1;
244  }
245
246  // Conditional branch
247  unsigned CC = Cond[0].getImm();
248
249  if (IsIntegerCC(CC))
250    BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
251  else
252    BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
253  if (!FBB)
254    return 1;
255
256  BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
257  return 2;
258}
259
260unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
261{
262  MachineBasicBlock::iterator I = MBB.end();
263  unsigned Count = 0;
264  while (I != MBB.begin()) {
265    --I;
266
267    if (I->isDebugValue())
268      continue;
269
270    if (I->getOpcode() != SP::BA
271        && I->getOpcode() != SP::BCOND
272        && I->getOpcode() != SP::FBCOND)
273      break; // Not a branch
274
275    I->eraseFromParent();
276    I = MBB.end();
277    ++Count;
278  }
279  return Count;
280}
281
282void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
283                                 MachineBasicBlock::iterator I, DebugLoc DL,
284                                 unsigned DestReg, unsigned SrcReg,
285                                 bool KillSrc) const {
286  unsigned numSubRegs = 0;
287  unsigned movOpc     = 0;
288  const unsigned *subRegIdx = 0;
289
290  const unsigned DFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };
291  const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
292  const unsigned QFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd,
293                                          SP::sub_odd64_then_sub_even,
294                                          SP::sub_odd64_then_sub_odd };
295
296  if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
297    BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
298      .addReg(SrcReg, getKillRegState(KillSrc));
299  else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
300    BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
301      .addReg(SrcReg, getKillRegState(KillSrc));
302  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
303    if (Subtarget.isV9()) {
304      BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
305        .addReg(SrcReg, getKillRegState(KillSrc));
306    } else {
307      // Use two FMOVS instructions.
308      subRegIdx  = DFP_FP_SubRegsIdx;
309      numSubRegs = 2;
310      movOpc     = SP::FMOVS;
311    }
312  } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
313    if (Subtarget.isV9()) {
314      if (Subtarget.hasHardQuad()) {
315        BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
316          .addReg(SrcReg, getKillRegState(KillSrc));
317      } else {
318        // Use two FMOVD instructions.
319        subRegIdx  = QFP_DFP_SubRegsIdx;
320        numSubRegs = 2;
321        movOpc     = SP::FMOVD;
322      }
323    } else {
324      // Use four FMOVS instructions.
325      subRegIdx  = QFP_FP_SubRegsIdx;
326      numSubRegs = 4;
327      movOpc     = SP::FMOVS;
328    }
329  } else
330    llvm_unreachable("Impossible reg-to-reg copy");
331
332  if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0)
333    return;
334
335  const TargetRegisterInfo *TRI = &getRegisterInfo();
336  MachineInstr *MovMI = 0;
337
338  for (unsigned i = 0; i != numSubRegs; ++i) {
339    unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
340    unsigned Src = TRI->getSubReg(SrcReg,  subRegIdx[i]);
341    assert(Dst && Src && "Bad sub-register");
342
343    MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
344  }
345  // Add implicit super-register defs and kills to the last MovMI.
346  MovMI->addRegisterDefined(DestReg, TRI);
347  if (KillSrc)
348    MovMI->addRegisterKilled(SrcReg, TRI);
349}
350
351void SparcInstrInfo::
352storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
353                    unsigned SrcReg, bool isKill, int FI,
354                    const TargetRegisterClass *RC,
355                    const TargetRegisterInfo *TRI) const {
356  DebugLoc DL;
357  if (I != MBB.end()) DL = I->getDebugLoc();
358
359  MachineFunction *MF = MBB.getParent();
360  const MachineFrameInfo &MFI = *MF->getFrameInfo();
361  MachineMemOperand *MMO =
362    MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
363                             MachineMemOperand::MOStore,
364                             MFI.getObjectSize(FI),
365                             MFI.getObjectAlignment(FI));
366
367  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
368 if (RC == &SP::I64RegsRegClass)
369    BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
370      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
371  else if (RC == &SP::IntRegsRegClass)
372    BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
373      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
374  else if (RC == &SP::FPRegsRegClass)
375    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
376      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
377  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
378    BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
379      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
380  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
381    // Use STQFri irrespective of its legality. If STQ is not legal, it will be
382    // lowered into two STDs in eliminateFrameIndex.
383    BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
384      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
385  else
386    llvm_unreachable("Can't store this register to stack slot");
387}
388
389void SparcInstrInfo::
390loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
391                     unsigned DestReg, int FI,
392                     const TargetRegisterClass *RC,
393                     const TargetRegisterInfo *TRI) const {
394  DebugLoc DL;
395  if (I != MBB.end()) DL = I->getDebugLoc();
396
397  MachineFunction *MF = MBB.getParent();
398  const MachineFrameInfo &MFI = *MF->getFrameInfo();
399  MachineMemOperand *MMO =
400    MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
401                             MachineMemOperand::MOLoad,
402                             MFI.getObjectSize(FI),
403                             MFI.getObjectAlignment(FI));
404
405  if (RC == &SP::I64RegsRegClass)
406    BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
407      .addMemOperand(MMO);
408  else if (RC == &SP::IntRegsRegClass)
409    BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
410      .addMemOperand(MMO);
411  else if (RC == &SP::FPRegsRegClass)
412    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
413      .addMemOperand(MMO);
414  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
415    BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
416      .addMemOperand(MMO);
417  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
418    // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
419    // lowered into two LDDs in eliminateFrameIndex.
420    BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
421      .addMemOperand(MMO);
422  else
423    llvm_unreachable("Can't load this register from stack slot");
424}
425
426unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
427{
428  SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
429  unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
430  if (GlobalBaseReg != 0)
431    return GlobalBaseReg;
432
433  // Insert the set of GlobalBaseReg into the first MBB of the function
434  MachineBasicBlock &FirstMBB = MF->front();
435  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
436  MachineRegisterInfo &RegInfo = MF->getRegInfo();
437
438  const TargetRegisterClass *PtrRC =
439    Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
440  GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
441
442  DebugLoc dl;
443
444  BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
445  SparcFI->setGlobalBaseReg(GlobalBaseReg);
446  return GlobalBaseReg;
447}
448