SparcInstrInfo.h revision e87146ace88464be4ea4f8869830642c40178f1f
1d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
2d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//
3d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//                     The LLVM Compiler Infrastructure
4d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//
5d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)// This file was developed by the LLVM research group and is distributed under
6d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)// the University of Illinois Open Source License. See LICENSE.TXT for details.
7d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//
8d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//===----------------------------------------------------------------------===//
9d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//
10d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)// This file contains the Sparc implementation of the TargetInstrInfo class.
11d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//
12d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)//===----------------------------------------------------------------------===//
13d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
14c1847b1379d12d0e05df27436bf19a9b1bf12deaTorne (Richard Coles)#ifndef SPARCINSTRUCTIONINFO_H
15d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)#define SPARCINSTRUCTIONINFO_H
16d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
17d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h"
18d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)#include "SparcRegisterInfo.h"
19d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
20d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)namespace llvm {
21d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
22d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)/// SPII - This namespace holds all of the target specific flags that
23d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)/// instruction info tracks.
24d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)///
25d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)namespace SPII {
26d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  enum {
27d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)    Pseudo = (1<<0),
28d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)    Load = (1<<1),
29d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)    Store = (1<<2),
30d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)    DelaySlot = (1<<3)
31d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  };
32d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)}
33d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
34d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)class SparcInstrInfo : public TargetInstrInfo {
35d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  const SparcRegisterInfo RI;
36d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)public:
37d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  SparcInstrInfo(SparcSubtarget &ST);
38d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
39d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
40d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// such, whenever a client has an instance of instruction info, it should
41d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// always be able to get register info as well (through this method).
42d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  ///
43d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
44d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
45d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// Return true if the instruction is a register to register move and
46d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// leave the source and dest operands in the passed parameters.
47d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  ///
48d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  virtual bool isMoveInstr(const MachineInstr &MI,
49d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)                           unsigned &SrcReg, unsigned &DstReg) const;
50d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
51d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// isLoadFromStackSlot - If the specified machine instruction is a direct
52d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// load from a stack slot, return the virtual or physical register number of
53d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// the destination along with the FrameIndex of the loaded stack slot.  If
54d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// not, return 0.  This predicate must return 0 if the instruction has
55d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// any side effects other than loading from the stack slot.
56d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
57d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)
58d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// isStoreToStackSlot - If the specified machine instruction is a direct
59d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// store to a stack slot, return the virtual or physical register number of
60d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// the source reg along with the FrameIndex of the loaded stack slot.  If
61c1847b1379d12d0e05df27436bf19a9b1bf12deaTorne (Richard Coles)  /// not, return 0.  This predicate must return 0 if the instruction has
62d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)  /// any side effects other than storing to the stack slot.
63  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
64
65
66  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67                            MachineBasicBlock *FBB,
68                            const std::vector<MachineOperand> &Cond) const;
69};
70
71}
72
73#endif
74