SparcInstrInfo.td revision 01021a8b93989a3c9e17dea540fe66809bf25403
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// UseDeprecatedInsts - This predicate is true when the target processor is a 43// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 44// to use when appropriate. In either of these cases, the instruction selector 45// will pick deprecated instructions. 46def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 47 48//===----------------------------------------------------------------------===// 49// Instruction Pattern Stuff 50//===----------------------------------------------------------------------===// 51 52def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 53 54def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 58 MVT::i32); 59}]>; 60 61def HI22 : SDNodeXForm<imm, [{ 62 // Transformation function: shift the immediate value down into the low bits. 63 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 64}]>; 65 66def SETHIimm : PatLeaf<(imm), [{ 67 return isShiftedUInt<22, 10>(N->getZExtValue()); 68}], HI22>; 69 70// Addressing modes. 71def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 72def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 73 74// Address operands 75def MEMrr : Operand<iPTR> { 76 let PrintMethod = "printMemOperand"; 77 let MIOperandInfo = (ops ptr_rc, ptr_rc); 78} 79def MEMri : Operand<iPTR> { 80 let PrintMethod = "printMemOperand"; 81 let MIOperandInfo = (ops ptr_rc, i32imm); 82} 83 84// Branch targets have OtherVT type. 85def brtarget : Operand<OtherVT>; 86def calltarget : Operand<i32>; 87 88// Operand for printing out a condition code. 89let PrintMethod = "printCCOperand" in 90 def CCOp : Operand<i32>; 91 92def SDTSPcmpicc : 93SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 94def SDTSPcmpfcc : 95SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 96def SDTSPbrcc : 97SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 98def SDTSPselectcc : 99SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 100def SDTSPFTOI : 101SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 102def SDTSPITOF : 103SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 104 105def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 106def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 107def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 108def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 109def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 110 111def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 112def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 113 114def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 115def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 116 117def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 118def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 119def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 120 121// These are target-independent nodes, but have target-specific formats. 122def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 123def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 124 SDTCisVT<1, i32> ]>; 125 126def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 127 [SDNPHasChain, SDNPOutGlue]>; 128def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 130 131def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 132def call : SDNode<"SPISD::CALL", SDT_SPCall, 133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 134 SDNPVariadic]>; 135 136def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 137def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 138 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 139 140def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 141 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 142 143def getPCX : Operand<i32> { 144 let PrintMethod = "printGetPCX"; 145} 146 147//===----------------------------------------------------------------------===// 148// SPARC Flag Conditions 149//===----------------------------------------------------------------------===// 150 151// Note that these values must be kept in sync with the CCOp::CondCode enum 152// values. 153class ICC_VAL<int N> : PatLeaf<(i32 N)>; 154def ICC_NE : ICC_VAL< 9>; // Not Equal 155def ICC_E : ICC_VAL< 1>; // Equal 156def ICC_G : ICC_VAL<10>; // Greater 157def ICC_LE : ICC_VAL< 2>; // Less or Equal 158def ICC_GE : ICC_VAL<11>; // Greater or Equal 159def ICC_L : ICC_VAL< 3>; // Less 160def ICC_GU : ICC_VAL<12>; // Greater Unsigned 161def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 162def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 163def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 164def ICC_POS : ICC_VAL<14>; // Positive 165def ICC_NEG : ICC_VAL< 6>; // Negative 166def ICC_VC : ICC_VAL<15>; // Overflow Clear 167def ICC_VS : ICC_VAL< 7>; // Overflow Set 168 169class FCC_VAL<int N> : PatLeaf<(i32 N)>; 170def FCC_U : FCC_VAL<23>; // Unordered 171def FCC_G : FCC_VAL<22>; // Greater 172def FCC_UG : FCC_VAL<21>; // Unordered or Greater 173def FCC_L : FCC_VAL<20>; // Less 174def FCC_UL : FCC_VAL<19>; // Unordered or Less 175def FCC_LG : FCC_VAL<18>; // Less or Greater 176def FCC_NE : FCC_VAL<17>; // Not Equal 177def FCC_E : FCC_VAL<25>; // Equal 178def FCC_UE : FCC_VAL<24>; // Unordered or Equal 179def FCC_GE : FCC_VAL<25>; // Greater or Equal 180def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 181def FCC_LE : FCC_VAL<27>; // Less or Equal 182def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 183def FCC_O : FCC_VAL<29>; // Ordered 184 185//===----------------------------------------------------------------------===// 186// Instruction Class Templates 187//===----------------------------------------------------------------------===// 188 189/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 190multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 191 def rr : F3_1<2, Op3Val, 192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 193 !strconcat(OpcStr, " $b, $c, $dst"), 194 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 195 def ri : F3_2<2, Op3Val, 196 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 197 !strconcat(OpcStr, " $b, $c, $dst"), 198 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 199} 200 201/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 202/// pattern. 203multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 204 def rr : F3_1<2, Op3Val, 205 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 206 !strconcat(OpcStr, " $b, $c, $dst"), []>; 207 def ri : F3_2<2, Op3Val, 208 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 209 !strconcat(OpcStr, " $b, $c, $dst"), []>; 210} 211 212//===----------------------------------------------------------------------===// 213// Instructions 214//===----------------------------------------------------------------------===// 215 216// Pseudo instructions. 217class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 218 : InstSP<outs, ins, asmstr, pattern>; 219 220// GETPCX for PIC 221let Defs = [O7] in { 222 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 223} 224 225let Defs = [O6], Uses = [O6] in { 226def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 227 "!ADJCALLSTACKDOWN $amt", 228 [(callseq_start timm:$amt)]>; 229def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 230 "!ADJCALLSTACKUP $amt1", 231 [(callseq_end timm:$amt1, timm:$amt2)]>; 232} 233 234let hasSideEffects = 1, mayStore = 1 in { 235 let rd = 0, rs1 = 0, rs2 = 0 in 236 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 237 "flushw", 238 [(flushw)]>, Requires<[HasV9]>; 239 let rd = 0, rs1 = 1, simm13 = 3 in 240 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 241 "ta 3", 242 [(flushw)]>; 243} 244 245def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 246 "unimp $val", []>; 247 248// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 249// fpmover pass. 250let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 251 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 252 "!FpMOVD $src, $dst", []>; 253 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 254 "!FpNEGD $src, $dst", 255 [(set f64:$dst, (fneg f64:$src))]>; 256 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 257 "!FpABSD $src, $dst", 258 [(set f64:$dst, (fabs f64:$src))]>; 259} 260 261// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 262// instruction selection into a branch sequence. This has to handle all 263// permutations of selection between i32/f32/f64 on ICC and FCC. 264// Expanded after instruction selection. 265let Uses = [ICC], usesCustomInserter = 1 in { 266 def SELECT_CC_Int_ICC 267 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 268 "; SELECT_CC_Int_ICC PSEUDO!", 269 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 270 def SELECT_CC_FP_ICC 271 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 272 "; SELECT_CC_FP_ICC PSEUDO!", 273 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 274 275 def SELECT_CC_DFP_ICC 276 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 277 "; SELECT_CC_DFP_ICC PSEUDO!", 278 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 279} 280 281let usesCustomInserter = 1, Uses = [FCC] in { 282 283 def SELECT_CC_Int_FCC 284 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 285 "; SELECT_CC_Int_FCC PSEUDO!", 286 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 287 288 def SELECT_CC_FP_FCC 289 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 290 "; SELECT_CC_FP_FCC PSEUDO!", 291 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 292 def SELECT_CC_DFP_FCC 293 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 294 "; SELECT_CC_DFP_FCC PSEUDO!", 295 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 296} 297 298 299// Section A.3 - Synthetic Instructions, p. 85 300// special cases of JMPL: 301let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 302 let rd = O7.Num, rs1 = G0.Num in 303 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 304 "jmp %o7+$val", [(retflag simm13:$val)]>; 305 306 let rd = I7.Num, rs1 = G0.Num in 307 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 308 "jmp %i7+$val", []>; 309} 310 311// Section B.1 - Load Integer Instructions, p. 90 312def LDSBrr : F3_1<3, 0b001001, 313 (outs IntRegs:$dst), (ins MEMrr:$addr), 314 "ldsb [$addr], $dst", 315 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 316def LDSBri : F3_2<3, 0b001001, 317 (outs IntRegs:$dst), (ins MEMri:$addr), 318 "ldsb [$addr], $dst", 319 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 320def LDSHrr : F3_1<3, 0b001010, 321 (outs IntRegs:$dst), (ins MEMrr:$addr), 322 "ldsh [$addr], $dst", 323 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 324def LDSHri : F3_2<3, 0b001010, 325 (outs IntRegs:$dst), (ins MEMri:$addr), 326 "ldsh [$addr], $dst", 327 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 328def LDUBrr : F3_1<3, 0b000001, 329 (outs IntRegs:$dst), (ins MEMrr:$addr), 330 "ldub [$addr], $dst", 331 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 332def LDUBri : F3_2<3, 0b000001, 333 (outs IntRegs:$dst), (ins MEMri:$addr), 334 "ldub [$addr], $dst", 335 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 336def LDUHrr : F3_1<3, 0b000010, 337 (outs IntRegs:$dst), (ins MEMrr:$addr), 338 "lduh [$addr], $dst", 339 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 340def LDUHri : F3_2<3, 0b000010, 341 (outs IntRegs:$dst), (ins MEMri:$addr), 342 "lduh [$addr], $dst", 343 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 344def LDrr : F3_1<3, 0b000000, 345 (outs IntRegs:$dst), (ins MEMrr:$addr), 346 "ld [$addr], $dst", 347 [(set i32:$dst, (load ADDRrr:$addr))]>; 348def LDri : F3_2<3, 0b000000, 349 (outs IntRegs:$dst), (ins MEMri:$addr), 350 "ld [$addr], $dst", 351 [(set i32:$dst, (load ADDRri:$addr))]>; 352 353// Section B.2 - Load Floating-point Instructions, p. 92 354def LDFrr : F3_1<3, 0b100000, 355 (outs FPRegs:$dst), (ins MEMrr:$addr), 356 "ld [$addr], $dst", 357 [(set f32:$dst, (load ADDRrr:$addr))]>; 358def LDFri : F3_2<3, 0b100000, 359 (outs FPRegs:$dst), (ins MEMri:$addr), 360 "ld [$addr], $dst", 361 [(set f32:$dst, (load ADDRri:$addr))]>; 362def LDDFrr : F3_1<3, 0b100011, 363 (outs DFPRegs:$dst), (ins MEMrr:$addr), 364 "ldd [$addr], $dst", 365 [(set f64:$dst, (load ADDRrr:$addr))]>; 366def LDDFri : F3_2<3, 0b100011, 367 (outs DFPRegs:$dst), (ins MEMri:$addr), 368 "ldd [$addr], $dst", 369 [(set f64:$dst, (load ADDRri:$addr))]>; 370 371// Section B.4 - Store Integer Instructions, p. 95 372def STBrr : F3_1<3, 0b000101, 373 (outs), (ins MEMrr:$addr, IntRegs:$src), 374 "stb $src, [$addr]", 375 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 376def STBri : F3_2<3, 0b000101, 377 (outs), (ins MEMri:$addr, IntRegs:$src), 378 "stb $src, [$addr]", 379 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 380def STHrr : F3_1<3, 0b000110, 381 (outs), (ins MEMrr:$addr, IntRegs:$src), 382 "sth $src, [$addr]", 383 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 384def STHri : F3_2<3, 0b000110, 385 (outs), (ins MEMri:$addr, IntRegs:$src), 386 "sth $src, [$addr]", 387 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 388def STrr : F3_1<3, 0b000100, 389 (outs), (ins MEMrr:$addr, IntRegs:$src), 390 "st $src, [$addr]", 391 [(store i32:$src, ADDRrr:$addr)]>; 392def STri : F3_2<3, 0b000100, 393 (outs), (ins MEMri:$addr, IntRegs:$src), 394 "st $src, [$addr]", 395 [(store i32:$src, ADDRri:$addr)]>; 396 397// Section B.5 - Store Floating-point Instructions, p. 97 398def STFrr : F3_1<3, 0b100100, 399 (outs), (ins MEMrr:$addr, FPRegs:$src), 400 "st $src, [$addr]", 401 [(store f32:$src, ADDRrr:$addr)]>; 402def STFri : F3_2<3, 0b100100, 403 (outs), (ins MEMri:$addr, FPRegs:$src), 404 "st $src, [$addr]", 405 [(store f32:$src, ADDRri:$addr)]>; 406def STDFrr : F3_1<3, 0b100111, 407 (outs), (ins MEMrr:$addr, DFPRegs:$src), 408 "std $src, [$addr]", 409 [(store f64:$src, ADDRrr:$addr)]>; 410def STDFri : F3_2<3, 0b100111, 411 (outs), (ins MEMri:$addr, DFPRegs:$src), 412 "std $src, [$addr]", 413 [(store f64:$src, ADDRri:$addr)]>; 414 415// Section B.9 - SETHI Instruction, p. 104 416def SETHIi: F2_1<0b100, 417 (outs IntRegs:$dst), (ins i32imm:$src), 418 "sethi $src, $dst", 419 [(set i32:$dst, SETHIimm:$src)]>; 420 421// Section B.10 - NOP Instruction, p. 105 422// (It's a special case of SETHI) 423let rd = 0, imm22 = 0 in 424 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 425 426// Section B.11 - Logical Instructions, p. 106 427defm AND : F3_12<"and", 0b000001, and>; 428 429def ANDNrr : F3_1<2, 0b000101, 430 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 431 "andn $b, $c, $dst", 432 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 433def ANDNri : F3_2<2, 0b000101, 434 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 435 "andn $b, $c, $dst", []>; 436 437defm OR : F3_12<"or", 0b000010, or>; 438 439def ORNrr : F3_1<2, 0b000110, 440 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 441 "orn $b, $c, $dst", 442 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 443def ORNri : F3_2<2, 0b000110, 444 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 445 "orn $b, $c, $dst", []>; 446defm XOR : F3_12<"xor", 0b000011, xor>; 447 448def XNORrr : F3_1<2, 0b000111, 449 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 450 "xnor $b, $c, $dst", 451 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 452def XNORri : F3_2<2, 0b000111, 453 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 454 "xnor $b, $c, $dst", []>; 455 456// Section B.12 - Shift Instructions, p. 107 457defm SLL : F3_12<"sll", 0b100101, shl>; 458defm SRL : F3_12<"srl", 0b100110, srl>; 459defm SRA : F3_12<"sra", 0b100111, sra>; 460 461// Section B.13 - Add Instructions, p. 108 462defm ADD : F3_12<"add", 0b000000, add>; 463 464// "LEA" forms of add (patterns to make tblgen happy) 465def LEA_ADDri : F3_2<2, 0b000000, 466 (outs IntRegs:$dst), (ins MEMri:$addr), 467 "add ${addr:arith}, $dst", 468 [(set iPTR:$dst, ADDRri:$addr)]>; 469 470let Defs = [ICC] in 471 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 472 473let Uses = [ICC] in 474 defm ADDX : F3_12<"addx", 0b001000, adde>; 475 476// Section B.15 - Subtract Instructions, p. 110 477defm SUB : F3_12 <"sub" , 0b000100, sub>; 478let Uses = [ICC] in 479 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 480 481let Defs = [ICC] in { 482 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 483 484 def CMPrr : F3_1<2, 0b010100, 485 (outs), (ins IntRegs:$b, IntRegs:$c), 486 "cmp $b, $c", 487 [(SPcmpicc i32:$b, i32:$c)]>; 488 def CMPri : F3_1<2, 0b010100, 489 (outs), (ins IntRegs:$b, i32imm:$c), 490 "cmp $b, $c", 491 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 492} 493 494let Uses = [ICC], Defs = [ICC] in 495 def SUBXCCrr: F3_1<2, 0b011100, 496 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 497 "subxcc $b, $c, $dst", []>; 498 499 500// Section B.18 - Multiply Instructions, p. 113 501let Defs = [Y] in { 502 defm UMUL : F3_12np<"umul", 0b001010>; 503 defm SMUL : F3_12 <"smul", 0b001011, mul>; 504} 505 506// Section B.19 - Divide Instructions, p. 115 507let Defs = [Y] in { 508 defm UDIV : F3_12np<"udiv", 0b001110>; 509 defm SDIV : F3_12np<"sdiv", 0b001111>; 510} 511 512// Section B.20 - SAVE and RESTORE, p. 117 513defm SAVE : F3_12np<"save" , 0b111100>; 514defm RESTORE : F3_12np<"restore", 0b111101>; 515 516// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 517 518// conditional branch class: 519class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 520 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 521 let isBranch = 1; 522 let isTerminator = 1; 523 let hasDelaySlot = 1; 524} 525 526let isBarrier = 1 in 527 def BA : BranchSP<0b1000, (ins brtarget:$dst), 528 "ba $dst", 529 [(br bb:$dst)]>; 530 531// Indirect branch instructions. 532let isTerminator = 1, isBarrier = 1, 533 hasDelaySlot = 1, isBranch =1, 534 isIndirectBranch = 1 in { 535 def BINDrr : F3_1<2, 0b111000, 536 (outs), (ins MEMrr:$ptr), 537 "jmp $ptr", 538 [(brind ADDRrr:$ptr)]>; 539 def BINDri : F3_2<2, 0b111000, 540 (outs), (ins MEMri:$ptr), 541 "jmp $ptr", 542 [(brind ADDRri:$ptr)]>; 543} 544 545// FIXME: the encoding for the JIT should look at the condition field. 546let Uses = [ICC] in 547 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 548 "b$cc $dst", 549 [(SPbricc bb:$dst, imm:$cc)]>; 550 551 552// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 553 554// floating-point conditional branch class: 555class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 556 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 557 let isBranch = 1; 558 let isTerminator = 1; 559 let hasDelaySlot = 1; 560} 561 562// FIXME: the encoding for the JIT should look at the condition field. 563let Uses = [FCC] in 564 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 565 "fb$cc $dst", 566 [(SPbrfcc bb:$dst, imm:$cc)]>; 567 568 569// Section B.24 - Call and Link Instruction, p. 125 570// This is the only Format 1 instruction 571let Uses = [O6], 572 hasDelaySlot = 1, isCall = 1, 573 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 574 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 575 ICC, FCC, Y] in { 576 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 577 "call $dst", []> { 578 bits<30> disp; 579 let op = 1; 580 let Inst{29-0} = disp; 581 } 582 583 // indirect calls 584 def JMPLrr : F3_1<2, 0b111000, 585 (outs), (ins MEMrr:$ptr, variable_ops), 586 "call $ptr", 587 [(call ADDRrr:$ptr)]>; 588 def JMPLri : F3_2<2, 0b111000, 589 (outs), (ins MEMri:$ptr, variable_ops), 590 "call $ptr", 591 [(call ADDRri:$ptr)]>; 592} 593 594// Section B.28 - Read State Register Instructions 595let Uses = [Y] in 596 def RDY : F3_1<2, 0b101000, 597 (outs IntRegs:$dst), (ins), 598 "rd %y, $dst", []>; 599 600// Section B.29 - Write State Register Instructions 601let Defs = [Y] in { 602 def WRYrr : F3_1<2, 0b110000, 603 (outs), (ins IntRegs:$b, IntRegs:$c), 604 "wr $b, $c, %y", []>; 605 def WRYri : F3_2<2, 0b110000, 606 (outs), (ins IntRegs:$b, i32imm:$c), 607 "wr $b, $c, %y", []>; 608} 609// Convert Integer to Floating-point Instructions, p. 141 610def FITOS : F3_3<2, 0b110100, 0b011000100, 611 (outs FPRegs:$dst), (ins FPRegs:$src), 612 "fitos $src, $dst", 613 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 614def FITOD : F3_3<2, 0b110100, 0b011001000, 615 (outs DFPRegs:$dst), (ins FPRegs:$src), 616 "fitod $src, $dst", 617 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 618 619// Convert Floating-point to Integer Instructions, p. 142 620def FSTOI : F3_3<2, 0b110100, 0b011010001, 621 (outs FPRegs:$dst), (ins FPRegs:$src), 622 "fstoi $src, $dst", 623 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 624def FDTOI : F3_3<2, 0b110100, 0b011010010, 625 (outs FPRegs:$dst), (ins DFPRegs:$src), 626 "fdtoi $src, $dst", 627 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 628 629// Convert between Floating-point Formats Instructions, p. 143 630def FSTOD : F3_3<2, 0b110100, 0b011001001, 631 (outs DFPRegs:$dst), (ins FPRegs:$src), 632 "fstod $src, $dst", 633 [(set f64:$dst, (fextend f32:$src))]>; 634def FDTOS : F3_3<2, 0b110100, 0b011000110, 635 (outs FPRegs:$dst), (ins DFPRegs:$src), 636 "fdtos $src, $dst", 637 [(set f32:$dst, (fround f64:$src))]>; 638 639// Floating-point Move Instructions, p. 144 640def FMOVS : F3_3<2, 0b110100, 0b000000001, 641 (outs FPRegs:$dst), (ins FPRegs:$src), 642 "fmovs $src, $dst", []>; 643def FNEGS : F3_3<2, 0b110100, 0b000000101, 644 (outs FPRegs:$dst), (ins FPRegs:$src), 645 "fnegs $src, $dst", 646 [(set f32:$dst, (fneg f32:$src))]>; 647def FABSS : F3_3<2, 0b110100, 0b000001001, 648 (outs FPRegs:$dst), (ins FPRegs:$src), 649 "fabss $src, $dst", 650 [(set f32:$dst, (fabs f32:$src))]>; 651 652 653// Floating-point Square Root Instructions, p.145 654def FSQRTS : F3_3<2, 0b110100, 0b000101001, 655 (outs FPRegs:$dst), (ins FPRegs:$src), 656 "fsqrts $src, $dst", 657 [(set f32:$dst, (fsqrt f32:$src))]>; 658def FSQRTD : F3_3<2, 0b110100, 0b000101010, 659 (outs DFPRegs:$dst), (ins DFPRegs:$src), 660 "fsqrtd $src, $dst", 661 [(set f64:$dst, (fsqrt f64:$src))]>; 662 663 664 665// Floating-point Add and Subtract Instructions, p. 146 666def FADDS : F3_3<2, 0b110100, 0b001000001, 667 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 668 "fadds $src1, $src2, $dst", 669 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 670def FADDD : F3_3<2, 0b110100, 0b001000010, 671 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 672 "faddd $src1, $src2, $dst", 673 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 674def FSUBS : F3_3<2, 0b110100, 0b001000101, 675 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 676 "fsubs $src1, $src2, $dst", 677 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 678def FSUBD : F3_3<2, 0b110100, 0b001000110, 679 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 680 "fsubd $src1, $src2, $dst", 681 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 682 683// Floating-point Multiply and Divide Instructions, p. 147 684def FMULS : F3_3<2, 0b110100, 0b001001001, 685 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 686 "fmuls $src1, $src2, $dst", 687 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 688def FMULD : F3_3<2, 0b110100, 0b001001010, 689 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 690 "fmuld $src1, $src2, $dst", 691 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 692def FSMULD : F3_3<2, 0b110100, 0b001101001, 693 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 694 "fsmuld $src1, $src2, $dst", 695 [(set f64:$dst, (fmul (fextend f32:$src1), 696 (fextend f32:$src2)))]>; 697def FDIVS : F3_3<2, 0b110100, 0b001001101, 698 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 699 "fdivs $src1, $src2, $dst", 700 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 701def FDIVD : F3_3<2, 0b110100, 0b001001110, 702 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 703 "fdivd $src1, $src2, $dst", 704 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 705 706// Floating-point Compare Instructions, p. 148 707// Note: the 2nd template arg is different for these guys. 708// Note 2: the result of a FCMP is not available until the 2nd cycle 709// after the instr is retired, but there is no interlock. This behavior 710// is modelled with a forced noop after the instruction. 711let Defs = [FCC] in { 712 def FCMPS : F3_3<2, 0b110101, 0b001010001, 713 (outs), (ins FPRegs:$src1, FPRegs:$src2), 714 "fcmps $src1, $src2\n\tnop", 715 [(SPcmpfcc f32:$src1, f32:$src2)]>; 716 def FCMPD : F3_3<2, 0b110101, 0b001010010, 717 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 718 "fcmpd $src1, $src2\n\tnop", 719 [(SPcmpfcc f64:$src1, f64:$src2)]>; 720} 721 722//===----------------------------------------------------------------------===// 723// V9 Instructions 724//===----------------------------------------------------------------------===// 725 726// V9 Conditional Moves. 727let Predicates = [HasV9], Constraints = "$f = $rd" in { 728 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 729 // FIXME: Add instruction encodings for the JIT some day. 730 let Uses = [ICC] in { 731 def MOVICCrr 732 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 733 "mov$cc %icc, $rs2, $rd", 734 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>; 735 def MOVICCri 736 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 737 "mov$cc %icc, $i, $rd", 738 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>; 739 } 740 741 let Uses = [FCC] in { 742 def MOVFCCrr 743 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 744 "mov$cc %fcc0, $rs2, $rd", 745 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>; 746 def MOVFCCri 747 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 748 "mov$cc %fcc0, $i, $rd", 749 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>; 750 } 751 752 let Uses = [ICC] in { 753 def FMOVS_ICC 754 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 755 "fmovs$cc %icc, $rs2, $rd", 756 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>; 757 def FMOVD_ICC 758 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 759 "fmovd$cc %icc, $rs2, $rd", 760 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>; 761 } 762 763 let Uses = [FCC] in { 764 def FMOVS_FCC 765 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 766 "fmovs$cc %fcc0, $rs2, $rd", 767 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>; 768 def FMOVD_FCC 769 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 770 "fmovd$cc %fcc0, $rs2, $rd", 771 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>; 772 } 773 774} 775 776// Floating-Point Move Instructions, p. 164 of the V9 manual. 777let Predicates = [HasV9] in { 778 def FMOVD : F3_3<2, 0b110100, 0b000000010, 779 (outs DFPRegs:$dst), (ins DFPRegs:$src), 780 "fmovd $src, $dst", []>; 781 def FNEGD : F3_3<2, 0b110100, 0b000000110, 782 (outs DFPRegs:$dst), (ins DFPRegs:$src), 783 "fnegd $src, $dst", 784 [(set f64:$dst, (fneg f64:$src))]>; 785 def FABSD : F3_3<2, 0b110100, 0b000001010, 786 (outs DFPRegs:$dst), (ins DFPRegs:$src), 787 "fabsd $src, $dst", 788 [(set f64:$dst, (fabs f64:$src))]>; 789} 790 791// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 792// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 793def POPCrr : F3_1<2, 0b101110, 794 (outs IntRegs:$dst), (ins IntRegs:$src), 795 "popc $src, $dst", []>, Requires<[HasV9]>; 796def : Pat<(ctpop i32:$src), 797 (POPCrr (SLLri $src, 0))>; 798 799//===----------------------------------------------------------------------===// 800// Non-Instruction Patterns 801//===----------------------------------------------------------------------===// 802 803// Small immediates. 804def : Pat<(i32 simm13:$val), 805 (ORri (i32 G0), imm:$val)>; 806// Arbitrary immediates. 807def : Pat<(i32 imm:$val), 808 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 809 810 811// Global addresses, constant pool entries 812def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 813def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 814def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 815def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 816 817// Blockaddress 818def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 819def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 820 821// Add reg, lo. This is used when taking the addr of a global/constpool entry. 822def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 823def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 824def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 825 (ADDri $r, tblockaddress:$in)>; 826 827// Calls: 828def : Pat<(call tglobaladdr:$dst), 829 (CALL tglobaladdr:$dst)>; 830def : Pat<(call texternalsym:$dst), 831 (CALL texternalsym:$dst)>; 832 833// Map integer extload's to zextloads. 834def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 835def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 836def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 837def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 838def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 839def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 840 841// zextload bool -> zextload byte 842def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 843def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 844 845// store 0, addr -> store %g0, addr 846def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 847def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 848 849include "SparcInstr64Bit.td" 850