SparcInstrInfo.td revision 0b9bbd2244e5f518361cb0f73279b5ccb8e6ee25
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 let ClassPrefix = "SparcV8"; 23 24 bits<2> op; 25 let Inst{31-30} = op; // Top two bits are the 'op' field 26 27 // Bit attributes specific to SparcV8 instructions 28 bit isPasi = 0; // Does this instruction affect an alternate addr space? 29 bit isPrivileged = 0; // Is this a privileged instruction? 30} 31 32include "SparcV8InstrInfo_F2.td" 33include "SparcV8InstrInfo_F3.td" 34 35//===----------------------------------------------------------------------===// 36// Instructions 37//===----------------------------------------------------------------------===// 38 39// Pseudo instructions. 40class PseudoInstV8<string nm> : InstV8 { 41 let Name = nm; 42} 43def PHI : PseudoInstV8<"PHI">; 44def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">; 45def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">; 46def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">; 47def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">; 48 49// Section A.3 - Synthetic Instructions, p. 85 50// special cases of JMPL: 51let isReturn = 1, isTerminator = 1, simm13 = 8 in 52 def RET : F3_2<2, 0b111000, "ret">; 53let isReturn = 1, isTerminator = 1, simm13 = 8 in 54 def RETL: F3_2<2, 0b111000, "retl">; 55// CMP is a special case of SUBCC where destination is ignored, by setting it to 56// %g0 (hardwired zero). 57// FIXME: should keep track of the fact that it defs the integer condition codes 58let rd = 0 in 59 def CMPri: F3_2<2, 0b010100, "cmp">; 60 61// Section B.1 - Load Integer Instructions, p. 90 62def LDSB: F3_2<3, 0b001001, "ldsb">; 63def LDSH: F3_2<3, 0b001010, "ldsh">; 64def LDUB: F3_2<3, 0b000001, "ldub">; 65def LDUH: F3_2<3, 0b000010, "lduh">; 66def LD : F3_2<3, 0b000000, "ld">; 67def LDD : F3_2<3, 0b000011, "ldd">; 68 69// Section B.2 - Load Floating-point Instructions, p. 92 70def LDFrr : F3_1<3, 0b100000, "ld">; 71def LDFri : F3_2<3, 0b100000, "ld">; 72def LDDFrr : F3_1<3, 0b100011, "ldd">; 73def LDDFri : F3_2<3, 0b100011, "ldd">; 74def LDFSRrr: F3_1<3, 0b100001, "ld">; 75def LDFSRri: F3_2<3, 0b100001, "ld">; 76 77// Section B.4 - Store Integer Instructions, p. 95 78def STB : F3_2<3, 0b000101, "stb">; 79def STH : F3_2<3, 0b000110, "sth">; 80def ST : F3_2<3, 0b000100, "st">; 81def STD : F3_2<3, 0b000111, "std">; 82 83// Section B.5 - Store Floating-point Instructions, p. 97 84def STFrr : F3_1<3, 0b100100, "st">; 85def STFri : F3_2<3, 0b100100, "st">; 86def STDFrr : F3_1<3, 0b100111, "std">; 87def STDFri : F3_2<3, 0b100111, "std">; 88def STFSRrr : F3_1<3, 0b100101, "st">; 89def STFSRri : F3_2<3, 0b100101, "st">; 90def STDFQrr : F3_1<3, 0b100110, "std">; 91def STDFQri : F3_2<3, 0b100110, "std">; 92 93// Section B.9 - SETHI Instruction, p. 104 94def SETHIi: F2_1<0b100, "sethi">; 95 96// Section B.10 - NOP Instruction, p. 105 97// (It's a special case of SETHI) 98let rd = 0, imm = 0 in 99 def NOP : F2_1<0b100, "nop">; 100 101// Section B.11 - Logical Instructions, p. 106 102def ANDrr : F3_1<2, 0b000001, "and">; 103def ANDri : F3_2<2, 0b000001, "and">; 104def ORrr : F3_1<2, 0b000010, "or">; 105def ORri : F3_2<2, 0b000010, "or">; 106def XORrr : F3_1<2, 0b000011, "xor">; 107def XORri : F3_2<2, 0b000011, "xor">; 108 109// Section B.12 - Shift Instructions, p. 107 110def SLLrr : F3_1<2, 0b100101, "sll">; 111def SLLri : F3_2<2, 0b100101, "sll">; 112def SRLrr : F3_1<2, 0b100110, "srl">; 113def SRLri : F3_2<2, 0b100110, "srl">; 114def SRArr : F3_1<2, 0b100111, "sra">; 115def SRAri : F3_2<2, 0b100111, "sra">; 116 117// Section B.13 - Add Instructions, p. 108 118def ADDrr : F3_1<2, 0b000000, "add">; 119def ADDri : F3_2<2, 0b000000, "add">; 120 121// Section B.15 - Subtract Instructions, p. 110 122def SUBrr : F3_1<2, 0b000100, "sub">; 123def SUBCCrr : F3_1<2, 0b010100, "subcc">; 124def SUBCCri : F3_2<2, 0b010100, "subcc">; 125 126// Section B.18 - Multiply Instructions, p. 113 127def UMULrr : F3_1<2, 0b001010, "umul">; 128def SMULrr : F3_1<2, 0b001011, "smul">; 129 130// Section B.19 - Divide Instructions, p. 115 131def UDIVrr : F3_1<2, 0b001110, "udiv">; 132def UDIVri : F3_2<2, 0b001110, "udiv">; 133def SDIVrr : F3_1<2, 0b001111, "sdiv">; 134def SDIVri : F3_2<2, 0b001111, "sdiv">; 135def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 136def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 137def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 138def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 139 140// Section B.20 - SAVE and RESTORE, p. 117 141def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 142def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 143def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 144def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 145 146// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 147 148// conditional branch class: 149class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 150 let isBranch = 1; 151 let isTerminator = 1; 152} 153 154let isBarrier = 1 in 155 def BA : BranchV8<0b1000, "ba">; 156def BN : BranchV8<0b0000, "bn">; 157def BNE : BranchV8<0b1001, "bne">; 158def BE : BranchV8<0b0001, "be">; 159def BG : BranchV8<0b1010, "bg">; 160def BLE : BranchV8<0b0010, "ble">; 161def BGE : BranchV8<0b1011, "bge">; 162def BL : BranchV8<0b0011, "bl">; 163def BGU : BranchV8<0b1100, "bgu">; 164def BLEU : BranchV8<0b0100, "bleu">; 165def BCC : BranchV8<0b1101, "bcc">; 166def BCS : BranchV8<0b0101, "bcs">; 167 168// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 169 170// floating-point conditional branch class: 171class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 172 let isBranch = 1; 173 let isTerminator = 1; 174} 175 176def FBA : FPBranchV8<0b1000, "fba">; 177def FBN : FPBranchV8<0b0000, "fbn">; 178def FBU : FPBranchV8<0b0111, "fbu">; 179def FBG : FPBranchV8<0b0110, "fbg">; 180def FBUG : FPBranchV8<0b0101, "fbug">; 181def FBL : FPBranchV8<0b0100, "fbl">; 182def FBUL : FPBranchV8<0b0011, "fbul">; 183def FBLG : FPBranchV8<0b0010, "fblg">; 184def FBNE : FPBranchV8<0b0001, "fbne">; 185def FBE : FPBranchV8<0b1001, "fbe">; 186def FBUE : FPBranchV8<0b1010, "fbue">; 187def FBGE : FPBranchV8<0b1011, "fbge">; 188def FBUGE: FPBranchV8<0b1100, "fbuge">; 189def FBLE : FPBranchV8<0b1101, "fble">; 190def FBULE: FPBranchV8<0b1110, "fbule">; 191def FBO : FPBranchV8<0b1111, "fbo">; 192 193// Section B.24 - Call and Link Instruction, p. 125 194// This is the only Format 1 instruction 195def CALL : InstV8 { 196 bits<30> disp; 197 let op = 1; 198 let Inst{29-0} = disp; 199 let Name = "call"; 200 let isCall = 1; 201} 202 203// Section B.25 - Jump and Link, p. 126 204let isCall = 1 in 205 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 206 207// Section B.29 - Write State Register Instructions 208def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 209def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 210 211// Convert Integer to Floating-point Instructions, p. 141 212def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 213def FITOD : F3_3<2, 0b110100, 0b011001000, "fitos">; 214 215// Convert between Floating-point Formats Instructions, p. 143 216def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 217def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 218 219// Floating-point Move Instructions, p. 144 220def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 221def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 222def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 223 224// Floating-point Add and Subtract Instructions, p. 146 225def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 226def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 227def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 228def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 229 230// Floating-point Multiply and Divide Instructions, p. 147 231def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 232def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 233def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 234def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 235def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 236 237// Floating-point Compare Instructions, p. 148 238// Note: the 2nd template arg is different for these guys 239def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 240def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 241def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 242def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 243 244