SparcInstrInfo.td revision 1662239a5eb745de7b683b034ea199cb984328f2
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let NumMIOperands = 2; 77 let MIOperandInfo = (ops IntRegs, IntRegs); 78} 79def MEMri : Operand<i32> { 80 let PrintMethod = "printMemOperand"; 81 let NumMIOperands = 2; 82 let MIOperandInfo = (ops IntRegs, i32imm); 83} 84 85// Branch targets have OtherVT type. 86def brtarget : Operand<OtherVT>; 87def calltarget : Operand<i32>; 88 89// Operand for printing out a condition code. 90let PrintMethod = "printCCOperand" in 91 def CCOp : Operand<i32>; 92 93def SDTSPcmpfcc : 94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 95def SDTSPbrcc : 96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 97def SDTSPselectcc : 98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 99def SDTSPFTOI : 100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 101def SDTSPITOF : 102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 103 104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 108 109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 111 112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 114 115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 117 118// These are target-independent nodes, but have target-specific formats. 119def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 120def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, 121 [SDNPHasChain, SDNPOutFlag]>; 122def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, 123 [SDNPHasChain, SDNPOutFlag]>; 124 125def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 126def call : SDNode<"SPISD::CALL", SDT_SPCall, 127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 128 129def SDT_SPRetFlag : SDTypeProfile<0, 0, []>; 130def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag, 131 [SDNPHasChain, SDNPOptInFlag]>; 132 133//===----------------------------------------------------------------------===// 134// SPARC Flag Conditions 135//===----------------------------------------------------------------------===// 136 137// Note that these values must be kept in sync with the CCOp::CondCode enum 138// values. 139class ICC_VAL<int N> : PatLeaf<(i32 N)>; 140def ICC_NE : ICC_VAL< 9>; // Not Equal 141def ICC_E : ICC_VAL< 1>; // Equal 142def ICC_G : ICC_VAL<10>; // Greater 143def ICC_LE : ICC_VAL< 2>; // Less or Equal 144def ICC_GE : ICC_VAL<11>; // Greater or Equal 145def ICC_L : ICC_VAL< 3>; // Less 146def ICC_GU : ICC_VAL<12>; // Greater Unsigned 147def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 148def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 149def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 150def ICC_POS : ICC_VAL<14>; // Positive 151def ICC_NEG : ICC_VAL< 6>; // Negative 152def ICC_VC : ICC_VAL<15>; // Overflow Clear 153def ICC_VS : ICC_VAL< 7>; // Overflow Set 154 155class FCC_VAL<int N> : PatLeaf<(i32 N)>; 156def FCC_U : FCC_VAL<23>; // Unordered 157def FCC_G : FCC_VAL<22>; // Greater 158def FCC_UG : FCC_VAL<21>; // Unordered or Greater 159def FCC_L : FCC_VAL<20>; // Less 160def FCC_UL : FCC_VAL<19>; // Unordered or Less 161def FCC_LG : FCC_VAL<18>; // Less or Greater 162def FCC_NE : FCC_VAL<17>; // Not Equal 163def FCC_E : FCC_VAL<25>; // Equal 164def FCC_UE : FCC_VAL<24>; // Unordered or Equal 165def FCC_GE : FCC_VAL<25>; // Greater or Equal 166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 167def FCC_LE : FCC_VAL<27>; // Less or Equal 168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 169def FCC_O : FCC_VAL<29>; // Ordered 170 171 172//===----------------------------------------------------------------------===// 173// Instructions 174//===----------------------------------------------------------------------===// 175 176// Pseudo instructions. 177class Pseudo<dag ops, string asmstr, list<dag> pattern> 178 : InstSP<ops, asmstr, pattern>; 179 180def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 181 "!ADJCALLSTACKDOWN $amt", 182 [(callseq_start imm:$amt)]>; 183def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 184 "!ADJCALLSTACKUP $amt", 185 [(callseq_end imm:$amt)]>; 186def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 187 "!IMPLICIT_DEF $dst", 188 [(set IntRegs:$dst, (undef))]>; 189def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 190 [(set FPRegs:$dst, (undef))]>; 191def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 192 [(set DFPRegs:$dst, (undef))]>; 193 194// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 195// fpmover pass. 196let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 197 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 198 "!FpMOVD $src, $dst", []>; 199 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 200 "!FpNEGD $src, $dst", 201 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 202 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 203 "!FpABSD $src, $dst", 204 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 205} 206 207// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 208// scheduler into a branch sequence. This has to handle all permutations of 209// selection between i32/f32/f64 on ICC and FCC. 210let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 211 def SELECT_CC_Int_ICC 212 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 213 "; SELECT_CC_Int_ICC PSEUDO!", 214 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 215 imm:$Cond))]>; 216 def SELECT_CC_Int_FCC 217 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 218 "; SELECT_CC_Int_FCC PSEUDO!", 219 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 220 imm:$Cond))]>; 221 def SELECT_CC_FP_ICC 222 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 223 "; SELECT_CC_FP_ICC PSEUDO!", 224 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 225 imm:$Cond))]>; 226 def SELECT_CC_FP_FCC 227 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 228 "; SELECT_CC_FP_FCC PSEUDO!", 229 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 230 imm:$Cond))]>; 231 def SELECT_CC_DFP_ICC 232 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 233 "; SELECT_CC_DFP_ICC PSEUDO!", 234 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 235 imm:$Cond))]>; 236 def SELECT_CC_DFP_FCC 237 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 238 "; SELECT_CC_DFP_FCC PSEUDO!", 239 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 240 imm:$Cond))]>; 241} 242 243 244// Section A.3 - Synthetic Instructions, p. 85 245// special cases of JMPL: 246let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 247 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 248 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 249} 250 251// Section B.1 - Load Integer Instructions, p. 90 252def LDSBrr : F3_1<3, 0b001001, 253 (ops IntRegs:$dst, MEMrr:$addr), 254 "ldsb [$addr], $dst", 255 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 256def LDSBri : F3_2<3, 0b001001, 257 (ops IntRegs:$dst, MEMri:$addr), 258 "ldsb [$addr], $dst", 259 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 260def LDSHrr : F3_1<3, 0b001010, 261 (ops IntRegs:$dst, MEMrr:$addr), 262 "ldsh [$addr], $dst", 263 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 264def LDSHri : F3_2<3, 0b001010, 265 (ops IntRegs:$dst, MEMri:$addr), 266 "ldsh [$addr], $dst", 267 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 268def LDUBrr : F3_1<3, 0b000001, 269 (ops IntRegs:$dst, MEMrr:$addr), 270 "ldub [$addr], $dst", 271 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 272def LDUBri : F3_2<3, 0b000001, 273 (ops IntRegs:$dst, MEMri:$addr), 274 "ldub [$addr], $dst", 275 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 276def LDUHrr : F3_1<3, 0b000010, 277 (ops IntRegs:$dst, MEMrr:$addr), 278 "lduh [$addr], $dst", 279 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 280def LDUHri : F3_2<3, 0b000010, 281 (ops IntRegs:$dst, MEMri:$addr), 282 "lduh [$addr], $dst", 283 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 284def LDrr : F3_1<3, 0b000000, 285 (ops IntRegs:$dst, MEMrr:$addr), 286 "ld [$addr], $dst", 287 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 288def LDri : F3_2<3, 0b000000, 289 (ops IntRegs:$dst, MEMri:$addr), 290 "ld [$addr], $dst", 291 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 292 293// Section B.2 - Load Floating-point Instructions, p. 92 294def LDFrr : F3_1<3, 0b100000, 295 (ops FPRegs:$dst, MEMrr:$addr), 296 "ld [$addr], $dst", 297 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 298def LDFri : F3_2<3, 0b100000, 299 (ops FPRegs:$dst, MEMri:$addr), 300 "ld [$addr], $dst", 301 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 302def LDDFrr : F3_1<3, 0b100011, 303 (ops DFPRegs:$dst, MEMrr:$addr), 304 "ldd [$addr], $dst", 305 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 306def LDDFri : F3_2<3, 0b100011, 307 (ops DFPRegs:$dst, MEMri:$addr), 308 "ldd [$addr], $dst", 309 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 310 311// Section B.4 - Store Integer Instructions, p. 95 312def STBrr : F3_1<3, 0b000101, 313 (ops MEMrr:$addr, IntRegs:$src), 314 "stb $src, [$addr]", 315 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 316def STBri : F3_2<3, 0b000101, 317 (ops MEMri:$addr, IntRegs:$src), 318 "stb $src, [$addr]", 319 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 320def STHrr : F3_1<3, 0b000110, 321 (ops MEMrr:$addr, IntRegs:$src), 322 "sth $src, [$addr]", 323 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 324def STHri : F3_2<3, 0b000110, 325 (ops MEMri:$addr, IntRegs:$src), 326 "sth $src, [$addr]", 327 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 328def STrr : F3_1<3, 0b000100, 329 (ops MEMrr:$addr, IntRegs:$src), 330 "st $src, [$addr]", 331 [(store IntRegs:$src, ADDRrr:$addr)]>; 332def STri : F3_2<3, 0b000100, 333 (ops MEMri:$addr, IntRegs:$src), 334 "st $src, [$addr]", 335 [(store IntRegs:$src, ADDRri:$addr)]>; 336 337// Section B.5 - Store Floating-point Instructions, p. 97 338def STFrr : F3_1<3, 0b100100, 339 (ops MEMrr:$addr, FPRegs:$src), 340 "st $src, [$addr]", 341 [(store FPRegs:$src, ADDRrr:$addr)]>; 342def STFri : F3_2<3, 0b100100, 343 (ops MEMri:$addr, FPRegs:$src), 344 "st $src, [$addr]", 345 [(store FPRegs:$src, ADDRri:$addr)]>; 346def STDFrr : F3_1<3, 0b100111, 347 (ops MEMrr:$addr, DFPRegs:$src), 348 "std $src, [$addr]", 349 [(store DFPRegs:$src, ADDRrr:$addr)]>; 350def STDFri : F3_2<3, 0b100111, 351 (ops MEMri:$addr, DFPRegs:$src), 352 "std $src, [$addr]", 353 [(store DFPRegs:$src, ADDRri:$addr)]>; 354 355// Section B.9 - SETHI Instruction, p. 104 356def SETHIi: F2_1<0b100, 357 (ops IntRegs:$dst, i32imm:$src), 358 "sethi $src, $dst", 359 [(set IntRegs:$dst, SETHIimm:$src)]>; 360 361// Section B.10 - NOP Instruction, p. 105 362// (It's a special case of SETHI) 363let rd = 0, imm22 = 0 in 364 def NOP : F2_1<0b100, (ops), "nop", []>; 365 366// Section B.11 - Logical Instructions, p. 106 367def ANDrr : F3_1<2, 0b000001, 368 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 369 "and $b, $c, $dst", 370 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 371def ANDri : F3_2<2, 0b000001, 372 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 373 "and $b, $c, $dst", 374 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 375def ANDNrr : F3_1<2, 0b000101, 376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 377 "andn $b, $c, $dst", 378 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 379def ANDNri : F3_2<2, 0b000101, 380 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 381 "andn $b, $c, $dst", []>; 382def ORrr : F3_1<2, 0b000010, 383 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 384 "or $b, $c, $dst", 385 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 386def ORri : F3_2<2, 0b000010, 387 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 388 "or $b, $c, $dst", 389 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 390def ORNrr : F3_1<2, 0b000110, 391 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 392 "orn $b, $c, $dst", 393 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 394def ORNri : F3_2<2, 0b000110, 395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 396 "orn $b, $c, $dst", []>; 397def XORrr : F3_1<2, 0b000011, 398 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 399 "xor $b, $c, $dst", 400 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 401def XORri : F3_2<2, 0b000011, 402 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 403 "xor $b, $c, $dst", 404 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 405def XNORrr : F3_1<2, 0b000111, 406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 407 "xnor $b, $c, $dst", 408 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 409def XNORri : F3_2<2, 0b000111, 410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 411 "xnor $b, $c, $dst", []>; 412 413// Section B.12 - Shift Instructions, p. 107 414def SLLrr : F3_1<2, 0b100101, 415 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 416 "sll $b, $c, $dst", 417 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 418def SLLri : F3_2<2, 0b100101, 419 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 420 "sll $b, $c, $dst", 421 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 422def SRLrr : F3_1<2, 0b100110, 423 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 424 "srl $b, $c, $dst", 425 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 426def SRLri : F3_2<2, 0b100110, 427 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 428 "srl $b, $c, $dst", 429 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 430def SRArr : F3_1<2, 0b100111, 431 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 432 "sra $b, $c, $dst", 433 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 434def SRAri : F3_2<2, 0b100111, 435 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 436 "sra $b, $c, $dst", 437 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 438 439// Section B.13 - Add Instructions, p. 108 440def ADDrr : F3_1<2, 0b000000, 441 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 442 "add $b, $c, $dst", 443 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 444def ADDri : F3_2<2, 0b000000, 445 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 446 "add $b, $c, $dst", 447 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 448 449// "LEA" forms of add (patterns to make tblgen happy) 450def LEA_ADDri : F3_2<2, 0b000000, 451 (ops IntRegs:$dst, MEMri:$addr), 452 "add ${addr:arith}, $dst", 453 [(set IntRegs:$dst, ADDRri:$addr)]>; 454 455def ADDCCrr : F3_1<2, 0b010000, 456 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 457 "addcc $b, $c, $dst", 458 [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>; 459def ADDCCri : F3_2<2, 0b010000, 460 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 461 "addcc $b, $c, $dst", 462 [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>; 463def ADDXrr : F3_1<2, 0b001000, 464 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 465 "addx $b, $c, $dst", 466 [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>; 467def ADDXri : F3_2<2, 0b001000, 468 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 469 "addx $b, $c, $dst", 470 [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>; 471 472// Section B.15 - Subtract Instructions, p. 110 473def SUBrr : F3_1<2, 0b000100, 474 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 475 "sub $b, $c, $dst", 476 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 477def SUBri : F3_2<2, 0b000100, 478 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 479 "sub $b, $c, $dst", 480 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 481def SUBXrr : F3_1<2, 0b001100, 482 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 483 "subx $b, $c, $dst", 484 [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>; 485def SUBXri : F3_2<2, 0b001100, 486 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 487 "subx $b, $c, $dst", 488 [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>; 489def SUBCCrr : F3_1<2, 0b010100, 490 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 491 "subcc $b, $c, $dst", 492 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>; 493def SUBCCri : F3_2<2, 0b010100, 494 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 495 "subcc $b, $c, $dst", 496 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>; 497def SUBXCCrr: F3_1<2, 0b011100, 498 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 499 "subxcc $b, $c, $dst", []>; 500 501// Section B.18 - Multiply Instructions, p. 113 502def UMULrr : F3_1<2, 0b001010, 503 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 504 "umul $b, $c, $dst", []>; 505def UMULri : F3_2<2, 0b001010, 506 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 507 "umul $b, $c, $dst", []>; 508 509def SMULrr : F3_1<2, 0b001011, 510 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 511 "smul $b, $c, $dst", 512 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 513def SMULri : F3_2<2, 0b001011, 514 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 515 "smul $b, $c, $dst", 516 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 517 518 519// Section B.19 - Divide Instructions, p. 115 520def UDIVrr : F3_1<2, 0b001110, 521 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 522 "udiv $b, $c, $dst", []>; 523def UDIVri : F3_2<2, 0b001110, 524 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 525 "udiv $b, $c, $dst", []>; 526def SDIVrr : F3_1<2, 0b001111, 527 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 528 "sdiv $b, $c, $dst", []>; 529def SDIVri : F3_2<2, 0b001111, 530 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 531 "sdiv $b, $c, $dst", []>; 532 533// Section B.20 - SAVE and RESTORE, p. 117 534def SAVErr : F3_1<2, 0b111100, 535 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 536 "save $b, $c, $dst", []>; 537def SAVEri : F3_2<2, 0b111100, 538 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 539 "save $b, $c, $dst", []>; 540def RESTORErr : F3_1<2, 0b111101, 541 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 542 "restore $b, $c, $dst", []>; 543def RESTOREri : F3_2<2, 0b111101, 544 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 545 "restore $b, $c, $dst", []>; 546 547// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 548 549// conditional branch class: 550class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 551 : F2_2<cc, 0b010, ops, asmstr, pattern> { 552 let isBranch = 1; 553 let isTerminator = 1; 554 let hasDelaySlot = 1; 555 let noResults = 1; 556} 557 558let isBarrier = 1 in 559 def BA : BranchSP<0b1000, (ops brtarget:$dst), 560 "ba $dst", 561 [(br bb:$dst)]>; 562 563// FIXME: the encoding for the JIT should look at the condition field. 564def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc), 565 "b$cc $dst", 566 [(SPbricc bb:$dst, imm:$cc)]>; 567 568 569// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 570 571// floating-point conditional branch class: 572class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 573 : F2_2<cc, 0b110, ops, asmstr, pattern> { 574 let isBranch = 1; 575 let isTerminator = 1; 576 let hasDelaySlot = 1; 577 let noResults = 1; 578} 579 580// FIXME: the encoding for the JIT should look at the condition field. 581def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc), 582 "fb$cc $dst", 583 [(SPbrfcc bb:$dst, imm:$cc)]>; 584 585 586// Section B.24 - Call and Link Instruction, p. 125 587// This is the only Format 1 instruction 588let Uses = [O0, O1, O2, O3, O4, O5], 589 hasDelaySlot = 1, isCall = 1, noResults = 1, 590 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 591 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 592 def CALL : InstSP<(ops calltarget:$dst), 593 "call $dst", []> { 594 bits<30> disp; 595 let op = 1; 596 let Inst{29-0} = disp; 597 } 598 599 // indirect calls 600 def JMPLrr : F3_1<2, 0b111000, 601 (ops MEMrr:$ptr), 602 "call $ptr", 603 [(call ADDRrr:$ptr)]>; 604 def JMPLri : F3_2<2, 0b111000, 605 (ops MEMri:$ptr), 606 "call $ptr", 607 [(call ADDRri:$ptr)]>; 608} 609 610// Section B.28 - Read State Register Instructions 611def RDY : F3_1<2, 0b101000, 612 (ops IntRegs:$dst), 613 "rd %y, $dst", []>; 614 615// Section B.29 - Write State Register Instructions 616def WRYrr : F3_1<2, 0b110000, 617 (ops IntRegs:$b, IntRegs:$c), 618 "wr $b, $c, %y", []>; 619def WRYri : F3_2<2, 0b110000, 620 (ops IntRegs:$b, i32imm:$c), 621 "wr $b, $c, %y", []>; 622 623// Convert Integer to Floating-point Instructions, p. 141 624def FITOS : F3_3<2, 0b110100, 0b011000100, 625 (ops FPRegs:$dst, FPRegs:$src), 626 "fitos $src, $dst", 627 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 628def FITOD : F3_3<2, 0b110100, 0b011001000, 629 (ops DFPRegs:$dst, FPRegs:$src), 630 "fitod $src, $dst", 631 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 632 633// Convert Floating-point to Integer Instructions, p. 142 634def FSTOI : F3_3<2, 0b110100, 0b011010001, 635 (ops FPRegs:$dst, FPRegs:$src), 636 "fstoi $src, $dst", 637 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 638def FDTOI : F3_3<2, 0b110100, 0b011010010, 639 (ops FPRegs:$dst, DFPRegs:$src), 640 "fdtoi $src, $dst", 641 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 642 643// Convert between Floating-point Formats Instructions, p. 143 644def FSTOD : F3_3<2, 0b110100, 0b011001001, 645 (ops DFPRegs:$dst, FPRegs:$src), 646 "fstod $src, $dst", 647 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 648def FDTOS : F3_3<2, 0b110100, 0b011000110, 649 (ops FPRegs:$dst, DFPRegs:$src), 650 "fdtos $src, $dst", 651 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 652 653// Floating-point Move Instructions, p. 144 654def FMOVS : F3_3<2, 0b110100, 0b000000001, 655 (ops FPRegs:$dst, FPRegs:$src), 656 "fmovs $src, $dst", []>; 657def FNEGS : F3_3<2, 0b110100, 0b000000101, 658 (ops FPRegs:$dst, FPRegs:$src), 659 "fnegs $src, $dst", 660 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 661def FABSS : F3_3<2, 0b110100, 0b000001001, 662 (ops FPRegs:$dst, FPRegs:$src), 663 "fabss $src, $dst", 664 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 665 666 667// Floating-point Square Root Instructions, p.145 668def FSQRTS : F3_3<2, 0b110100, 0b000101001, 669 (ops FPRegs:$dst, FPRegs:$src), 670 "fsqrts $src, $dst", 671 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 672def FSQRTD : F3_3<2, 0b110100, 0b000101010, 673 (ops DFPRegs:$dst, DFPRegs:$src), 674 "fsqrtd $src, $dst", 675 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 676 677 678 679// Floating-point Add and Subtract Instructions, p. 146 680def FADDS : F3_3<2, 0b110100, 0b001000001, 681 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 682 "fadds $src1, $src2, $dst", 683 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 684def FADDD : F3_3<2, 0b110100, 0b001000010, 685 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 686 "faddd $src1, $src2, $dst", 687 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 688def FSUBS : F3_3<2, 0b110100, 0b001000101, 689 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 690 "fsubs $src1, $src2, $dst", 691 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 692def FSUBD : F3_3<2, 0b110100, 0b001000110, 693 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 694 "fsubd $src1, $src2, $dst", 695 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 696 697// Floating-point Multiply and Divide Instructions, p. 147 698def FMULS : F3_3<2, 0b110100, 0b001001001, 699 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 700 "fmuls $src1, $src2, $dst", 701 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 702def FMULD : F3_3<2, 0b110100, 0b001001010, 703 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 704 "fmuld $src1, $src2, $dst", 705 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 706def FSMULD : F3_3<2, 0b110100, 0b001101001, 707 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 708 "fsmuld $src1, $src2, $dst", 709 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 710 (fextend FPRegs:$src2)))]>; 711def FDIVS : F3_3<2, 0b110100, 0b001001101, 712 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 713 "fdivs $src1, $src2, $dst", 714 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 715def FDIVD : F3_3<2, 0b110100, 0b001001110, 716 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 717 "fdivd $src1, $src2, $dst", 718 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 719 720// Floating-point Compare Instructions, p. 148 721// Note: the 2nd template arg is different for these guys. 722// Note 2: the result of a FCMP is not available until the 2nd cycle 723// after the instr is retired, but there is no interlock. This behavior 724// is modelled with a forced noop after the instruction. 725def FCMPS : F3_3<2, 0b110101, 0b001010001, 726 (ops FPRegs:$src1, FPRegs:$src2), 727 "fcmps $src1, $src2\n\tnop", 728 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 729def FCMPD : F3_3<2, 0b110101, 0b001010010, 730 (ops DFPRegs:$src1, DFPRegs:$src2), 731 "fcmpd $src1, $src2\n\tnop", 732 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 733 734 735//===----------------------------------------------------------------------===// 736// V9 Instructions 737//===----------------------------------------------------------------------===// 738 739// V9 Conditional Moves. 740let Predicates = [HasV9], isTwoAddress = 1 in { 741 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 742 // FIXME: Add instruction encodings for the JIT some day. 743 def MOVICCrr 744 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), 745 "mov$cc %icc, $F, $dst", 746 [(set IntRegs:$dst, 747 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 748 def MOVICCri 749 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), 750 "mov$cc %icc, $F, $dst", 751 [(set IntRegs:$dst, 752 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 753 754 def MOVFCCrr 755 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), 756 "mov$cc %fcc0, $F, $dst", 757 [(set IntRegs:$dst, 758 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 759 def MOVFCCri 760 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), 761 "mov$cc %fcc0, $F, $dst", 762 [(set IntRegs:$dst, 763 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 764 765 def FMOVS_ICC 766 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), 767 "fmovs$cc %icc, $F, $dst", 768 [(set FPRegs:$dst, 769 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 770 def FMOVD_ICC 771 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 772 "fmovd$cc %icc, $F, $dst", 773 [(set DFPRegs:$dst, 774 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 775 def FMOVS_FCC 776 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), 777 "fmovs$cc %fcc0, $F, $dst", 778 [(set FPRegs:$dst, 779 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 780 def FMOVD_FCC 781 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 782 "fmovd$cc %fcc0, $F, $dst", 783 [(set DFPRegs:$dst, 784 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 785 786} 787 788// Floating-Point Move Instructions, p. 164 of the V9 manual. 789let Predicates = [HasV9] in { 790 def FMOVD : F3_3<2, 0b110100, 0b000000010, 791 (ops DFPRegs:$dst, DFPRegs:$src), 792 "fmovd $src, $dst", []>; 793 def FNEGD : F3_3<2, 0b110100, 0b000000110, 794 (ops DFPRegs:$dst, DFPRegs:$src), 795 "fnegd $src, $dst", 796 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 797 def FABSD : F3_3<2, 0b110100, 0b000001010, 798 (ops DFPRegs:$dst, DFPRegs:$src), 799 "fabsd $src, $dst", 800 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 801} 802 803// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 804// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 805def POPCrr : F3_1<2, 0b101110, 806 (ops IntRegs:$dst, IntRegs:$src), 807 "popc $src, $dst", []>, Requires<[HasV9]>; 808def : Pat<(ctpop IntRegs:$src), 809 (POPCrr (SLLri IntRegs:$src, 0))>; 810 811//===----------------------------------------------------------------------===// 812// Non-Instruction Patterns 813//===----------------------------------------------------------------------===// 814 815// Small immediates. 816def : Pat<(i32 simm13:$val), 817 (ORri G0, imm:$val)>; 818// Arbitrary immediates. 819def : Pat<(i32 imm:$val), 820 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 821 822// subc 823def : Pat<(subc IntRegs:$b, IntRegs:$c), 824 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 825def : Pat<(subc IntRegs:$b, simm13:$val), 826 (SUBCCri IntRegs:$b, imm:$val)>; 827 828// Global addresses, constant pool entries 829def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 830def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 831def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 832def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 833 834// Add reg, lo. This is used when taking the addr of a global/constpool entry. 835def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 836 (ADDri IntRegs:$r, tglobaladdr:$in)>; 837def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 838 (ADDri IntRegs:$r, tconstpool:$in)>; 839 840// Calls: 841def : Pat<(call tglobaladdr:$dst), 842 (CALL tglobaladdr:$dst)>; 843def : Pat<(call texternalsym:$dst), 844 (CALL texternalsym:$dst)>; 845 846def : Pat<(ret), (RETL)>; 847 848// Map integer extload's to zextloads. 849def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 850def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 851def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 852def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 853def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 854def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 855 856// zextload bool -> zextload byte 857def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 858def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 859 860// truncstore bool -> truncstore byte. 861def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 862 (STBrr ADDRrr:$addr, IntRegs:$src)>; 863def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 864 (STBri ADDRri:$addr, IntRegs:$src)>; 865