SparcInstrInfo.td revision 2db3ff66f1183fa65bd5102ad255a798f76cb3b2
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcV8InstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Instruction Pattern Stuff 22//===----------------------------------------------------------------------===// 23 24def simm13 : PatLeaf<(imm), [{ 25 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 26 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 27}]>; 28 29def LO10 : SDNodeXForm<imm, [{ 30 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 31}]>; 32 33def HI22 : SDNodeXForm<imm, [{ 34 // Transformation function: shift the immediate value down into the low bits. 35 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 36}]>; 37 38def SETHIimm : PatLeaf<(imm), [{ 39 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 40}], HI22>; 41 42// Addressing modes. 43def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 44def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 45 46// Address operands 47def MEMrr : Operand<i32> { 48 let PrintMethod = "printMemOperand"; 49 let NumMIOperands = 2; 50 let MIOperandInfo = (ops IntRegs, IntRegs); 51} 52def MEMri : Operand<i32> { 53 let PrintMethod = "printMemOperand"; 54 let NumMIOperands = 2; 55 let MIOperandInfo = (ops IntRegs, i32imm); 56} 57 58// Branch targets have OtherVT type. 59def brtarget : Operand<OtherVT>; 60def calltarget : Operand<i32>; 61 62def SDTV8cmpicc : 63SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 64def SDTV8cmpfcc : 65SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 66def SDTV8brcc : 67SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>, 68 SDTCisVT<2, FlagVT>]>; 69def SDTV8selectcc : 70SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 71 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>; 72 73def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; 74def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; 75def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 76def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 77 78def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 79def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 80 81def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>; 82def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>; 83 84def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>; 85def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>; 86 87// These are target-independent nodes, but have target-specific formats. 88def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 89def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>; 90def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>; 91 92def SDT_V8Call : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>, 93 SDTCisVT<2, FlagVT>]>; 94def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>; 95 96//===----------------------------------------------------------------------===// 97// Instructions 98//===----------------------------------------------------------------------===// 99 100// Pseudo instructions. 101class Pseudo<dag ops, string asmstr, list<dag> pattern> 102 : InstV8<ops, asmstr, pattern>; 103 104def PHI : Pseudo<(ops variable_ops), "PHI", []>; 105def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 106 "!ADJCALLSTACKDOWN $amt", 107 [(callseq_start imm:$amt)]>; 108def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 109 "!ADJCALLSTACKUP $amt", 110 [(callseq_end imm:$amt)]>; 111def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>; 112def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 113 "!FpMOVD", []>; // pseudo 64-bit double move 114 115// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 116// scheduler into a branch sequence. This has to handle all permutations of 117// selection between i32/f32/f64 on ICC and FCC. 118let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 119 def SELECT_CC_Int_ICC 120 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 121 "; SELECT_CC_Int_ICC PSEUDO!", 122 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F, 123 imm:$Cond, ICC))]>; 124 def SELECT_CC_Int_FCC 125 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 126 "; SELECT_CC_Int_FCC PSEUDO!", 127 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F, 128 imm:$Cond, FCC))]>; 129 def SELECT_CC_FP_ICC 130 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 131 "; SELECT_CC_FP_ICC PSEUDO!", 132 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F, 133 imm:$Cond, ICC))]>; 134 def SELECT_CC_FP_FCC 135 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 136 "; SELECT_CC_FP_FCC PSEUDO!", 137 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F, 138 imm:$Cond, FCC))]>; 139 def SELECT_CC_DFP_ICC 140 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 141 "; SELECT_CC_DFP_ICC PSEUDO!", 142 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F, 143 imm:$Cond, ICC))]>; 144 def SELECT_CC_DFP_FCC 145 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 146 "; SELECT_CC_DFP_FCC PSEUDO!", 147 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F, 148 imm:$Cond, FCC))]>; 149} 150 151// Section A.3 - Synthetic Instructions, p. 85 152// special cases of JMPL: 153let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 154 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 155 def RETL: F3_2<2, 0b111000, (ops), 156 "retl", [(ret)]>; 157} 158 159// Section B.1 - Load Integer Instructions, p. 90 160def LDSBrr : F3_1<3, 0b001001, 161 (ops IntRegs:$dst, MEMrr:$addr), 162 "ldsb [$addr], $dst", 163 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 164def LDSBri : F3_2<3, 0b001001, 165 (ops IntRegs:$dst, MEMri:$addr), 166 "ldsb [$addr], $dst", 167 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 168def LDSHrr : F3_1<3, 0b001010, 169 (ops IntRegs:$dst, MEMrr:$addr), 170 "ldsh [$addr], $dst", 171 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 172def LDSHri : F3_2<3, 0b001010, 173 (ops IntRegs:$dst, MEMri:$addr), 174 "ldsh [$addr], $dst", 175 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 176def LDUBrr : F3_1<3, 0b000001, 177 (ops IntRegs:$dst, MEMrr:$addr), 178 "ldub [$addr], $dst", 179 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 180def LDUBri : F3_2<3, 0b000001, 181 (ops IntRegs:$dst, MEMri:$addr), 182 "ldub [$addr], $dst", 183 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 184def LDUHrr : F3_1<3, 0b000010, 185 (ops IntRegs:$dst, MEMrr:$addr), 186 "lduh [$addr], $dst", 187 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 188def LDUHri : F3_2<3, 0b000010, 189 (ops IntRegs:$dst, MEMri:$addr), 190 "lduh [$addr], $dst", 191 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 192def LDrr : F3_1<3, 0b000000, 193 (ops IntRegs:$dst, MEMrr:$addr), 194 "ld [$addr], $dst", 195 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 196def LDri : F3_2<3, 0b000000, 197 (ops IntRegs:$dst, MEMri:$addr), 198 "ld [$addr], $dst", 199 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 200 201// Section B.2 - Load Floating-point Instructions, p. 92 202def LDFrr : F3_1<3, 0b100000, 203 (ops FPRegs:$dst, MEMrr:$addr), 204 "ld [$addr], $dst", 205 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 206def LDFri : F3_2<3, 0b100000, 207 (ops FPRegs:$dst, MEMri:$addr), 208 "ld [$addr], $dst", 209 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 210def LDDFrr : F3_1<3, 0b100011, 211 (ops DFPRegs:$dst, MEMrr:$addr), 212 "ldd [$addr], $dst", 213 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 214def LDDFri : F3_2<3, 0b100011, 215 (ops DFPRegs:$dst, MEMri:$addr), 216 "ldd [$addr], $dst", 217 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 218 219// Section B.4 - Store Integer Instructions, p. 95 220def STBrr : F3_1<3, 0b000101, 221 (ops MEMrr:$addr, IntRegs:$src), 222 "stb $src, [$addr]", 223 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 224def STBri : F3_2<3, 0b000101, 225 (ops MEMri:$addr, IntRegs:$src), 226 "stb $src, [$addr]", 227 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 228def STHrr : F3_1<3, 0b000110, 229 (ops MEMrr:$addr, IntRegs:$src), 230 "sth $src, [$addr]", 231 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 232def STHri : F3_2<3, 0b000110, 233 (ops MEMri:$addr, IntRegs:$src), 234 "sth $src, [$addr]", 235 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 236def STrr : F3_1<3, 0b000100, 237 (ops MEMrr:$addr, IntRegs:$src), 238 "st $src, [$addr]", 239 [(store IntRegs:$src, ADDRrr:$addr)]>; 240def STri : F3_2<3, 0b000100, 241 (ops MEMri:$addr, IntRegs:$src), 242 "st $src, [$addr]", 243 [(store IntRegs:$src, ADDRri:$addr)]>; 244 245// Section B.5 - Store Floating-point Instructions, p. 97 246def STFrr : F3_1<3, 0b100100, 247 (ops MEMrr:$addr, FPRegs:$src), 248 "st $src, [$addr]", 249 [(store FPRegs:$src, ADDRrr:$addr)]>; 250def STFri : F3_2<3, 0b100100, 251 (ops MEMri:$addr, FPRegs:$src), 252 "st $src, [$addr]", 253 [(store FPRegs:$src, ADDRri:$addr)]>; 254def STDFrr : F3_1<3, 0b100111, 255 (ops MEMrr:$addr, DFPRegs:$src), 256 "std $src, [$addr]", 257 [(store DFPRegs:$src, ADDRrr:$addr)]>; 258def STDFri : F3_2<3, 0b100111, 259 (ops MEMri:$addr, DFPRegs:$src), 260 "std $src, [$addr]", 261 [(store DFPRegs:$src, ADDRri:$addr)]>; 262 263// Section B.9 - SETHI Instruction, p. 104 264def SETHIi: F2_1<0b100, 265 (ops IntRegs:$dst, i32imm:$src), 266 "sethi $src, $dst", 267 [(set IntRegs:$dst, SETHIimm:$src)]>; 268 269// Section B.10 - NOP Instruction, p. 105 270// (It's a special case of SETHI) 271let rd = 0, imm22 = 0 in 272 def NOP : F2_1<0b100, (ops), "nop", []>; 273 274// Section B.11 - Logical Instructions, p. 106 275def ANDrr : F3_1<2, 0b000001, 276 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 277 "and $b, $c, $dst", 278 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 279def ANDri : F3_2<2, 0b000001, 280 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 281 "and $b, $c, $dst", 282 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 283def ANDNrr : F3_1<2, 0b000101, 284 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 285 "andn $b, $c, $dst", 286 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 287def ANDNri : F3_2<2, 0b000101, 288 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 289 "andn $b, $c, $dst", []>; 290def ORrr : F3_1<2, 0b000010, 291 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 292 "or $b, $c, $dst", 293 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 294def ORri : F3_2<2, 0b000010, 295 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 296 "or $b, $c, $dst", 297 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 298def ORNrr : F3_1<2, 0b000110, 299 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 300 "orn $b, $c, $dst", 301 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 302def ORNri : F3_2<2, 0b000110, 303 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 304 "orn $b, $c, $dst", []>; 305def XORrr : F3_1<2, 0b000011, 306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 307 "xor $b, $c, $dst", 308 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 309def XORri : F3_2<2, 0b000011, 310 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 311 "xor $b, $c, $dst", 312 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 313def XNORrr : F3_1<2, 0b000111, 314 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 315 "xnor $b, $c, $dst", 316 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>; 317def XNORri : F3_2<2, 0b000111, 318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 319 "xnor $b, $c, $dst", []>; 320 321// Section B.12 - Shift Instructions, p. 107 322def SLLrr : F3_1<2, 0b100101, 323 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 324 "sll $b, $c, $dst", 325 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 326def SLLri : F3_2<2, 0b100101, 327 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 328 "sll $b, $c, $dst", 329 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 330def SRLrr : F3_1<2, 0b100110, 331 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 332 "srl $b, $c, $dst", 333 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 334def SRLri : F3_2<2, 0b100110, 335 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 336 "srl $b, $c, $dst", 337 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 338def SRArr : F3_1<2, 0b100111, 339 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 340 "sra $b, $c, $dst", 341 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 342def SRAri : F3_2<2, 0b100111, 343 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 344 "sra $b, $c, $dst", 345 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 346 347// Section B.13 - Add Instructions, p. 108 348def ADDrr : F3_1<2, 0b000000, 349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 350 "add $b, $c, $dst", 351 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 352def ADDri : F3_2<2, 0b000000, 353 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 354 "add $b, $c, $dst", 355 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 356def ADDCCrr : F3_1<2, 0b010000, 357 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 358 "addcc $b, $c, $dst", []>; 359def ADDCCri : F3_2<2, 0b010000, 360 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 361 "addcc $b, $c, $dst", []>; 362def ADDXrr : F3_1<2, 0b001000, 363 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 364 "addx $b, $c, $dst", []>; 365def ADDXri : F3_2<2, 0b001000, 366 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 367 "addx $b, $c, $dst", []>; 368 369// Section B.15 - Subtract Instructions, p. 110 370def SUBrr : F3_1<2, 0b000100, 371 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 372 "sub $b, $c, $dst", 373 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 374def SUBri : F3_2<2, 0b000100, 375 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 376 "sub $b, $c, $dst", 377 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 378def SUBXrr : F3_1<2, 0b001100, 379 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 380 "subx $b, $c, $dst", []>; 381def SUBXri : F3_2<2, 0b001100, 382 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 383 "subx $b, $c, $dst", []>; 384def SUBCCrr : F3_1<2, 0b010100, 385 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 386 "subcc $b, $c, $dst", []>; 387def SUBCCri : F3_2<2, 0b010100, 388 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 389 "subcc $b, $c, $dst", []>; 390def SUBXCCrr: F3_1<2, 0b011100, 391 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 392 "subxcc $b, $c, $dst", []>; 393 394// Section B.18 - Multiply Instructions, p. 113 395def UMULrr : F3_1<2, 0b001010, 396 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 397 "umul $b, $c, $dst", []>; 398def UMULri : F3_2<2, 0b001010, 399 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 400 "umul $b, $c, $dst", []>; 401def SMULrr : F3_1<2, 0b001011, 402 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 403 "smul $b, $c, $dst", 404 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 405def SMULri : F3_2<2, 0b001011, 406 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 407 "smul $b, $c, $dst", 408 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 409 410// Section B.19 - Divide Instructions, p. 115 411def UDIVrr : F3_1<2, 0b001110, 412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 413 "udiv $b, $c, $dst", []>; 414def UDIVri : F3_2<2, 0b001110, 415 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 416 "udiv $b, $c, $dst", []>; 417def SDIVrr : F3_1<2, 0b001111, 418 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 419 "sdiv $b, $c, $dst", []>; 420def SDIVri : F3_2<2, 0b001111, 421 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 422 "sdiv $b, $c, $dst", []>; 423 424// Section B.20 - SAVE and RESTORE, p. 117 425def SAVErr : F3_1<2, 0b111100, 426 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 427 "save $b, $c, $dst", []>; 428def SAVEri : F3_2<2, 0b111100, 429 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 430 "save $b, $c, $dst", []>; 431def RESTORErr : F3_1<2, 0b111101, 432 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 433 "restore $b, $c, $dst", []>; 434def RESTOREri : F3_2<2, 0b111101, 435 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 436 "restore $b, $c, $dst", []>; 437 438// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 439 440// conditional branch class: 441class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 442 : F2_2<cc, 0b010, ops, asmstr, pattern> { 443 let isBranch = 1; 444 let isTerminator = 1; 445 let hasDelaySlot = 1; 446} 447 448let isBarrier = 1 in 449 def BA : BranchV8<0b1000, (ops brtarget:$dst), 450 "ba $dst", 451 [(br bb:$dst)]>; 452def BNE : BranchV8<0b1001, (ops brtarget:$dst), 453 "bne $dst", 454 [(V8bricc bb:$dst, SETNE, ICC)]>; 455def BE : BranchV8<0b0001, (ops brtarget:$dst), 456 "be $dst", 457 [(V8bricc bb:$dst, SETEQ, ICC)]>; 458def BG : BranchV8<0b1010, (ops brtarget:$dst), 459 "bg $dst", 460 [(V8bricc bb:$dst, SETGT, ICC)]>; 461def BLE : BranchV8<0b0010, (ops brtarget:$dst), 462 "ble $dst", 463 [(V8bricc bb:$dst, SETLE, ICC)]>; 464def BGE : BranchV8<0b1011, (ops brtarget:$dst), 465 "bge $dst", 466 [(V8bricc bb:$dst, SETGE, ICC)]>; 467def BL : BranchV8<0b0011, (ops brtarget:$dst), 468 "bl $dst", 469 [(V8bricc bb:$dst, SETLT, ICC)]>; 470def BGU : BranchV8<0b1100, (ops brtarget:$dst), 471 "bgu $dst", 472 [(V8bricc bb:$dst, SETUGT, ICC)]>; 473def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 474 "bleu $dst", 475 [(V8bricc bb:$dst, SETULE, ICC)]>; 476def BCC : BranchV8<0b1101, (ops brtarget:$dst), 477 "bcc $dst", 478 [(V8bricc bb:$dst, SETUGE, ICC)]>; 479def BCS : BranchV8<0b0101, (ops brtarget:$dst), 480 "bcs $dst", 481 [(V8bricc bb:$dst, SETULT, ICC)]>; 482 483// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 484 485// floating-point conditional branch class: 486class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 487 : F2_2<cc, 0b110, ops, asmstr, pattern> { 488 let isBranch = 1; 489 let isTerminator = 1; 490 let hasDelaySlot = 1; 491} 492 493def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 494 "fbu $dst", 495 [(V8brfcc bb:$dst, SETUO, FCC)]>; 496def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 497 "fbg $dst", 498 [(V8brfcc bb:$dst, SETGT, FCC)]>; 499def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 500 "fbug $dst", 501 [(V8brfcc bb:$dst, SETUGT, FCC)]>; 502def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 503 "fbl $dst", 504 [(V8brfcc bb:$dst, SETLT, FCC)]>; 505def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 506 "fbul $dst", 507 [(V8brfcc bb:$dst, SETULT, FCC)]>; 508def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 509 "fblg $dst", 510 [(V8brfcc bb:$dst, SETONE, FCC)]>; 511def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 512 "fbne $dst", 513 [(V8brfcc bb:$dst, SETNE, FCC)]>; 514def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 515 "fbe $dst", 516 [(V8brfcc bb:$dst, SETEQ, FCC)]>; 517def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 518 "fbue $dst", 519 [(V8brfcc bb:$dst, SETUEQ, FCC)]>; 520def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 521 "fbge $dst", 522 [(V8brfcc bb:$dst, SETGE, FCC)]>; 523def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 524 "fbuge $dst", 525 [(V8brfcc bb:$dst, SETUGE, FCC)]>; 526def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 527 "fble $dst", 528 [(V8brfcc bb:$dst, SETLE, FCC)]>; 529def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 530 "fbule $dst", 531 [(V8brfcc bb:$dst, SETULE, FCC)]>; 532def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 533 "fbo $dst", 534 [(V8brfcc bb:$dst, SETO, FCC)]>; 535 536 537 538// Section B.24 - Call and Link Instruction, p. 125 539// This is the only Format 1 instruction 540let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1, 541 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 542 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 543 // pc-relative call: 544 def CALL : InstV8<(ops calltarget:$dst), 545 "call $dst", 546 [(set ICC/*bogus*/, (call tglobaladdr:$dst, ICC/*bogus*/))]> { 547 bits<30> disp; 548 let op = 1; 549 let Inst{29-0} = disp; 550 } 551 552 // indirect calls 553 def JMPLrr : F3_1<2, 0b111000, 554 (ops MEMrr:$ptr), 555 "jmpl $ptr", 556 [(set ICC/*bogus*/, (call ADDRrr:$ptr, ICC/*bogus*/))]>; 557 def JMPLri : F3_2<2, 0b111000, 558 (ops MEMri:$ptr), 559 "jmpl $ptr", 560 [(set ICC/*bogus*/, (call ADDRri:$ptr, ICC/*bogus*/))]>; 561} 562 563// Section B.28 - Read State Register Instructions 564def RDY : F3_1<2, 0b101000, 565 (ops IntRegs:$dst), 566 "rdy $dst", []>; 567 568// Section B.29 - Write State Register Instructions 569def WRYrr : F3_1<2, 0b110000, 570 (ops IntRegs:$b, IntRegs:$c), 571 "wr $b, $c, %y", []>; 572def WRYri : F3_2<2, 0b110000, 573 (ops IntRegs:$b, i32imm:$c), 574 "wr $b, $c, %y", []>; 575 576// Convert Integer to Floating-point Instructions, p. 141 577def FITOS : F3_3<2, 0b110100, 0b011000100, 578 (ops FPRegs:$dst, FPRegs:$src), 579 "fitos $src, $dst", 580 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 581def FITOD : F3_3<2, 0b110100, 0b011001000, 582 (ops DFPRegs:$dst, DFPRegs:$src), 583 "fitod $src, $dst", 584 [(set DFPRegs:$dst, (V8itof DFPRegs:$src))]>; 585 586// Convert Floating-point to Integer Instructions, p. 142 587def FSTOI : F3_3<2, 0b110100, 0b011010001, 588 (ops FPRegs:$dst, FPRegs:$src), 589 "fstoi $src, $dst", 590 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 591def FDTOI : F3_3<2, 0b110100, 0b011010010, 592 (ops DFPRegs:$dst, DFPRegs:$src), 593 "fdtoi $src, $dst", 594 [(set DFPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 595 596// Convert between Floating-point Formats Instructions, p. 143 597def FSTOD : F3_3<2, 0b110100, 0b011001001, 598 (ops DFPRegs:$dst, FPRegs:$src), 599 "fstod $src, $dst", 600 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 601def FDTOS : F3_3<2, 0b110100, 0b011000110, 602 (ops FPRegs:$dst, DFPRegs:$src), 603 "fdtos $src, $dst", 604 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 605 606// Floating-point Move Instructions, p. 144 607def FMOVS : F3_3<2, 0b110100, 0b000000001, 608 (ops FPRegs:$dst, FPRegs:$src), 609 "fmovs $src, $dst", []>; 610def FNEGS : F3_3<2, 0b110100, 0b000000101, 611 (ops FPRegs:$dst, FPRegs:$src), 612 "fnegs $src, $dst", 613 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 614def FABSS : F3_3<2, 0b110100, 0b000001001, 615 (ops FPRegs:$dst, FPRegs:$src), 616 "fabss $src, $dst", 617 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 618// FIXME: ADD FNEGD/FABSD pseudo instructions. 619 620 621// Floating-point Square Root Instructions, p.145 622def FSQRTS : F3_3<2, 0b110100, 0b000101001, 623 (ops FPRegs:$dst, FPRegs:$src), 624 "fsqrts $src, $dst", 625 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 626def FSQRTD : F3_3<2, 0b110100, 0b000101010, 627 (ops DFPRegs:$dst, DFPRegs:$src), 628 "fsqrtd $src, $dst", 629 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 630 631 632 633// Floating-point Add and Subtract Instructions, p. 146 634def FADDS : F3_3<2, 0b110100, 0b001000001, 635 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 636 "fadds $src1, $src2, $dst", 637 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 638def FADDD : F3_3<2, 0b110100, 0b001000010, 639 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 640 "faddd $src1, $src2, $dst", 641 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 642def FSUBS : F3_3<2, 0b110100, 0b001000101, 643 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 644 "fsubs $src1, $src2, $dst", 645 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 646def FSUBD : F3_3<2, 0b110100, 0b001000110, 647 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 648 "fsubd $src1, $src2, $dst", 649 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 650 651// Floating-point Multiply and Divide Instructions, p. 147 652def FMULS : F3_3<2, 0b110100, 0b001001001, 653 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 654 "fmuls $src1, $src2, $dst", 655 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 656def FMULD : F3_3<2, 0b110100, 0b001001010, 657 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 658 "fmuld $src1, $src2, $dst", 659 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 660def FSMULD : F3_3<2, 0b110100, 0b001101001, 661 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 662 "fsmuld $src1, $src2, $dst", 663 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 664 (fextend FPRegs:$src2)))]>; 665def FDIVS : F3_3<2, 0b110100, 0b001001101, 666 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 667 "fdivs $src1, $src2, $dst", 668 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 669def FDIVD : F3_3<2, 0b110100, 0b001001110, 670 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 671 "fdivd $src1, $src2, $dst", 672 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 673 674// Floating-point Compare Instructions, p. 148 675// Note: the 2nd template arg is different for these guys. 676// Note 2: the result of a FCMP is not available until the 2nd cycle 677// after the instr is retired, but there is no interlock. This behavior 678// is modelled with a forced noop after the instruction. 679def FCMPS : F3_3<2, 0b110101, 0b001010001, 680 (ops FPRegs:$src1, FPRegs:$src2), 681 "fcmps $src1, $src2\n\tnop", 682 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 683def FCMPD : F3_3<2, 0b110101, 0b001010010, 684 (ops DFPRegs:$src1, DFPRegs:$src2), 685 "fcmpd $src1, $src2\n\tnop", 686 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 687 688//===----------------------------------------------------------------------===// 689// Non-Instruction Patterns 690//===----------------------------------------------------------------------===// 691 692// Small immediates. 693def : Pat<(i32 simm13:$val), 694 (ORri G0, imm:$val)>; 695// Arbitrary immediates. 696def : Pat<(i32 imm:$val), 697 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 698 699// Global addresses, constant pool entries 700def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 701def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 702def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 703def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 704