SparcInstrInfo.td revision 53ec2035eb686c25013d47405fd0b178b60d59c8
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42def LO10 : SDNodeXForm<imm, [{ 43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 44}]>; 45 46def HI22 : SDNodeXForm<imm, [{ 47 // Transformation function: shift the immediate value down into the low bits. 48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 49}]>; 50 51def SETHIimm : PatLeaf<(imm), [{ 52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 53}], HI22>; 54 55// Addressing modes. 56def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 57def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 58 59// Address operands 60def MEMrr : Operand<i32> { 61 let PrintMethod = "printMemOperand"; 62 let NumMIOperands = 2; 63 let MIOperandInfo = (ops IntRegs, IntRegs); 64} 65def MEMri : Operand<i32> { 66 let PrintMethod = "printMemOperand"; 67 let NumMIOperands = 2; 68 let MIOperandInfo = (ops IntRegs, i32imm); 69} 70 71//===----------------------------------------------------------------------===// 72// Instructions 73//===----------------------------------------------------------------------===// 74 75// Pseudo instructions. 76class PseudoInstV8<string asmstr, dag ops> : InstV8 { 77 let AsmString = asmstr; 78 dag OperandList = ops; 79} 80def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 81def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 82 (ops i32imm:$amt)>; 83def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 84 (ops i32imm:$amt)>; 85//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 86def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 87 (ops IntRegs:$dst)>; 88def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 89 90// Section A.3 - Synthetic Instructions, p. 85 91// special cases of JMPL: 92let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 94 def RET : F3_2<2, 0b111000, 95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 96 "ret $b, $c, $dst", []>; 97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 98 def RETL: F3_2<2, 0b111000, (ops), 99 "retl", [(ret)]>; 100} 101// CMP is a special case of SUBCC where destination is ignored, by setting it to 102// %g0 (hardwired zero). 103// FIXME: should keep track of the fact that it defs the integer condition codes 104let rd = 0 in 105 def CMPri: F3_2<2, 0b010100, 106 (ops IntRegs:$b, i32imm:$c), 107 "cmp $b, $c", []>; 108 109// Section B.1 - Load Integer Instructions, p. 90 110def LDSBrr : F3_1<3, 0b001001, 111 (ops IntRegs:$dst, MEMrr:$addr), 112 "ldsb [$addr], $dst", 113 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 114def LDSBri : F3_2<3, 0b001001, 115 (ops IntRegs:$dst, MEMri:$addr), 116 "ldsb [$addr], $dst", 117 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 118def LDSHrr : F3_1<3, 0b001010, 119 (ops IntRegs:$dst, MEMrr:$addr), 120 "ldsh [$addr], $dst", 121 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 122def LDSHri : F3_2<3, 0b001010, 123 (ops IntRegs:$dst, MEMri:$addr), 124 "ldsh [$addr], $dst", 125 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 126def LDUBrr : F3_1<3, 0b000001, 127 (ops IntRegs:$dst, MEMrr:$addr), 128 "ldub [$addr], $dst", 129 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 130def LDUBri : F3_2<3, 0b000001, 131 (ops IntRegs:$dst, MEMri:$addr), 132 "ldub [$addr], $dst", 133 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 134def LDUHrr : F3_1<3, 0b000010, 135 (ops IntRegs:$dst, MEMrr:$addr), 136 "lduh [$addr], $dst", 137 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 138def LDUHri : F3_2<3, 0b000010, 139 (ops IntRegs:$dst, MEMri:$addr), 140 "lduh [$addr], $dst", 141 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 142def LDrr : F3_1<3, 0b000000, 143 (ops IntRegs:$dst, MEMrr:$addr), 144 "ld [$addr], $dst", 145 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 146def LDri : F3_2<3, 0b000000, 147 (ops IntRegs:$dst, MEMri:$addr), 148 "ld [$addr], $dst", 149 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 150def LDDrr : F3_1<3, 0b000011, 151 (ops IntRegs:$dst, MEMrr:$addr), 152 "ldd [$addr], $dst", []>; 153def LDDri : F3_2<3, 0b000011, 154 (ops IntRegs:$dst, MEMri:$addr), 155 "ldd [$addr], $dst", []>; 156 157// Section B.2 - Load Floating-point Instructions, p. 92 158def LDFrr : F3_1<3, 0b100000, 159 (ops FPRegs:$dst, MEMrr:$addr), 160 "ld [$addr], $dst", 161 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 162def LDFri : F3_2<3, 0b100000, 163 (ops FPRegs:$dst, MEMri:$addr), 164 "ld [$addr], $dst", 165 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 166def LDDFrr : F3_1<3, 0b100011, 167 (ops DFPRegs:$dst, MEMrr:$addr), 168 "ldd [$addr], $dst", 169 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 170def LDDFri : F3_2<3, 0b100011, 171 (ops DFPRegs:$dst, MEMri:$addr), 172 "ldd [$addr], $dst", 173 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 174 175// Section B.4 - Store Integer Instructions, p. 95 176def STBrr : F3_1<3, 0b000101, 177 (ops MEMrr:$addr, IntRegs:$src), 178 "stb $src, [$addr]", 179 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 180def STBri : F3_2<3, 0b000101, 181 (ops MEMri:$addr, IntRegs:$src), 182 "stb $src, [$addr]", 183 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 184def STHrr : F3_1<3, 0b000110, 185 (ops MEMrr:$addr, IntRegs:$src), 186 "sth $src, [$addr]", 187 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 188def STHri : F3_2<3, 0b000110, 189 (ops MEMri:$addr, IntRegs:$src), 190 "sth $src, [$addr]", 191 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 192def STrr : F3_1<3, 0b000100, 193 (ops MEMrr:$addr, IntRegs:$src), 194 "st $src, [$addr]", 195 [(store IntRegs:$src, ADDRrr:$addr)]>; 196def STri : F3_2<3, 0b000100, 197 (ops MEMri:$addr, IntRegs:$src), 198 "st $src, [$addr]", 199 [(store IntRegs:$src, ADDRri:$addr)]>; 200def STDrr : F3_1<3, 0b000111, 201 (ops MEMrr:$addr, IntRegs:$src), 202 "std $src, [$addr]", []>; 203def STDri : F3_2<3, 0b000111, 204 (ops MEMri:$addr, IntRegs:$src), 205 "std $src, [$addr]", []>; 206 207// Section B.5 - Store Floating-point Instructions, p. 97 208def STFrr : F3_1<3, 0b100100, 209 (ops MEMrr:$addr, FPRegs:$src), 210 "st $src, [$addr]", 211 [(store FPRegs:$src, ADDRrr:$addr)]>; 212def STFri : F3_2<3, 0b100100, 213 (ops MEMri:$addr, FPRegs:$src), 214 "st $src, [$addr]", 215 [(store FPRegs:$src, ADDRri:$addr)]>; 216def STDFrr : F3_1<3, 0b100111, 217 (ops MEMrr:$addr, DFPRegs:$src), 218 "std $src, [$addr]", 219 [(store DFPRegs:$src, ADDRrr:$addr)]>; 220def STDFri : F3_2<3, 0b100111, 221 (ops MEMri:$addr, DFPRegs:$src), 222 "std $src, [$addr]", 223 [(store DFPRegs:$src, ADDRri:$addr)]>; 224 225// Section B.9 - SETHI Instruction, p. 104 226def SETHIi: F2_1<0b100, 227 (ops IntRegs:$dst, i32imm:$src), 228 "sethi $src, $dst", 229 [(set IntRegs:$dst, SETHIimm:$src)]>; 230 231// Section B.10 - NOP Instruction, p. 105 232// (It's a special case of SETHI) 233let rd = 0, imm22 = 0 in 234 def NOP : F2_1<0b100, (ops), "nop", []>; 235 236// Section B.11 - Logical Instructions, p. 106 237def ANDrr : F3_1<2, 0b000001, 238 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 239 "and $b, $c, $dst", 240 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 241def ANDri : F3_2<2, 0b000001, 242 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 243 "and $b, $c, $dst", 244 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 245def ANDCCrr : F3_1<2, 0b010001, 246 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 247 "andcc $b, $c, $dst", []>; 248def ANDCCri : F3_2<2, 0b010001, 249 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 250 "andcc $b, $c, $dst", []>; 251def ANDNrr : F3_1<2, 0b000101, 252 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 253 "andn $b, $c, $dst", []>; 254def ANDNri : F3_2<2, 0b000101, 255 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 256 "andn $b, $c, $dst", []>; 257def ANDNCCrr: F3_1<2, 0b010101, 258 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 259 "andncc $b, $c, $dst", []>; 260def ANDNCCri: F3_2<2, 0b010101, 261 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 262 "andncc $b, $c, $dst", []>; 263def ORrr : F3_1<2, 0b000010, 264 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 265 "or $b, $c, $dst", 266 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 267def ORri : F3_2<2, 0b000010, 268 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 269 "or $b, $c, $dst", 270 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 271def ORCCrr : F3_1<2, 0b010010, 272 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 273 "orcc $b, $c, $dst", []>; 274def ORCCri : F3_2<2, 0b010010, 275 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 276 "orcc $b, $c, $dst", []>; 277def ORNrr : F3_1<2, 0b000110, 278 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 279 "orn $b, $c, $dst", []>; 280def ORNri : F3_2<2, 0b000110, 281 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 282 "orn $b, $c, $dst", []>; 283def ORNCCrr : F3_1<2, 0b010110, 284 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 285 "orncc $b, $c, $dst", []>; 286def ORNCCri : F3_2<2, 0b010110, 287 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 288 "orncc $b, $c, $dst", []>; 289def XORrr : F3_1<2, 0b000011, 290 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 291 "xor $b, $c, $dst", 292 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 293def XORri : F3_2<2, 0b000011, 294 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 295 "xor $b, $c, $dst", 296 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 297def XORCCrr : F3_1<2, 0b010011, 298 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 299 "xorcc $b, $c, $dst", []>; 300def XORCCri : F3_2<2, 0b010011, 301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 302 "xorcc $b, $c, $dst", []>; 303def XNORrr : F3_1<2, 0b000111, 304 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 305 "xnor $b, $c, $dst", []>; 306def XNORri : F3_2<2, 0b000111, 307 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 308 "xnor $b, $c, $dst", []>; 309def XNORCCrr: F3_1<2, 0b010111, 310 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 311 "xnorcc $b, $c, $dst", []>; 312def XNORCCri: F3_2<2, 0b010111, 313 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 314 "xnorcc $b, $c, $dst", []>; 315 316// Section B.12 - Shift Instructions, p. 107 317def SLLrr : F3_1<2, 0b100101, 318 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 319 "sll $b, $c, $dst", 320 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 321def SLLri : F3_2<2, 0b100101, 322 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 323 "sll $b, $c, $dst", 324 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 325def SRLrr : F3_1<2, 0b100110, 326 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 327 "srl $b, $c, $dst", 328 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 329def SRLri : F3_2<2, 0b100110, 330 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 331 "srl $b, $c, $dst", 332 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 333def SRArr : F3_1<2, 0b100111, 334 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 335 "sra $b, $c, $dst", 336 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 337def SRAri : F3_2<2, 0b100111, 338 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 339 "sra $b, $c, $dst", 340 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 341 342// Section B.13 - Add Instructions, p. 108 343def ADDrr : F3_1<2, 0b000000, 344 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 345 "add $b, $c, $dst", 346 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 347def ADDri : F3_2<2, 0b000000, 348 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 349 "add $b, $c, $dst", 350 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 351def ADDCCrr : F3_1<2, 0b010000, 352 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 353 "addcc $b, $c, $dst", []>; 354def ADDCCri : F3_2<2, 0b010000, 355 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 356 "addcc $b, $c, $dst", []>; 357def ADDXrr : F3_1<2, 0b001000, 358 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 359 "addx $b, $c, $dst", []>; 360def ADDXri : F3_2<2, 0b001000, 361 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 362 "addx $b, $c, $dst", []>; 363def ADDXCCrr: F3_1<2, 0b011000, 364 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 365 "addxcc $b, $c, $dst", []>; 366def ADDXCCri: F3_2<2, 0b011000, 367 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 368 "addxcc $b, $c, $dst", []>; 369 370// Section B.15 - Subtract Instructions, p. 110 371def SUBrr : F3_1<2, 0b000100, 372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 373 "sub $b, $c, $dst", 374 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 375def SUBri : F3_2<2, 0b000100, 376 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 377 "sub $b, $c, $dst", 378 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 379def SUBCCrr : F3_1<2, 0b010100, 380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 381 "subcc $b, $c, $dst", []>; 382def SUBCCri : F3_2<2, 0b010100, 383 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 384 "subcc $b, $c, $dst", []>; 385def SUBXrr : F3_1<2, 0b001100, 386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 387 "subx $b, $c, $dst", []>; 388def SUBXri : F3_2<2, 0b001100, 389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 390 "subx $b, $c, $dst", []>; 391def SUBXCCrr: F3_1<2, 0b011100, 392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 393 "subxcc $b, $c, $dst", []>; 394def SUBXCCri: F3_2<2, 0b011100, 395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 396 "subxcc $b, $c, $dst", []>; 397 398// Section B.18 - Multiply Instructions, p. 113 399def UMULrr : F3_1<2, 0b001010, 400 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 401 "umul $b, $c, $dst", []>; 402def UMULri : F3_2<2, 0b001010, 403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 404 "umul $b, $c, $dst", []>; 405def SMULrr : F3_1<2, 0b001011, 406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 407 "smul $b, $c, $dst", []>; 408def SMULri : F3_2<2, 0b001011, 409 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 410 "smul $b, $c, $dst", []>; 411def UMULCCrr: F3_1<2, 0b011010, 412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 413 "umulcc $b, $c, $dst", []>; 414def UMULCCri: F3_2<2, 0b011010, 415 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 416 "umulcc $b, $c, $dst", []>; 417def SMULCCrr: F3_1<2, 0b011011, 418 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 419 "smulcc $b, $c, $dst", []>; 420def SMULCCri: F3_2<2, 0b011011, 421 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 422 "smulcc $b, $c, $dst", []>; 423 424// Section B.19 - Divide Instructions, p. 115 425def UDIVrr : F3_1<2, 0b001110, 426 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 427 "udiv $b, $c, $dst", []>; 428def UDIVri : F3_2<2, 0b001110, 429 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 430 "udiv $b, $c, $dst", []>; 431def SDIVrr : F3_1<2, 0b001111, 432 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 433 "sdiv $b, $c, $dst", []>; 434def SDIVri : F3_2<2, 0b001111, 435 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 436 "sdiv $b, $c, $dst", []>; 437def UDIVCCrr : F3_1<2, 0b011110, 438 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 439 "udivcc $b, $c, $dst", []>; 440def UDIVCCri : F3_2<2, 0b011110, 441 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 442 "udivcc $b, $c, $dst", []>; 443def SDIVCCrr : F3_1<2, 0b011111, 444 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 445 "sdivcc $b, $c, $dst", []>; 446def SDIVCCri : F3_2<2, 0b011111, 447 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 448 "sdivcc $b, $c, $dst", []>; 449 450// Section B.20 - SAVE and RESTORE, p. 117 451def SAVErr : F3_1<2, 0b111100, 452 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 453 "save $b, $c, $dst", []>; 454def SAVEri : F3_2<2, 0b111100, 455 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 456 "save $b, $c, $dst", []>; 457def RESTORErr : F3_1<2, 0b111101, 458 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 459 "restore $b, $c, $dst", []>; 460def RESTOREri : F3_2<2, 0b111101, 461 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 462 "restore $b, $c, $dst", []>; 463 464// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 465 466// conditional branch class: 467class BranchV8<bits<4> cc, dag ops, string asmstr> 468 : F2_2<cc, 0b010, ops, asmstr> { 469 let isBranch = 1; 470 let isTerminator = 1; 471 let hasDelaySlot = 1; 472} 473 474let isBarrier = 1 in 475 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">; 476def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">; 477def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">; 478def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">; 479def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">; 480def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">; 481def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">; 482def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">; 483def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">; 484def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">; 485def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">; 486def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">; 487 488// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 489 490// floating-point conditional branch class: 491class FPBranchV8<bits<4> cc, dag ops, string asmstr> 492 : F2_2<cc, 0b110, ops, asmstr> { 493 let isBranch = 1; 494 let isTerminator = 1; 495 let hasDelaySlot = 1; 496} 497 498def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">; 499def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">; 500def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">; 501def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">; 502def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">; 503def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">; 504def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">; 505def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">; 506def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">; 507def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">; 508def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">; 509def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">; 510def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">; 511def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">; 512def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">; 513def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">; 514 515 516 517// Section B.24 - Call and Link Instruction, p. 125 518// This is the only Format 1 instruction 519let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 520 // pc-relative call: 521 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 522 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 523 def CALL : InstV8 { 524 let OperandList = (ops IntRegs:$dst); 525 bits<30> disp; 526 let op = 1; 527 let Inst{29-0} = disp; 528 let AsmString = "call $dst"; 529 } 530 531 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 532 // be an implicit def): 533 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 534 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 535 def JMPLrr : F3_1<2, 0b111000, 536 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 537 "jmpl $b+$c, $dst", []>; 538} 539 540// Section B.29 - Write State Register Instructions 541def WRrr : F3_1<2, 0b110000, 542 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 543 "wr $b, $c, $dst", []>; 544def WRri : F3_2<2, 0b110000, 545 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 546 "wr $b, $c, $dst", []>; 547 548// Convert Integer to Floating-point Instructions, p. 141 549def FITOS : F3_3<2, 0b110100, 0b011000100, 550 (ops FPRegs:$dst, FPRegs:$src), 551 "fitos $src, $dst">; 552def FITOD : F3_3<2, 0b110100, 0b011001000, 553 (ops DFPRegs:$dst, DFPRegs:$src), 554 "fitod $src, $dst">; 555 556// Convert Floating-point to Integer Instructions, p. 142 557def FSTOI : F3_3<2, 0b110100, 0b011010001, 558 (ops FPRegs:$dst, FPRegs:$src), 559 "fstoi $src, $dst">; 560def FDTOI : F3_3<2, 0b110100, 0b011010010, 561 (ops DFPRegs:$dst, DFPRegs:$src), 562 "fdtoi $src, $dst">; 563 564// Convert between Floating-point Formats Instructions, p. 143 565def FSTOD : F3_3<2, 0b110100, 0b011001001, 566 (ops DFPRegs:$dst, FPRegs:$src), 567 "fstod $src, $dst">; 568def FDTOS : F3_3<2, 0b110100, 0b011000110, 569 (ops FPRegs:$dst, DFPRegs:$src), 570 "fdtos $src, $dst">; 571 572// Floating-point Move Instructions, p. 144 573def FMOVS : F3_3<2, 0b110100, 0b000000001, 574 (ops FPRegs:$dst, FPRegs:$src), 575 "fmovs $src, $dst">; 576def FNEGS : F3_3<2, 0b110100, 0b000000101, 577 (ops FPRegs:$dst, FPRegs:$src), 578 "fnegs $src, $dst">; 579def FABSS : F3_3<2, 0b110100, 0b000001001, 580 (ops FPRegs:$dst, FPRegs:$src), 581 "fabss $src, $dst">; 582 583// Floating-point Add and Subtract Instructions, p. 146 584def FADDS : F3_3<2, 0b110100, 0b001000001, 585 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 586 "fadds $src1, $src2, $dst">; 587def FADDD : F3_3<2, 0b110100, 0b001000010, 588 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 589 "faddd $src1, $src2, $dst">; 590def FSUBS : F3_3<2, 0b110100, 0b001000101, 591 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 592 "fsubs $src1, $src2, $dst">; 593def FSUBD : F3_3<2, 0b110100, 0b001000110, 594 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 595 "fsubd $src1, $src2, $dst">; 596 597// Floating-point Multiply and Divide Instructions, p. 147 598def FMULS : F3_3<2, 0b110100, 0b001001001, 599 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 600 "fmuls $src1, $src2, $dst">; 601def FMULD : F3_3<2, 0b110100, 0b001001010, 602 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 603 "fmuld $src1, $src2, $dst">; 604def FSMULD : F3_3<2, 0b110100, 0b001101001, 605 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 606 "fsmuld $src1, $src2, $dst">; 607def FDIVS : F3_3<2, 0b110100, 0b001001101, 608 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 609 "fdivs $src1, $src2, $dst">; 610def FDIVD : F3_3<2, 0b110100, 0b001001110, 611 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 612 "fdivd $src1, $src2, $dst">; 613 614// Floating-point Compare Instructions, p. 148 615// Note: the 2nd template arg is different for these guys. 616// Note 2: the result of a FCMP is not available until the 2nd cycle 617// after the instr is retired, but there is no interlock. This behavior 618// is modelled with a forced noop after the instruction. 619def FCMPS : F3_3<2, 0b110101, 0b001010001, 620 (ops FPRegs:$src1, FPRegs:$src2), 621 "fcmps $src1, $src2\n\tnop">; 622def FCMPD : F3_3<2, 0b110101, 0b001010010, 623 (ops DFPRegs:$src1, DFPRegs:$src2), 624 "fcmpd $src1, $src2\n\tnop">; 625def FCMPES : F3_3<2, 0b110101, 0b001010101, 626 (ops FPRegs:$src1, FPRegs:$src2), 627 "fcmpes $src1, $src2\n\tnop">; 628def FCMPED : F3_3<2, 0b110101, 0b001010110, 629 (ops DFPRegs:$src1, DFPRegs:$src2), 630 "fcmped $src1, $src2\n\tnop">; 631 632//===----------------------------------------------------------------------===// 633// Non-Instruction Patterns 634//===----------------------------------------------------------------------===// 635 636// Small immediates. 637def : Pat<(i32 simm13:$val), 638 (ORri G0, imm:$val)>; 639// Arbitrary immediates. 640def : Pat<(i32 imm:$val), 641 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 642