SparcInstrInfo.td revision 6dc83c777db605209aaa707bb23bd49dc8770228
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcV8InstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm13 : PatLeaf<(imm), [{ 47 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 48 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 49}]>; 50 51def LO10 : SDNodeXForm<imm, [{ 52 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 53}]>; 54 55def HI22 : SDNodeXForm<imm, [{ 56 // Transformation function: shift the immediate value down into the low bits. 57 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 58}]>; 59 60def SETHIimm : PatLeaf<(imm), [{ 61 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 62}], HI22>; 63 64// Addressing modes. 65def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 66def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 67 68// Address operands 69def MEMrr : Operand<i32> { 70 let PrintMethod = "printMemOperand"; 71 let NumMIOperands = 2; 72 let MIOperandInfo = (ops IntRegs, IntRegs); 73} 74def MEMri : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let NumMIOperands = 2; 77 let MIOperandInfo = (ops IntRegs, i32imm); 78} 79 80// Branch targets have OtherVT type. 81def brtarget : Operand<OtherVT>; 82def calltarget : Operand<i32>; 83 84def SDTV8cmpfcc : 85SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 86def SDTV8brcc : 87SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, 88 SDTCisVT<2, FlagVT>]>; 89def SDTV8selectcc : 90SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 91 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>; 92def SDTV8FTOI : 93SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 94def SDTV8ITOF : 95SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 96 97def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 98def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>; 99def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 100def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 101 102def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 103def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 104 105def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>; 106def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>; 107 108def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>; 109def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>; 110 111// These are target-independent nodes, but have target-specific formats. 112def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 113def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>; 114def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>; 115 116def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 117def call : SDNode<"V8ISD::CALL", SDT_V8Call, 118 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 119 120def SDT_V8RetFlag : SDTypeProfile<0, 0, []>; 121def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, 122 [SDNPHasChain, SDNPOptInFlag]>; 123 124//===----------------------------------------------------------------------===// 125// SPARC Flag Conditions 126//===----------------------------------------------------------------------===// 127 128// Note that these values must be kept in sync with the V8CC::CondCode enum 129// values. 130def ICC_NE : PatLeaf<(i32 9)>; // Not Equal 131def ICC_E : PatLeaf<(i32 1)>; // Equal 132def ICC_G : PatLeaf<(i32 10)>; // Greater 133def ICC_LE : PatLeaf<(i32 2)>; // Less or Equal 134def ICC_GE : PatLeaf<(i32 11)>; // Greater or Equal 135def ICC_L : PatLeaf<(i32 3)>; // Less 136def ICC_GU : PatLeaf<(i32 12)>; // Greater Unsigned 137def ICC_LEU : PatLeaf<(i32 4)>; // Less or Equal Unsigned 138def ICC_CC : PatLeaf<(i32 13)>; // Carry Clear/Great or Equal Unsigned 139def ICC_CS : PatLeaf<(i32 5)>; // Carry Set/Less Unsigned 140def ICC_POS : PatLeaf<(i32 14)>; // Positive 141def ICC_NEG : PatLeaf<(i32 6)>; // Negative 142def ICC_VC : PatLeaf<(i32 15)>; // Overflow Clear 143def ICC_VS : PatLeaf<(i32 7)>; // Overflow Set 144 145def FCC_U : PatLeaf<(i32 23)>; // Unordered 146def FCC_G : PatLeaf<(i32 22)>; // Greater 147def FCC_UG : PatLeaf<(i32 21)>; // Unordered or Greater 148def FCC_L : PatLeaf<(i32 20)>; // Less 149def FCC_UL : PatLeaf<(i32 19)>; // Unordered or Less 150def FCC_LG : PatLeaf<(i32 18)>; // Less or Greater 151def FCC_NE : PatLeaf<(i32 17)>; // Not Equal 152def FCC_E : PatLeaf<(i32 25)>; // Equal 153def FCC_UE : PatLeaf<(i32 24)>; // Unordered or Equal 154def FCC_GE : PatLeaf<(i32 25)>; // Greater or Equal 155def FCC_UGE : PatLeaf<(i32 26)>; // Unordered or Greater or Equal 156def FCC_LE : PatLeaf<(i32 27)>; // Less or Equal 157def FCC_ULE : PatLeaf<(i32 28)>; // Unordered or Less or Equal 158def FCC_O : PatLeaf<(i32 29)>; // Ordered 159 160 161//===----------------------------------------------------------------------===// 162// Instructions 163//===----------------------------------------------------------------------===// 164 165// Pseudo instructions. 166class Pseudo<dag ops, string asmstr, list<dag> pattern> 167 : InstV8<ops, asmstr, pattern>; 168 169def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 170 "!ADJCALLSTACKDOWN $amt", 171 [(callseq_start imm:$amt)]>; 172def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 173 "!ADJCALLSTACKUP $amt", 174 [(callseq_end imm:$amt)]>; 175def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 176 "!IMPLICIT_DEF $dst", 177 [(set IntRegs:$dst, (undef))]>; 178def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 179 [(set FPRegs:$dst, (undef))]>; 180def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 181 [(set DFPRegs:$dst, (undef))]>; 182 183// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 184// fpmover pass. 185let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 186 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 187 "!FpMOVD $src, $dst", []>; 188 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 189 "!FpNEGD $src, $dst", 190 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 191 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 192 "!FpABSD $src, $dst", 193 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 194} 195 196// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 197// scheduler into a branch sequence. This has to handle all permutations of 198// selection between i32/f32/f64 on ICC and FCC. 199let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 200 def SELECT_CC_Int_ICC 201 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 202 "; SELECT_CC_Int_ICC PSEUDO!", 203 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F, 204 imm:$Cond, ICC))]>; 205 def SELECT_CC_Int_FCC 206 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 207 "; SELECT_CC_Int_FCC PSEUDO!", 208 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F, 209 imm:$Cond, FCC))]>; 210 def SELECT_CC_FP_ICC 211 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 212 "; SELECT_CC_FP_ICC PSEUDO!", 213 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F, 214 imm:$Cond, ICC))]>; 215 def SELECT_CC_FP_FCC 216 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 217 "; SELECT_CC_FP_FCC PSEUDO!", 218 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F, 219 imm:$Cond, FCC))]>; 220 def SELECT_CC_DFP_ICC 221 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 222 "; SELECT_CC_DFP_ICC PSEUDO!", 223 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F, 224 imm:$Cond, ICC))]>; 225 def SELECT_CC_DFP_FCC 226 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 227 "; SELECT_CC_DFP_FCC PSEUDO!", 228 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F, 229 imm:$Cond, FCC))]>; 230} 231 232 233// Section A.3 - Synthetic Instructions, p. 85 234// special cases of JMPL: 235let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 236 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 237 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 238} 239 240// Section B.1 - Load Integer Instructions, p. 90 241def LDSBrr : F3_1<3, 0b001001, 242 (ops IntRegs:$dst, MEMrr:$addr), 243 "ldsb [$addr], $dst", 244 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 245def LDSBri : F3_2<3, 0b001001, 246 (ops IntRegs:$dst, MEMri:$addr), 247 "ldsb [$addr], $dst", 248 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 249def LDSHrr : F3_1<3, 0b001010, 250 (ops IntRegs:$dst, MEMrr:$addr), 251 "ldsh [$addr], $dst", 252 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 253def LDSHri : F3_2<3, 0b001010, 254 (ops IntRegs:$dst, MEMri:$addr), 255 "ldsh [$addr], $dst", 256 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 257def LDUBrr : F3_1<3, 0b000001, 258 (ops IntRegs:$dst, MEMrr:$addr), 259 "ldub [$addr], $dst", 260 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 261def LDUBri : F3_2<3, 0b000001, 262 (ops IntRegs:$dst, MEMri:$addr), 263 "ldub [$addr], $dst", 264 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 265def LDUHrr : F3_1<3, 0b000010, 266 (ops IntRegs:$dst, MEMrr:$addr), 267 "lduh [$addr], $dst", 268 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 269def LDUHri : F3_2<3, 0b000010, 270 (ops IntRegs:$dst, MEMri:$addr), 271 "lduh [$addr], $dst", 272 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 273def LDrr : F3_1<3, 0b000000, 274 (ops IntRegs:$dst, MEMrr:$addr), 275 "ld [$addr], $dst", 276 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 277def LDri : F3_2<3, 0b000000, 278 (ops IntRegs:$dst, MEMri:$addr), 279 "ld [$addr], $dst", 280 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 281 282// Section B.2 - Load Floating-point Instructions, p. 92 283def LDFrr : F3_1<3, 0b100000, 284 (ops FPRegs:$dst, MEMrr:$addr), 285 "ld [$addr], $dst", 286 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 287def LDFri : F3_2<3, 0b100000, 288 (ops FPRegs:$dst, MEMri:$addr), 289 "ld [$addr], $dst", 290 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 291def LDDFrr : F3_1<3, 0b100011, 292 (ops DFPRegs:$dst, MEMrr:$addr), 293 "ldd [$addr], $dst", 294 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 295def LDDFri : F3_2<3, 0b100011, 296 (ops DFPRegs:$dst, MEMri:$addr), 297 "ldd [$addr], $dst", 298 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 299 300// Section B.4 - Store Integer Instructions, p. 95 301def STBrr : F3_1<3, 0b000101, 302 (ops MEMrr:$addr, IntRegs:$src), 303 "stb $src, [$addr]", 304 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 305def STBri : F3_2<3, 0b000101, 306 (ops MEMri:$addr, IntRegs:$src), 307 "stb $src, [$addr]", 308 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 309def STHrr : F3_1<3, 0b000110, 310 (ops MEMrr:$addr, IntRegs:$src), 311 "sth $src, [$addr]", 312 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 313def STHri : F3_2<3, 0b000110, 314 (ops MEMri:$addr, IntRegs:$src), 315 "sth $src, [$addr]", 316 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 317def STrr : F3_1<3, 0b000100, 318 (ops MEMrr:$addr, IntRegs:$src), 319 "st $src, [$addr]", 320 [(store IntRegs:$src, ADDRrr:$addr)]>; 321def STri : F3_2<3, 0b000100, 322 (ops MEMri:$addr, IntRegs:$src), 323 "st $src, [$addr]", 324 [(store IntRegs:$src, ADDRri:$addr)]>; 325 326// Section B.5 - Store Floating-point Instructions, p. 97 327def STFrr : F3_1<3, 0b100100, 328 (ops MEMrr:$addr, FPRegs:$src), 329 "st $src, [$addr]", 330 [(store FPRegs:$src, ADDRrr:$addr)]>; 331def STFri : F3_2<3, 0b100100, 332 (ops MEMri:$addr, FPRegs:$src), 333 "st $src, [$addr]", 334 [(store FPRegs:$src, ADDRri:$addr)]>; 335def STDFrr : F3_1<3, 0b100111, 336 (ops MEMrr:$addr, DFPRegs:$src), 337 "std $src, [$addr]", 338 [(store DFPRegs:$src, ADDRrr:$addr)]>; 339def STDFri : F3_2<3, 0b100111, 340 (ops MEMri:$addr, DFPRegs:$src), 341 "std $src, [$addr]", 342 [(store DFPRegs:$src, ADDRri:$addr)]>; 343 344// Section B.9 - SETHI Instruction, p. 104 345def SETHIi: F2_1<0b100, 346 (ops IntRegs:$dst, i32imm:$src), 347 "sethi $src, $dst", 348 [(set IntRegs:$dst, SETHIimm:$src)]>; 349 350// Section B.10 - NOP Instruction, p. 105 351// (It's a special case of SETHI) 352let rd = 0, imm22 = 0 in 353 def NOP : F2_1<0b100, (ops), "nop", []>; 354 355// Section B.11 - Logical Instructions, p. 106 356def ANDrr : F3_1<2, 0b000001, 357 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 358 "and $b, $c, $dst", 359 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 360def ANDri : F3_2<2, 0b000001, 361 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 362 "and $b, $c, $dst", 363 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 364def ANDNrr : F3_1<2, 0b000101, 365 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 366 "andn $b, $c, $dst", 367 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 368def ANDNri : F3_2<2, 0b000101, 369 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 370 "andn $b, $c, $dst", []>; 371def ORrr : F3_1<2, 0b000010, 372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 373 "or $b, $c, $dst", 374 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 375def ORri : F3_2<2, 0b000010, 376 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 377 "or $b, $c, $dst", 378 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 379def ORNrr : F3_1<2, 0b000110, 380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 381 "orn $b, $c, $dst", 382 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 383def ORNri : F3_2<2, 0b000110, 384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 385 "orn $b, $c, $dst", []>; 386def XORrr : F3_1<2, 0b000011, 387 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 388 "xor $b, $c, $dst", 389 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 390def XORri : F3_2<2, 0b000011, 391 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 392 "xor $b, $c, $dst", 393 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 394def XNORrr : F3_1<2, 0b000111, 395 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 396 "xnor $b, $c, $dst", 397 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 398def XNORri : F3_2<2, 0b000111, 399 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 400 "xnor $b, $c, $dst", []>; 401 402// Section B.12 - Shift Instructions, p. 107 403def SLLrr : F3_1<2, 0b100101, 404 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 405 "sll $b, $c, $dst", 406 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 407def SLLri : F3_2<2, 0b100101, 408 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 409 "sll $b, $c, $dst", 410 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 411def SRLrr : F3_1<2, 0b100110, 412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 413 "srl $b, $c, $dst", 414 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 415def SRLri : F3_2<2, 0b100110, 416 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 417 "srl $b, $c, $dst", 418 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 419def SRArr : F3_1<2, 0b100111, 420 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 421 "sra $b, $c, $dst", 422 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 423def SRAri : F3_2<2, 0b100111, 424 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 425 "sra $b, $c, $dst", 426 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 427 428// Section B.13 - Add Instructions, p. 108 429def ADDrr : F3_1<2, 0b000000, 430 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 431 "add $b, $c, $dst", 432 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 433def ADDri : F3_2<2, 0b000000, 434 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 435 "add $b, $c, $dst", 436 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 437def ADDCCrr : F3_1<2, 0b010000, 438 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 439 "addcc $b, $c, $dst", []>; 440def ADDCCri : F3_2<2, 0b010000, 441 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 442 "addcc $b, $c, $dst", []>; 443def ADDXrr : F3_1<2, 0b001000, 444 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 445 "addx $b, $c, $dst", []>; 446def ADDXri : F3_2<2, 0b001000, 447 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 448 "addx $b, $c, $dst", []>; 449 450// Section B.15 - Subtract Instructions, p. 110 451def SUBrr : F3_1<2, 0b000100, 452 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 453 "sub $b, $c, $dst", 454 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 455def SUBri : F3_2<2, 0b000100, 456 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 457 "sub $b, $c, $dst", 458 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 459def SUBXrr : F3_1<2, 0b001100, 460 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 461 "subx $b, $c, $dst", []>; 462def SUBXri : F3_2<2, 0b001100, 463 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 464 "subx $b, $c, $dst", []>; 465def SUBCCrr : F3_1<2, 0b010100, 466 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 467 "subcc $b, $c, $dst", 468 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>; 469def SUBCCri : F3_2<2, 0b010100, 470 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 471 "subcc $b, $c, $dst", 472 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>; 473def SUBXCCrr: F3_1<2, 0b011100, 474 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 475 "subxcc $b, $c, $dst", []>; 476 477// Section B.18 - Multiply Instructions, p. 113 478def UMULrr : F3_1<2, 0b001010, 479 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 480 "umul $b, $c, $dst", []>; 481def UMULri : F3_2<2, 0b001010, 482 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 483 "umul $b, $c, $dst", []>; 484def SMULrr : F3_1<2, 0b001011, 485 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 486 "smul $b, $c, $dst", 487 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 488def SMULri : F3_2<2, 0b001011, 489 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 490 "smul $b, $c, $dst", 491 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 492 493// Section B.19 - Divide Instructions, p. 115 494def UDIVrr : F3_1<2, 0b001110, 495 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 496 "udiv $b, $c, $dst", []>; 497def UDIVri : F3_2<2, 0b001110, 498 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 499 "udiv $b, $c, $dst", []>; 500def SDIVrr : F3_1<2, 0b001111, 501 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 502 "sdiv $b, $c, $dst", []>; 503def SDIVri : F3_2<2, 0b001111, 504 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 505 "sdiv $b, $c, $dst", []>; 506 507// Section B.20 - SAVE and RESTORE, p. 117 508def SAVErr : F3_1<2, 0b111100, 509 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 510 "save $b, $c, $dst", []>; 511def SAVEri : F3_2<2, 0b111100, 512 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 513 "save $b, $c, $dst", []>; 514def RESTORErr : F3_1<2, 0b111101, 515 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 516 "restore $b, $c, $dst", []>; 517def RESTOREri : F3_2<2, 0b111101, 518 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 519 "restore $b, $c, $dst", []>; 520 521// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 522 523// conditional branch class: 524class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 525 : F2_2<cc, 0b010, ops, asmstr, pattern> { 526 let isBranch = 1; 527 let isTerminator = 1; 528 let hasDelaySlot = 1; 529 let noResults = 1; 530} 531 532let isBarrier = 1 in 533 def BA : BranchV8<0b1000, (ops brtarget:$dst), 534 "ba $dst", 535 [(br bb:$dst)]>; 536def BNE : BranchV8<0b1001, (ops brtarget:$dst), 537 "bne $dst", 538 [(V8bricc bb:$dst, ICC_NE, ICC)]>; 539def BE : BranchV8<0b0001, (ops brtarget:$dst), 540 "be $dst", 541 [(V8bricc bb:$dst, ICC_E, ICC)]>; 542def BG : BranchV8<0b1010, (ops brtarget:$dst), 543 "bg $dst", 544 [(V8bricc bb:$dst, ICC_G, ICC)]>; 545def BLE : BranchV8<0b0010, (ops brtarget:$dst), 546 "ble $dst", 547 [(V8bricc bb:$dst, ICC_LE, ICC)]>; 548def BGE : BranchV8<0b1011, (ops brtarget:$dst), 549 "bge $dst", 550 [(V8bricc bb:$dst, ICC_GE, ICC)]>; 551def BL : BranchV8<0b0011, (ops brtarget:$dst), 552 "bl $dst", 553 [(V8bricc bb:$dst, ICC_L, ICC)]>; 554def BGU : BranchV8<0b1100, (ops brtarget:$dst), 555 "bgu $dst", 556 [(V8bricc bb:$dst, ICC_GU, ICC)]>; 557def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 558 "bleu $dst", 559 [(V8bricc bb:$dst, ICC_LEU, ICC)]>; 560def BCC : BranchV8<0b1101, (ops brtarget:$dst), 561 "bcc $dst", 562 [(V8bricc bb:$dst, ICC_CC, ICC)]>; 563def BCS : BranchV8<0b0101, (ops brtarget:$dst), 564 "bcs $dst", 565 [(V8bricc bb:$dst, ICC_CS, ICC)]>; 566def BPOS : BranchV8<0b1110, (ops brtarget:$dst), 567 "bpos $dst", 568 [(V8bricc bb:$dst, ICC_POS, ICC)]>; 569def BNEG : BranchV8<0b0110, (ops brtarget:$dst), 570 "bneg $dst", 571 [(V8bricc bb:$dst, ICC_NEG, ICC)]>; 572def BVC : BranchV8<0b1111, (ops brtarget:$dst), 573 "bvc $dst", 574 [(V8bricc bb:$dst, ICC_VC, ICC)]>; 575def BVS : BranchV8<0b0111, (ops brtarget:$dst), 576 "bvs $dst", 577 [(V8bricc bb:$dst, ICC_VS, ICC)]>; 578 579 580 581// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 582 583// floating-point conditional branch class: 584class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 585 : F2_2<cc, 0b110, ops, asmstr, pattern> { 586 let isBranch = 1; 587 let isTerminator = 1; 588 let hasDelaySlot = 1; 589 let noResults = 1; 590} 591 592def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 593 "fbu $dst", 594 [(V8brfcc bb:$dst, FCC_U, FCC)]>; 595def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 596 "fbg $dst", 597 [(V8brfcc bb:$dst, FCC_G, FCC)]>; 598def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 599 "fbug $dst", 600 [(V8brfcc bb:$dst, FCC_UG, FCC)]>; 601def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 602 "fbl $dst", 603 [(V8brfcc bb:$dst, FCC_L, FCC)]>; 604def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 605 "fbul $dst", 606 [(V8brfcc bb:$dst, FCC_UL, FCC)]>; 607def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 608 "fblg $dst", 609 [(V8brfcc bb:$dst, FCC_LG, FCC)]>; 610def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 611 "fbne $dst", 612 [(V8brfcc bb:$dst, FCC_NE, FCC)]>; 613def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 614 "fbe $dst", 615 [(V8brfcc bb:$dst, FCC_E, FCC)]>; 616def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 617 "fbue $dst", 618 [(V8brfcc bb:$dst, FCC_UE, FCC)]>; 619def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 620 "fbge $dst", 621 [(V8brfcc bb:$dst, FCC_GE, FCC)]>; 622def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 623 "fbuge $dst", 624 [(V8brfcc bb:$dst, FCC_UGE, FCC)]>; 625def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 626 "fble $dst", 627 [(V8brfcc bb:$dst, FCC_LE, FCC)]>; 628def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 629 "fbule $dst", 630 [(V8brfcc bb:$dst, FCC_ULE, FCC)]>; 631def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 632 "fbo $dst", 633 [(V8brfcc bb:$dst, FCC_O, FCC)]>; 634 635 636 637// Section B.24 - Call and Link Instruction, p. 125 638// This is the only Format 1 instruction 639let Uses = [O0, O1, O2, O3, O4, O5], 640 hasDelaySlot = 1, isCall = 1, noResults = 1, 641 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 642 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 643 def CALL : InstV8<(ops calltarget:$dst), 644 "call $dst", []> { 645 bits<30> disp; 646 let op = 1; 647 let Inst{29-0} = disp; 648 } 649 650 // indirect calls 651 def JMPLrr : F3_1<2, 0b111000, 652 (ops MEMrr:$ptr), 653 "call $ptr", 654 [(call ADDRrr:$ptr)]>; 655 def JMPLri : F3_2<2, 0b111000, 656 (ops MEMri:$ptr), 657 "call $ptr", 658 [(call ADDRri:$ptr)]>; 659} 660 661// Section B.28 - Read State Register Instructions 662def RDY : F3_1<2, 0b101000, 663 (ops IntRegs:$dst), 664 "rd %y, $dst", []>; 665 666// Section B.29 - Write State Register Instructions 667def WRYrr : F3_1<2, 0b110000, 668 (ops IntRegs:$b, IntRegs:$c), 669 "wr $b, $c, %y", []>; 670def WRYri : F3_2<2, 0b110000, 671 (ops IntRegs:$b, i32imm:$c), 672 "wr $b, $c, %y", []>; 673 674// Convert Integer to Floating-point Instructions, p. 141 675def FITOS : F3_3<2, 0b110100, 0b011000100, 676 (ops FPRegs:$dst, FPRegs:$src), 677 "fitos $src, $dst", 678 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 679def FITOD : F3_3<2, 0b110100, 0b011001000, 680 (ops DFPRegs:$dst, FPRegs:$src), 681 "fitod $src, $dst", 682 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>; 683 684// Convert Floating-point to Integer Instructions, p. 142 685def FSTOI : F3_3<2, 0b110100, 0b011010001, 686 (ops FPRegs:$dst, FPRegs:$src), 687 "fstoi $src, $dst", 688 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 689def FDTOI : F3_3<2, 0b110100, 0b011010010, 690 (ops FPRegs:$dst, DFPRegs:$src), 691 "fdtoi $src, $dst", 692 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 693 694// Convert between Floating-point Formats Instructions, p. 143 695def FSTOD : F3_3<2, 0b110100, 0b011001001, 696 (ops DFPRegs:$dst, FPRegs:$src), 697 "fstod $src, $dst", 698 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 699def FDTOS : F3_3<2, 0b110100, 0b011000110, 700 (ops FPRegs:$dst, DFPRegs:$src), 701 "fdtos $src, $dst", 702 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 703 704// Floating-point Move Instructions, p. 144 705def FMOVS : F3_3<2, 0b110100, 0b000000001, 706 (ops FPRegs:$dst, FPRegs:$src), 707 "fmovs $src, $dst", []>; 708def FNEGS : F3_3<2, 0b110100, 0b000000101, 709 (ops FPRegs:$dst, FPRegs:$src), 710 "fnegs $src, $dst", 711 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 712def FABSS : F3_3<2, 0b110100, 0b000001001, 713 (ops FPRegs:$dst, FPRegs:$src), 714 "fabss $src, $dst", 715 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 716 717 718// Floating-point Square Root Instructions, p.145 719def FSQRTS : F3_3<2, 0b110100, 0b000101001, 720 (ops FPRegs:$dst, FPRegs:$src), 721 "fsqrts $src, $dst", 722 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 723def FSQRTD : F3_3<2, 0b110100, 0b000101010, 724 (ops DFPRegs:$dst, DFPRegs:$src), 725 "fsqrtd $src, $dst", 726 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 727 728 729 730// Floating-point Add and Subtract Instructions, p. 146 731def FADDS : F3_3<2, 0b110100, 0b001000001, 732 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 733 "fadds $src1, $src2, $dst", 734 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 735def FADDD : F3_3<2, 0b110100, 0b001000010, 736 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 737 "faddd $src1, $src2, $dst", 738 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 739def FSUBS : F3_3<2, 0b110100, 0b001000101, 740 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 741 "fsubs $src1, $src2, $dst", 742 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 743def FSUBD : F3_3<2, 0b110100, 0b001000110, 744 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 745 "fsubd $src1, $src2, $dst", 746 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 747 748// Floating-point Multiply and Divide Instructions, p. 147 749def FMULS : F3_3<2, 0b110100, 0b001001001, 750 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 751 "fmuls $src1, $src2, $dst", 752 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 753def FMULD : F3_3<2, 0b110100, 0b001001010, 754 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 755 "fmuld $src1, $src2, $dst", 756 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 757def FSMULD : F3_3<2, 0b110100, 0b001101001, 758 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 759 "fsmuld $src1, $src2, $dst", 760 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 761 (fextend FPRegs:$src2)))]>; 762def FDIVS : F3_3<2, 0b110100, 0b001001101, 763 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 764 "fdivs $src1, $src2, $dst", 765 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 766def FDIVD : F3_3<2, 0b110100, 0b001001110, 767 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 768 "fdivd $src1, $src2, $dst", 769 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 770 771// Floating-point Compare Instructions, p. 148 772// Note: the 2nd template arg is different for these guys. 773// Note 2: the result of a FCMP is not available until the 2nd cycle 774// after the instr is retired, but there is no interlock. This behavior 775// is modelled with a forced noop after the instruction. 776def FCMPS : F3_3<2, 0b110101, 0b001010001, 777 (ops FPRegs:$src1, FPRegs:$src2), 778 "fcmps $src1, $src2\n\tnop", 779 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 780def FCMPD : F3_3<2, 0b110101, 0b001010010, 781 (ops DFPRegs:$src1, DFPRegs:$src2), 782 "fcmpd $src1, $src2\n\tnop", 783 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 784 785 786//===----------------------------------------------------------------------===// 787// V9 Instructions 788//===----------------------------------------------------------------------===// 789 790// V9 Conditional Moves. 791let Predicates = [HasV9], isTwoAddress = 1 in { 792 // FIXME: Add instruction encodings for the JIT some day. 793 // FIXME: Allow regalloc of the condition code some day. 794 795 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 796 def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 797 "movne %icc, $F, $dst", 798 [(set IntRegs:$dst, 799 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_NE, ICC))]>; 800 def MOVE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 801 "move %icc, $F, $dst", 802 [(set IntRegs:$dst, 803 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_E, ICC))]>; 804 def MOVG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 805 "movg %icc, $F, $dst", 806 [(set IntRegs:$dst, 807 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_G, ICC))]>; 808 def MOVLE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 809 "movle %icc, $F, $dst", 810 [(set IntRegs:$dst, 811 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_LE, ICC))]>; 812 def MOVGE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 813 "movge %icc, $F, $dst", 814 [(set IntRegs:$dst, 815 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_GE, ICC))]>; 816 def MOVL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 817 "movl %icc, $F, $dst", 818 [(set IntRegs:$dst, 819 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_L, ICC))]>; 820 def MOVGU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 821 "movgu %icc, $F, $dst", 822 [(set IntRegs:$dst, 823 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_GU, ICC))]>; 824 def MOVLEU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 825 "movleu %icc, $F, $dst", 826 [(set IntRegs:$dst, 827 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_LEU, ICC))]>; 828 def MOVCC : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 829 "movcc %icc, $F, $dst", 830 [(set IntRegs:$dst, 831 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_CC, ICC))]>; 832 def MOVCS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 833 "movcs %icc, $F, $dst", 834 [(set IntRegs:$dst, 835 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_CS, ICC))]>; 836 def MOVPOS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 837 "movpos %icc, $F, $dst", 838 [(set IntRegs:$dst, 839 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_POS, ICC))]>; 840 def MOVNEG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 841 "movneg %icc, $F, $dst", 842 [(set IntRegs:$dst, 843 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_NEG, ICC))]>; 844 def MOVVC : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 845 "movvc %icc, $F, $dst", 846 [(set IntRegs:$dst, 847 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_VC, ICC))]>; 848 def MOVVS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 849 "movvs %icc, $F, $dst", 850 [(set IntRegs:$dst, 851 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_CS, ICC))]>; 852 853 def MOVFU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 854 "movfu %fcc, $F, $dst", 855 [(set IntRegs:$dst, 856 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_U, FCC))]>; 857 def MOVFG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 858 "movfg %fcc, $F, $dst", 859 [(set IntRegs:$dst, 860 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_G, FCC))]>; 861 def MOVFUG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 862 "movfug %fcc, $F, $dst", 863 [(set IntRegs:$dst, 864 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UG, FCC))]>; 865 def MOVFL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 866 "movfl %fcc, $F, $dst", 867 [(set IntRegs:$dst, 868 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_L, FCC))]>; 869 def MOVFUL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 870 "movful %fcc, $F, $dst", 871 [(set IntRegs:$dst, 872 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UL, FCC))]>; 873 def MOVFLG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 874 "movflg %fcc, $F, $dst", 875 [(set IntRegs:$dst, 876 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_LG, FCC))]>; 877 def MOVFNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 878 "movfne %fcc, $F, $dst", 879 [(set IntRegs:$dst, 880 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_NE, FCC))]>; 881 def MOVFE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 882 "movfe %fcc, $F, $dst", 883 [(set IntRegs:$dst, 884 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_E, FCC))]>; 885 def MOVFUE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 886 "movfue %fcc, $F, $dst", 887 [(set IntRegs:$dst, 888 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UE, FCC))]>; 889 def MOVFGE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 890 "movfge %fcc, $F, $dst", 891 [(set IntRegs:$dst, 892 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_GE, FCC))]>; 893 def MOVFUGE: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 894 "movfuge %fcc, $F, $dst", 895 [(set IntRegs:$dst, 896 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UGE, FCC))]>; 897 def MOVFLE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 898 "movfle %fcc, $F, $dst", 899 [(set IntRegs:$dst, 900 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_LE, FCC))]>; 901 def MOVFULE: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 902 "movfule %fcc, $F, $dst", 903 [(set IntRegs:$dst, 904 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_ULE, FCC))]>; 905 def MOVFO : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 906 "movfo %fcc, $F, $dst", 907 [(set IntRegs:$dst, 908 (V8selectfcc IntRegs:$F, IntRegs:$T, FCC_O, FCC))]>; 909} 910 911// Floating-Point Move Instructions, p. 164 of the V9 manual. 912let Predicates = [HasV9] in { 913 def FMOVD : F3_3<2, 0b110100, 0b000000010, 914 (ops DFPRegs:$dst, DFPRegs:$src), 915 "fmovd $src, $dst", []>; 916 def FNEGD : F3_3<2, 0b110100, 0b000000110, 917 (ops DFPRegs:$dst, DFPRegs:$src), 918 "fnegd $src, $dst", 919 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 920 def FABSD : F3_3<2, 0b110100, 0b000001010, 921 (ops DFPRegs:$dst, DFPRegs:$src), 922 "fabsd $src, $dst", 923 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 924} 925 926// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 927// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 928def POPCrr : F3_1<2, 0b101110, 929 (ops IntRegs:$dst, IntRegs:$src), 930 "popc $src, $dst", []>, Requires<[HasV9]>; 931def : Pat<(ctpop IntRegs:$src), 932 (POPCrr (SLLri IntRegs:$src, 0))>; 933 934//===----------------------------------------------------------------------===// 935// Non-Instruction Patterns 936//===----------------------------------------------------------------------===// 937 938// Small immediates. 939def : Pat<(i32 simm13:$val), 940 (ORri G0, imm:$val)>; 941// Arbitrary immediates. 942def : Pat<(i32 imm:$val), 943 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 944 945// Global addresses, constant pool entries 946def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 947def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 948def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 949def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 950 951// Add reg, lo. This is used when taking the addr of a global/constpool entry. 952def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)), 953 (ADDri IntRegs:$r, tglobaladdr:$in)>; 954def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)), 955 (ADDri IntRegs:$r, tconstpool:$in)>; 956 957 958// Calls: 959def : Pat<(call tglobaladdr:$dst), 960 (CALL tglobaladdr:$dst)>; 961def : Pat<(call externalsym:$dst), 962 (CALL externalsym:$dst)>; 963 964def : Pat<(ret), (RETL)>; 965 966// Map integer extload's to zextloads. 967def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 968def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 969def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 970def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 971def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 972def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 973 974// zextload bool -> zextload byte 975def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 976def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 977 978// truncstore bool -> truncstore byte. 979def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 980 (STBrr ADDRrr:$addr, IntRegs:$src)>; 981def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 982 (STBri ADDRri:$addr, IntRegs:$src)>; 983