SparcInstrInfo.td revision 75ddb2bb34f96c2bda48d0e86331fb52b55b8d03
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// HasHardQuad - This is true when the target processor supports quad floating 43// point instructions. 44def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; 45 46// UseDeprecatedInsts - This predicate is true when the target processor is a 47// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 48// to use when appropriate. In either of these cases, the instruction selector 49// will pick deprecated instructions. 50def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 51 52//===----------------------------------------------------------------------===// 53// Instruction Pattern Stuff 54//===----------------------------------------------------------------------===// 55 56def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 57 58def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 59 60def LO10 : SDNodeXForm<imm, [{ 61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 62 MVT::i32); 63}]>; 64 65def HI22 : SDNodeXForm<imm, [{ 66 // Transformation function: shift the immediate value down into the low bits. 67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 68}]>; 69 70def SETHIimm : PatLeaf<(imm), [{ 71 return isShiftedUInt<22, 10>(N->getZExtValue()); 72}], HI22>; 73 74// Addressing modes. 75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 77 78// Address operands 79def MEMrr : Operand<iPTR> { 80 let PrintMethod = "printMemOperand"; 81 let MIOperandInfo = (ops ptr_rc, ptr_rc); 82} 83def MEMri : Operand<iPTR> { 84 let PrintMethod = "printMemOperand"; 85 let MIOperandInfo = (ops ptr_rc, i32imm); 86} 87 88// Branch targets have OtherVT type. 89def brtarget : Operand<OtherVT>; 90def calltarget : Operand<i32>; 91 92// Operand for printing out a condition code. 93let PrintMethod = "printCCOperand" in 94 def CCOp : Operand<i32>; 95 96def SDTSPcmpicc : 97SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 98def SDTSPcmpfcc : 99SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 100def SDTSPbrcc : 101SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 102def SDTSPselectcc : 103SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 104def SDTSPFTOI : 105SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 106def SDTSPITOF : 107SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 108 109def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 110def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 111def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 112def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 113def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 114 115def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 116def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 117 118def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 119def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 120 121def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 122def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 123def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 124 125// These are target-independent nodes, but have target-specific formats. 126def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 127def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 128 SDTCisVT<1, i32> ]>; 129 130def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 131 [SDNPHasChain, SDNPOutGlue]>; 132def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 134 135def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 136def call : SDNode<"SPISD::CALL", SDT_SPCall, 137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 138 SDNPVariadic]>; 139 140def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 141def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143 144def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 145 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 146 147def getPCX : Operand<i32> { 148 let PrintMethod = "printGetPCX"; 149} 150 151//===----------------------------------------------------------------------===// 152// SPARC Flag Conditions 153//===----------------------------------------------------------------------===// 154 155// Note that these values must be kept in sync with the CCOp::CondCode enum 156// values. 157class ICC_VAL<int N> : PatLeaf<(i32 N)>; 158def ICC_NE : ICC_VAL< 9>; // Not Equal 159def ICC_E : ICC_VAL< 1>; // Equal 160def ICC_G : ICC_VAL<10>; // Greater 161def ICC_LE : ICC_VAL< 2>; // Less or Equal 162def ICC_GE : ICC_VAL<11>; // Greater or Equal 163def ICC_L : ICC_VAL< 3>; // Less 164def ICC_GU : ICC_VAL<12>; // Greater Unsigned 165def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 166def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 167def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 168def ICC_POS : ICC_VAL<14>; // Positive 169def ICC_NEG : ICC_VAL< 6>; // Negative 170def ICC_VC : ICC_VAL<15>; // Overflow Clear 171def ICC_VS : ICC_VAL< 7>; // Overflow Set 172 173class FCC_VAL<int N> : PatLeaf<(i32 N)>; 174def FCC_U : FCC_VAL<23>; // Unordered 175def FCC_G : FCC_VAL<22>; // Greater 176def FCC_UG : FCC_VAL<21>; // Unordered or Greater 177def FCC_L : FCC_VAL<20>; // Less 178def FCC_UL : FCC_VAL<19>; // Unordered or Less 179def FCC_LG : FCC_VAL<18>; // Less or Greater 180def FCC_NE : FCC_VAL<17>; // Not Equal 181def FCC_E : FCC_VAL<25>; // Equal 182def FCC_UE : FCC_VAL<24>; // Unordered or Equal 183def FCC_GE : FCC_VAL<25>; // Greater or Equal 184def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 185def FCC_LE : FCC_VAL<27>; // Less or Equal 186def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 187def FCC_O : FCC_VAL<29>; // Ordered 188 189//===----------------------------------------------------------------------===// 190// Instruction Class Templates 191//===----------------------------------------------------------------------===// 192 193/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 194multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 195 def rr : F3_1<2, Op3Val, 196 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 197 !strconcat(OpcStr, " $b, $c, $dst"), 198 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 199 def ri : F3_2<2, Op3Val, 200 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 201 !strconcat(OpcStr, " $b, $c, $dst"), 202 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 203} 204 205/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 206/// pattern. 207multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 208 def rr : F3_1<2, Op3Val, 209 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 210 !strconcat(OpcStr, " $b, $c, $dst"), []>; 211 def ri : F3_2<2, Op3Val, 212 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 213 !strconcat(OpcStr, " $b, $c, $dst"), []>; 214} 215 216//===----------------------------------------------------------------------===// 217// Instructions 218//===----------------------------------------------------------------------===// 219 220// Pseudo instructions. 221class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 222 : InstSP<outs, ins, asmstr, pattern>; 223 224// GETPCX for PIC 225let Defs = [O7] in { 226 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 227} 228 229let Defs = [O6], Uses = [O6] in { 230def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 231 "!ADJCALLSTACKDOWN $amt", 232 [(callseq_start timm:$amt)]>; 233def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 234 "!ADJCALLSTACKUP $amt1", 235 [(callseq_end timm:$amt1, timm:$amt2)]>; 236} 237 238let hasSideEffects = 1, mayStore = 1 in { 239 let rd = 0, rs1 = 0, rs2 = 0 in 240 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 241 "flushw", 242 [(flushw)]>, Requires<[HasV9]>; 243 let rd = 0, rs1 = 1, simm13 = 3 in 244 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 245 "ta 3", 246 [(flushw)]>; 247} 248 249def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 250 "unimp $val", []>; 251 252// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 253// instruction selection into a branch sequence. This has to handle all 254// permutations of selection between i32/f32/f64 on ICC and FCC. 255// Expanded after instruction selection. 256let Uses = [ICC], usesCustomInserter = 1 in { 257 def SELECT_CC_Int_ICC 258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_Int_ICC PSEUDO!", 260 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 261 def SELECT_CC_FP_ICC 262 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 263 "; SELECT_CC_FP_ICC PSEUDO!", 264 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 265 266 def SELECT_CC_DFP_ICC 267 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 268 "; SELECT_CC_DFP_ICC PSEUDO!", 269 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 270 271 def SELECT_CC_QFP_ICC 272 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 273 "; SELECT_CC_QFP_ICC PSEUDO!", 274 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 275} 276 277let usesCustomInserter = 1, Uses = [FCC] in { 278 279 def SELECT_CC_Int_FCC 280 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 281 "; SELECT_CC_Int_FCC PSEUDO!", 282 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 283 284 def SELECT_CC_FP_FCC 285 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 286 "; SELECT_CC_FP_FCC PSEUDO!", 287 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 288 def SELECT_CC_DFP_FCC 289 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 290 "; SELECT_CC_DFP_FCC PSEUDO!", 291 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 292 def SELECT_CC_QFP_FCC 293 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 294 "; SELECT_CC_QFP_FCC PSEUDO!", 295 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 296} 297 298 299// Section A.3 - Synthetic Instructions, p. 85 300// special cases of JMPL: 301let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 302 let rd = 0, rs1 = 15 in 303 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 304 "jmp %o7+$val", [(retflag simm13:$val)]>; 305 306 let rd = 0, rs1 = 31 in 307 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 308 "jmp %i7+$val", []>; 309} 310 311// Section B.1 - Load Integer Instructions, p. 90 312def LDSBrr : F3_1<3, 0b001001, 313 (outs IntRegs:$dst), (ins MEMrr:$addr), 314 "ldsb [$addr], $dst", 315 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 316def LDSBri : F3_2<3, 0b001001, 317 (outs IntRegs:$dst), (ins MEMri:$addr), 318 "ldsb [$addr], $dst", 319 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 320def LDSHrr : F3_1<3, 0b001010, 321 (outs IntRegs:$dst), (ins MEMrr:$addr), 322 "ldsh [$addr], $dst", 323 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 324def LDSHri : F3_2<3, 0b001010, 325 (outs IntRegs:$dst), (ins MEMri:$addr), 326 "ldsh [$addr], $dst", 327 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 328def LDUBrr : F3_1<3, 0b000001, 329 (outs IntRegs:$dst), (ins MEMrr:$addr), 330 "ldub [$addr], $dst", 331 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 332def LDUBri : F3_2<3, 0b000001, 333 (outs IntRegs:$dst), (ins MEMri:$addr), 334 "ldub [$addr], $dst", 335 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 336def LDUHrr : F3_1<3, 0b000010, 337 (outs IntRegs:$dst), (ins MEMrr:$addr), 338 "lduh [$addr], $dst", 339 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 340def LDUHri : F3_2<3, 0b000010, 341 (outs IntRegs:$dst), (ins MEMri:$addr), 342 "lduh [$addr], $dst", 343 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 344def LDrr : F3_1<3, 0b000000, 345 (outs IntRegs:$dst), (ins MEMrr:$addr), 346 "ld [$addr], $dst", 347 [(set i32:$dst, (load ADDRrr:$addr))]>; 348def LDri : F3_2<3, 0b000000, 349 (outs IntRegs:$dst), (ins MEMri:$addr), 350 "ld [$addr], $dst", 351 [(set i32:$dst, (load ADDRri:$addr))]>; 352 353// Section B.2 - Load Floating-point Instructions, p. 92 354def LDFrr : F3_1<3, 0b100000, 355 (outs FPRegs:$dst), (ins MEMrr:$addr), 356 "ld [$addr], $dst", 357 [(set f32:$dst, (load ADDRrr:$addr))]>; 358def LDFri : F3_2<3, 0b100000, 359 (outs FPRegs:$dst), (ins MEMri:$addr), 360 "ld [$addr], $dst", 361 [(set f32:$dst, (load ADDRri:$addr))]>; 362def LDDFrr : F3_1<3, 0b100011, 363 (outs DFPRegs:$dst), (ins MEMrr:$addr), 364 "ldd [$addr], $dst", 365 [(set f64:$dst, (load ADDRrr:$addr))]>; 366def LDDFri : F3_2<3, 0b100011, 367 (outs DFPRegs:$dst), (ins MEMri:$addr), 368 "ldd [$addr], $dst", 369 [(set f64:$dst, (load ADDRri:$addr))]>; 370def LDQFrr : F3_1<3, 0b100010, 371 (outs QFPRegs:$dst), (ins MEMrr:$addr), 372 "ldq [$addr], $dst", 373 [(set f128:$dst, (load ADDRrr:$addr))]>, 374 Requires<[HasV9, HasHardQuad]>; 375def LDQFri : F3_2<3, 0b100010, 376 (outs QFPRegs:$dst), (ins MEMri:$addr), 377 "ldq [$addr], $dst", 378 [(set f128:$dst, (load ADDRri:$addr))]>, 379 Requires<[HasV9, HasHardQuad]>; 380 381// Section B.4 - Store Integer Instructions, p. 95 382def STBrr : F3_1<3, 0b000101, 383 (outs), (ins MEMrr:$addr, IntRegs:$src), 384 "stb $src, [$addr]", 385 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 386def STBri : F3_2<3, 0b000101, 387 (outs), (ins MEMri:$addr, IntRegs:$src), 388 "stb $src, [$addr]", 389 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 390def STHrr : F3_1<3, 0b000110, 391 (outs), (ins MEMrr:$addr, IntRegs:$src), 392 "sth $src, [$addr]", 393 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 394def STHri : F3_2<3, 0b000110, 395 (outs), (ins MEMri:$addr, IntRegs:$src), 396 "sth $src, [$addr]", 397 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 398def STrr : F3_1<3, 0b000100, 399 (outs), (ins MEMrr:$addr, IntRegs:$src), 400 "st $src, [$addr]", 401 [(store i32:$src, ADDRrr:$addr)]>; 402def STri : F3_2<3, 0b000100, 403 (outs), (ins MEMri:$addr, IntRegs:$src), 404 "st $src, [$addr]", 405 [(store i32:$src, ADDRri:$addr)]>; 406 407// Section B.5 - Store Floating-point Instructions, p. 97 408def STFrr : F3_1<3, 0b100100, 409 (outs), (ins MEMrr:$addr, FPRegs:$src), 410 "st $src, [$addr]", 411 [(store f32:$src, ADDRrr:$addr)]>; 412def STFri : F3_2<3, 0b100100, 413 (outs), (ins MEMri:$addr, FPRegs:$src), 414 "st $src, [$addr]", 415 [(store f32:$src, ADDRri:$addr)]>; 416def STDFrr : F3_1<3, 0b100111, 417 (outs), (ins MEMrr:$addr, DFPRegs:$src), 418 "std $src, [$addr]", 419 [(store f64:$src, ADDRrr:$addr)]>; 420def STDFri : F3_2<3, 0b100111, 421 (outs), (ins MEMri:$addr, DFPRegs:$src), 422 "std $src, [$addr]", 423 [(store f64:$src, ADDRri:$addr)]>; 424def STQFrr : F3_1<3, 0b100110, 425 (outs), (ins MEMrr:$addr, QFPRegs:$src), 426 "stq $src, [$addr]", 427 [(store f128:$src, ADDRrr:$addr)]>, 428 Requires<[HasV9, HasHardQuad]>; 429def STQFri : F3_2<3, 0b100110, 430 (outs), (ins MEMri:$addr, QFPRegs:$src), 431 "stq $src, [$addr]", 432 [(store f128:$src, ADDRri:$addr)]>, 433 Requires<[HasV9, HasHardQuad]>; 434 435// Section B.9 - SETHI Instruction, p. 104 436def SETHIi: F2_1<0b100, 437 (outs IntRegs:$dst), (ins i32imm:$src), 438 "sethi $src, $dst", 439 [(set i32:$dst, SETHIimm:$src)]>; 440 441// Section B.10 - NOP Instruction, p. 105 442// (It's a special case of SETHI) 443let rd = 0, imm22 = 0 in 444 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 445 446// Section B.11 - Logical Instructions, p. 106 447defm AND : F3_12<"and", 0b000001, and>; 448 449def ANDNrr : F3_1<2, 0b000101, 450 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 451 "andn $b, $c, $dst", 452 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 453def ANDNri : F3_2<2, 0b000101, 454 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 455 "andn $b, $c, $dst", []>; 456 457defm OR : F3_12<"or", 0b000010, or>; 458 459def ORNrr : F3_1<2, 0b000110, 460 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 461 "orn $b, $c, $dst", 462 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 463def ORNri : F3_2<2, 0b000110, 464 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 465 "orn $b, $c, $dst", []>; 466defm XOR : F3_12<"xor", 0b000011, xor>; 467 468def XNORrr : F3_1<2, 0b000111, 469 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 470 "xnor $b, $c, $dst", 471 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 472def XNORri : F3_2<2, 0b000111, 473 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 474 "xnor $b, $c, $dst", []>; 475 476// Section B.12 - Shift Instructions, p. 107 477defm SLL : F3_12<"sll", 0b100101, shl>; 478defm SRL : F3_12<"srl", 0b100110, srl>; 479defm SRA : F3_12<"sra", 0b100111, sra>; 480 481// Section B.13 - Add Instructions, p. 108 482defm ADD : F3_12<"add", 0b000000, add>; 483 484// "LEA" forms of add (patterns to make tblgen happy) 485def LEA_ADDri : F3_2<2, 0b000000, 486 (outs IntRegs:$dst), (ins MEMri:$addr), 487 "add ${addr:arith}, $dst", 488 [(set iPTR:$dst, ADDRri:$addr)]>; 489 490let Defs = [ICC] in 491 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 492 493let Uses = [ICC] in 494 defm ADDX : F3_12<"addx", 0b001000, adde>; 495 496// Section B.15 - Subtract Instructions, p. 110 497defm SUB : F3_12 <"sub" , 0b000100, sub>; 498let Uses = [ICC] in 499 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 500 501let Defs = [ICC] in { 502 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 503 504 def CMPrr : F3_1<2, 0b010100, 505 (outs), (ins IntRegs:$b, IntRegs:$c), 506 "cmp $b, $c", 507 [(SPcmpicc i32:$b, i32:$c)]>; 508 def CMPri : F3_1<2, 0b010100, 509 (outs), (ins IntRegs:$b, i32imm:$c), 510 "cmp $b, $c", 511 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 512} 513 514let Uses = [ICC], Defs = [ICC] in 515 def SUBXCCrr: F3_1<2, 0b011100, 516 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 517 "subxcc $b, $c, $dst", []>; 518 519 520// Section B.18 - Multiply Instructions, p. 113 521let Defs = [Y] in { 522 defm UMUL : F3_12np<"umul", 0b001010>; 523 defm SMUL : F3_12 <"smul", 0b001011, mul>; 524} 525 526// Section B.19 - Divide Instructions, p. 115 527let Defs = [Y] in { 528 defm UDIV : F3_12np<"udiv", 0b001110>; 529 defm SDIV : F3_12np<"sdiv", 0b001111>; 530} 531 532// Section B.20 - SAVE and RESTORE, p. 117 533defm SAVE : F3_12np<"save" , 0b111100>; 534defm RESTORE : F3_12np<"restore", 0b111101>; 535 536// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 537 538// conditional branch class: 539class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 540 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 541 let isBranch = 1; 542 let isTerminator = 1; 543 let hasDelaySlot = 1; 544} 545 546let isBarrier = 1 in 547 def BA : BranchSP<0b1000, (ins brtarget:$dst), 548 "ba $dst", 549 [(br bb:$dst)]>; 550 551// Indirect branch instructions. 552let isTerminator = 1, isBarrier = 1, 553 hasDelaySlot = 1, isBranch =1, 554 isIndirectBranch = 1 in { 555 def BINDrr : F3_1<2, 0b111000, 556 (outs), (ins MEMrr:$ptr), 557 "jmp $ptr", 558 [(brind ADDRrr:$ptr)]>; 559 def BINDri : F3_2<2, 0b111000, 560 (outs), (ins MEMri:$ptr), 561 "jmp $ptr", 562 [(brind ADDRri:$ptr)]>; 563} 564 565// FIXME: the encoding for the JIT should look at the condition field. 566let Uses = [ICC] in 567 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 568 "b$cc $dst", 569 [(SPbricc bb:$dst, imm:$cc)]>; 570 571 572// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 573 574// floating-point conditional branch class: 575class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 576 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 577 let isBranch = 1; 578 let isTerminator = 1; 579 let hasDelaySlot = 1; 580} 581 582// FIXME: the encoding for the JIT should look at the condition field. 583let Uses = [FCC] in 584 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 585 "fb$cc $dst", 586 [(SPbrfcc bb:$dst, imm:$cc)]>; 587 588 589// Section B.24 - Call and Link Instruction, p. 125 590// This is the only Format 1 instruction 591let Uses = [O6], 592 hasDelaySlot = 1, isCall = 1 in { 593 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 594 "call $dst", []> { 595 bits<30> disp; 596 let op = 1; 597 let Inst{29-0} = disp; 598 } 599 600 // indirect calls 601 def JMPLrr : F3_1<2, 0b111000, 602 (outs), (ins MEMrr:$ptr, variable_ops), 603 "call $ptr", 604 [(call ADDRrr:$ptr)]>; 605 def JMPLri : F3_2<2, 0b111000, 606 (outs), (ins MEMri:$ptr, variable_ops), 607 "call $ptr", 608 [(call ADDRri:$ptr)]>; 609} 610 611// Section B.28 - Read State Register Instructions 612let Uses = [Y] in 613 def RDY : F3_1<2, 0b101000, 614 (outs IntRegs:$dst), (ins), 615 "rd %y, $dst", []>; 616 617// Section B.29 - Write State Register Instructions 618let Defs = [Y] in { 619 def WRYrr : F3_1<2, 0b110000, 620 (outs), (ins IntRegs:$b, IntRegs:$c), 621 "wr $b, $c, %y", []>; 622 def WRYri : F3_2<2, 0b110000, 623 (outs), (ins IntRegs:$b, i32imm:$c), 624 "wr $b, $c, %y", []>; 625} 626// Convert Integer to Floating-point Instructions, p. 141 627def FITOS : F3_3<2, 0b110100, 0b011000100, 628 (outs FPRegs:$dst), (ins FPRegs:$src), 629 "fitos $src, $dst", 630 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 631def FITOD : F3_3<2, 0b110100, 0b011001000, 632 (outs DFPRegs:$dst), (ins FPRegs:$src), 633 "fitod $src, $dst", 634 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 635def FITOQ : F3_3<2, 0b110100, 0b011001100, 636 (outs QFPRegs:$dst), (ins FPRegs:$src), 637 "fitoq $src, $dst", 638 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>, 639 Requires<[HasHardQuad]>; 640 641// Convert Floating-point to Integer Instructions, p. 142 642def FSTOI : F3_3<2, 0b110100, 0b011010001, 643 (outs FPRegs:$dst), (ins FPRegs:$src), 644 "fstoi $src, $dst", 645 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 646def FDTOI : F3_3<2, 0b110100, 0b011010010, 647 (outs FPRegs:$dst), (ins DFPRegs:$src), 648 "fdtoi $src, $dst", 649 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 650def FQTOI : F3_3<2, 0b110100, 0b011010011, 651 (outs FPRegs:$dst), (ins QFPRegs:$src), 652 "fqtoi $src, $dst", 653 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>, 654 Requires<[HasHardQuad]>; 655 656// Convert between Floating-point Formats Instructions, p. 143 657def FSTOD : F3_3<2, 0b110100, 0b011001001, 658 (outs DFPRegs:$dst), (ins FPRegs:$src), 659 "fstod $src, $dst", 660 [(set f64:$dst, (fextend f32:$src))]>; 661def FSTOQ : F3_3<2, 0b110100, 0b011001101, 662 (outs QFPRegs:$dst), (ins FPRegs:$src), 663 "fstoq $src, $dst", 664 [(set f128:$dst, (fextend f32:$src))]>, 665 Requires<[HasHardQuad]>; 666def FDTOS : F3_3<2, 0b110100, 0b011000110, 667 (outs FPRegs:$dst), (ins DFPRegs:$src), 668 "fdtos $src, $dst", 669 [(set f32:$dst, (fround f64:$src))]>; 670def FDTOQ : F3_3<2, 0b110100, 0b01101110, 671 (outs QFPRegs:$dst), (ins DFPRegs:$src), 672 "fdtoq $src, $dst", 673 [(set f128:$dst, (fextend f64:$src))]>, 674 Requires<[HasHardQuad]>; 675def FQTOS : F3_3<2, 0b110100, 0b011000111, 676 (outs FPRegs:$dst), (ins QFPRegs:$src), 677 "fqtos $src, $dst", 678 [(set f32:$dst, (fround f128:$src))]>, 679 Requires<[HasHardQuad]>; 680def FQTOD : F3_3<2, 0b110100, 0b011001011, 681 (outs DFPRegs:$dst), (ins QFPRegs:$src), 682 "fqtod $src, $dst", 683 [(set f64:$dst, (fround f128:$src))]>, 684 Requires<[HasHardQuad]>; 685 686// Floating-point Move Instructions, p. 144 687def FMOVS : F3_3<2, 0b110100, 0b000000001, 688 (outs FPRegs:$dst), (ins FPRegs:$src), 689 "fmovs $src, $dst", []>; 690def FNEGS : F3_3<2, 0b110100, 0b000000101, 691 (outs FPRegs:$dst), (ins FPRegs:$src), 692 "fnegs $src, $dst", 693 [(set f32:$dst, (fneg f32:$src))]>; 694def FABSS : F3_3<2, 0b110100, 0b000001001, 695 (outs FPRegs:$dst), (ins FPRegs:$src), 696 "fabss $src, $dst", 697 [(set f32:$dst, (fabs f32:$src))]>; 698 699 700// Floating-point Square Root Instructions, p.145 701def FSQRTS : F3_3<2, 0b110100, 0b000101001, 702 (outs FPRegs:$dst), (ins FPRegs:$src), 703 "fsqrts $src, $dst", 704 [(set f32:$dst, (fsqrt f32:$src))]>; 705def FSQRTD : F3_3<2, 0b110100, 0b000101010, 706 (outs DFPRegs:$dst), (ins DFPRegs:$src), 707 "fsqrtd $src, $dst", 708 [(set f64:$dst, (fsqrt f64:$src))]>; 709def FSQRTQ : F3_3<2, 0b110100, 0b000101011, 710 (outs QFPRegs:$dst), (ins QFPRegs:$src), 711 "fsqrtq $src, $dst", 712 [(set f128:$dst, (fsqrt f128:$src))]>, 713 Requires<[HasHardQuad]>; 714 715 716 717// Floating-point Add and Subtract Instructions, p. 146 718def FADDS : F3_3<2, 0b110100, 0b001000001, 719 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 720 "fadds $src1, $src2, $dst", 721 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 722def FADDD : F3_3<2, 0b110100, 0b001000010, 723 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 724 "faddd $src1, $src2, $dst", 725 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 726def FADDQ : F3_3<2, 0b110100, 0b001000011, 727 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 728 "faddq $src1, $src2, $dst", 729 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>, 730 Requires<[HasHardQuad]>; 731 732def FSUBS : F3_3<2, 0b110100, 0b001000101, 733 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 734 "fsubs $src1, $src2, $dst", 735 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 736def FSUBD : F3_3<2, 0b110100, 0b001000110, 737 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 738 "fsubd $src1, $src2, $dst", 739 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 740def FSUBQ : F3_3<2, 0b110100, 0b001000111, 741 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 742 "fsubq $src1, $src2, $dst", 743 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>, 744 Requires<[HasHardQuad]>; 745 746 747// Floating-point Multiply and Divide Instructions, p. 147 748def FMULS : F3_3<2, 0b110100, 0b001001001, 749 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 750 "fmuls $src1, $src2, $dst", 751 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 752def FMULD : F3_3<2, 0b110100, 0b001001010, 753 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 754 "fmuld $src1, $src2, $dst", 755 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 756def FMULQ : F3_3<2, 0b110100, 0b001001011, 757 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 758 "fmulq $src1, $src2, $dst", 759 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>, 760 Requires<[HasHardQuad]>; 761 762def FSMULD : F3_3<2, 0b110100, 0b001101001, 763 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 764 "fsmuld $src1, $src2, $dst", 765 [(set f64:$dst, (fmul (fextend f32:$src1), 766 (fextend f32:$src2)))]>; 767def FDMULQ : F3_3<2, 0b110100, 0b001101110, 768 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 769 "fdmulq $src1, $src2, $dst", 770 [(set f128:$dst, (fmul (fextend f64:$src1), 771 (fextend f64:$src2)))]>, 772 Requires<[HasHardQuad]>; 773 774def FDIVS : F3_3<2, 0b110100, 0b001001101, 775 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 776 "fdivs $src1, $src2, $dst", 777 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 778def FDIVD : F3_3<2, 0b110100, 0b001001110, 779 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 780 "fdivd $src1, $src2, $dst", 781 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 782def FDIVQ : F3_3<2, 0b110100, 0b001001111, 783 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 784 "fdivq $src1, $src2, $dst", 785 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>, 786 Requires<[HasHardQuad]>; 787 788// Floating-point Compare Instructions, p. 148 789// Note: the 2nd template arg is different for these guys. 790// Note 2: the result of a FCMP is not available until the 2nd cycle 791// after the instr is retired, but there is no interlock. This behavior 792// is modelled with a forced noop after the instruction. 793let Defs = [FCC] in { 794 def FCMPS : F3_3<2, 0b110101, 0b001010001, 795 (outs), (ins FPRegs:$src1, FPRegs:$src2), 796 "fcmps $src1, $src2\n\tnop", 797 [(SPcmpfcc f32:$src1, f32:$src2)]>; 798 def FCMPD : F3_3<2, 0b110101, 0b001010010, 799 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 800 "fcmpd $src1, $src2\n\tnop", 801 [(SPcmpfcc f64:$src1, f64:$src2)]>; 802 def FCMPQ : F3_3<2, 0b110101, 0b001010011, 803 (outs), (ins QFPRegs:$src1, QFPRegs:$src2), 804 "fcmpq $src1, $src2\n\tnop", 805 [(SPcmpfcc f128:$src1, f128:$src2)]>, 806 Requires<[HasHardQuad]>; 807} 808 809//===----------------------------------------------------------------------===// 810// V9 Instructions 811//===----------------------------------------------------------------------===// 812 813// V9 Conditional Moves. 814let Predicates = [HasV9], Constraints = "$f = $rd" in { 815 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 816 // FIXME: Add instruction encodings for the JIT some day. 817 let Uses = [ICC] in { 818 def MOVICCrr 819 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 820 "mov$cc %icc, $rs2, $rd", 821 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>; 822 def MOVICCri 823 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 824 "mov$cc %icc, $i, $rd", 825 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>; 826 } 827 828 let Uses = [FCC] in { 829 def MOVFCCrr 830 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 831 "mov$cc %fcc0, $rs2, $rd", 832 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>; 833 def MOVFCCri 834 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 835 "mov$cc %fcc0, $i, $rd", 836 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>; 837 } 838 839 let Uses = [ICC] in { 840 def FMOVS_ICC 841 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 842 "fmovs$cc %icc, $rs2, $rd", 843 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>; 844 def FMOVD_ICC 845 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 846 "fmovd$cc %icc, $rs2, $rd", 847 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>; 848 } 849 850 let Uses = [FCC] in { 851 def FMOVS_FCC 852 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 853 "fmovs$cc %fcc0, $rs2, $rd", 854 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>; 855 def FMOVD_FCC 856 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 857 "fmovd$cc %fcc0, $rs2, $rd", 858 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>; 859 } 860 861} 862 863// Floating-Point Move Instructions, p. 164 of the V9 manual. 864let Predicates = [HasV9] in { 865 def FMOVD : F3_3<2, 0b110100, 0b000000010, 866 (outs DFPRegs:$dst), (ins DFPRegs:$src), 867 "fmovd $src, $dst", []>; 868 def FMOVQ : F3_3<2, 0b110100, 0b000000011, 869 (outs QFPRegs:$dst), (ins QFPRegs:$src), 870 "fmovq $src, $dst", []>, 871 Requires<[HasHardQuad]>; 872 def FNEGD : F3_3<2, 0b110100, 0b000000110, 873 (outs DFPRegs:$dst), (ins DFPRegs:$src), 874 "fnegd $src, $dst", 875 [(set f64:$dst, (fneg f64:$src))]>; 876 def FNEGQ : F3_3<2, 0b110100, 0b000000111, 877 (outs QFPRegs:$dst), (ins QFPRegs:$src), 878 "fnegq $src, $dst", 879 [(set f128:$dst, (fneg f128:$src))]>, 880 Requires<[HasHardQuad]>; 881 def FABSD : F3_3<2, 0b110100, 0b000001010, 882 (outs DFPRegs:$dst), (ins DFPRegs:$src), 883 "fabsd $src, $dst", 884 [(set f64:$dst, (fabs f64:$src))]>; 885 def FABSQ : F3_3<2, 0b110100, 0b000001011, 886 (outs QFPRegs:$dst), (ins QFPRegs:$src), 887 "fabsq $src, $dst", 888 [(set f128:$dst, (fabs f128:$src))]>, 889 Requires<[HasHardQuad]>; 890} 891 892// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 893// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 894def POPCrr : F3_1<2, 0b101110, 895 (outs IntRegs:$dst), (ins IntRegs:$src), 896 "popc $src, $dst", []>, Requires<[HasV9]>; 897def : Pat<(ctpop i32:$src), 898 (POPCrr (SLLri $src, 0))>; 899 900//===----------------------------------------------------------------------===// 901// Non-Instruction Patterns 902//===----------------------------------------------------------------------===// 903 904// Small immediates. 905def : Pat<(i32 simm13:$val), 906 (ORri (i32 G0), imm:$val)>; 907// Arbitrary immediates. 908def : Pat<(i32 imm:$val), 909 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 910 911 912// Global addresses, constant pool entries 913def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 914def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 915def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 916def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 917 918// Blockaddress 919def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 920def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 921 922// Add reg, lo. This is used when taking the addr of a global/constpool entry. 923def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 924def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 925def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 926 (ADDri $r, tblockaddress:$in)>; 927 928// Calls: 929def : Pat<(call tglobaladdr:$dst), 930 (CALL tglobaladdr:$dst)>; 931def : Pat<(call texternalsym:$dst), 932 (CALL texternalsym:$dst)>; 933 934// Map integer extload's to zextloads. 935def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 936def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 937def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 938def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 939def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 940def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 941 942// zextload bool -> zextload byte 943def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 944def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 945 946// store 0, addr -> store %g0, addr 947def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 948def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 949 950include "SparcInstr64Bit.td" 951