SparcInstrInfo.td revision 82a4795850d694b010b3dac0f48d9468496aa243
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm> : InstV8 { 39 let Name = nm; 40} 41def PHI : PseudoInstV8<"PHI">; 42def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">; 43def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">; 44def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">; 45def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">; 46def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move 47 48// Section A.3 - Synthetic Instructions, p. 85 49// special cases of JMPL: 50let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 51 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 52 def RET : F3_2<2, 0b111000, "ret">; 53 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 54 def RETL: F3_2<2, 0b111000, "retl">; 55} 56// CMP is a special case of SUBCC where destination is ignored, by setting it to 57// %g0 (hardwired zero). 58// FIXME: should keep track of the fact that it defs the integer condition codes 59let rd = 0 in 60 def CMPri: F3_2<2, 0b010100, "cmp">; 61 62// Section B.1 - Load Integer Instructions, p. 90 63def LDSB: F3_2<3, 0b001001, "ldsb">; 64def LDSH: F3_2<3, 0b001010, "ldsh">; 65def LDUB: F3_2<3, 0b000001, "ldub">; 66def LDUH: F3_2<3, 0b000010, "lduh">; 67def LD : F3_2<3, 0b000000, "ld">; 68def LDD : F3_2<3, 0b000011, "ldd">; 69 70// Section B.2 - Load Floating-point Instructions, p. 92 71def LDFrr : F3_1<3, 0b100000, "ld">; 72def LDFri : F3_2<3, 0b100000, "ld">; 73def LDDFrr : F3_1<3, 0b100011, "ldd">; 74def LDDFri : F3_2<3, 0b100011, "ldd">; 75def LDFSRrr: F3_1<3, 0b100001, "ld">; 76def LDFSRri: F3_2<3, 0b100001, "ld">; 77 78// Section B.4 - Store Integer Instructions, p. 95 79def STB : F3_2<3, 0b000101, "stb">; 80def STH : F3_2<3, 0b000110, "sth">; 81def ST : F3_2<3, 0b000100, "st">; 82def STD : F3_2<3, 0b000111, "std">; 83 84// Section B.5 - Store Floating-point Instructions, p. 97 85def STFrr : F3_1<3, 0b100100, "st">; 86def STFri : F3_2<3, 0b100100, "st">; 87def STDFrr : F3_1<3, 0b100111, "std">; 88def STDFri : F3_2<3, 0b100111, "std">; 89def STFSRrr : F3_1<3, 0b100101, "st">; 90def STFSRri : F3_2<3, 0b100101, "st">; 91def STDFQrr : F3_1<3, 0b100110, "std">; 92def STDFQri : F3_2<3, 0b100110, "std">; 93 94// Section B.9 - SETHI Instruction, p. 104 95def SETHIi: F2_1<0b100, "sethi">; 96 97// Section B.10 - NOP Instruction, p. 105 98// (It's a special case of SETHI) 99let rd = 0, imm22 = 0 in 100 def NOP : F2_1<0b100, "nop">; 101 102// Section B.11 - Logical Instructions, p. 106 103def ANDrr : F3_1<2, 0b000001, "and">; 104def ANDri : F3_2<2, 0b000001, "and">; 105def ANDCCrr : F3_1<2, 0b010001, "andcc">; 106def ANDCCri : F3_2<2, 0b010001, "andcc">; 107def ANDNrr : F3_1<2, 0b000101, "andn">; 108def ANDNri : F3_2<2, 0b000101, "andn">; 109def ANDNCCrr: F3_1<2, 0b010101, "andncc">; 110def ANDNCCri: F3_2<2, 0b010101, "andncc">; 111def ORrr : F3_1<2, 0b000010, "or">; 112def ORri : F3_2<2, 0b000010, "or">; 113def ORCCrr : F3_1<2, 0b010010, "orcc">; 114def ORCCri : F3_2<2, 0b010010, "orcc">; 115def ORNrr : F3_1<2, 0b000110, "orn">; 116def ORNri : F3_2<2, 0b000110, "orn">; 117def ORNCCrr : F3_1<2, 0b010110, "orncc">; 118def ORNCCri : F3_2<2, 0b010110, "orncc">; 119def XORrr : F3_1<2, 0b000011, "xor">; 120def XORri : F3_2<2, 0b000011, "xor">; 121def XORCCrr : F3_1<2, 0b010011, "xorcc">; 122def XORCCri : F3_2<2, 0b010011, "xorcc">; 123def XNORrr : F3_1<2, 0b000111, "xnor">; 124def XNORri : F3_2<2, 0b000111, "xnor">; 125def XNORCCrr: F3_1<2, 0b010111, "xnorcc">; 126def XNORCCri: F3_2<2, 0b010111, "xnorcc">; 127 128// Section B.12 - Shift Instructions, p. 107 129def SLLrr : F3_1<2, 0b100101, "sll">; 130def SLLri : F3_2<2, 0b100101, "sll">; 131def SRLrr : F3_1<2, 0b100110, "srl">; 132def SRLri : F3_2<2, 0b100110, "srl">; 133def SRArr : F3_1<2, 0b100111, "sra">; 134def SRAri : F3_2<2, 0b100111, "sra">; 135 136// Section B.13 - Add Instructions, p. 108 137def ADDrr : F3_1<2, 0b000000, "add">; 138def ADDri : F3_2<2, 0b000000, "add">; 139def ADDCCrr : F3_1<2, 0b010000, "addcc">; 140def ADDCCri : F3_2<2, 0b010000, "addcc">; 141def ADDXrr : F3_1<2, 0b001000, "addx">; 142def ADDXri : F3_2<2, 0b001000, "addx">; 143def ADDXCCrr: F3_1<2, 0b011000, "addxcc">; 144def ADDXCCri: F3_2<2, 0b011000, "addxcc">; 145 146// Section B.15 - Subtract Instructions, p. 110 147def SUBrr : F3_1<2, 0b000100, "sub">; 148def SUBri : F3_2<2, 0b000100, "sub">; 149def SUBCCrr : F3_1<2, 0b010100, "subcc">; 150def SUBCCri : F3_2<2, 0b010100, "subcc">; 151def SUBXrr : F3_1<2, 0b001100, "subx">; 152def SUBXri : F3_2<2, 0b001100, "subx">; 153def SUBXCCrr: F3_1<2, 0b011100, "subxcc">; 154def SUBXCCri: F3_2<2, 0b011100, "subxcc">; 155 156// Section B.18 - Multiply Instructions, p. 113 157def UMULrr : F3_1<2, 0b001010, "umul">; 158def SMULrr : F3_1<2, 0b001011, "smul">; 159 160// Section B.19 - Divide Instructions, p. 115 161def UDIVrr : F3_1<2, 0b001110, "udiv">; 162def UDIVri : F3_2<2, 0b001110, "udiv">; 163def SDIVrr : F3_1<2, 0b001111, "sdiv">; 164def SDIVri : F3_2<2, 0b001111, "sdiv">; 165def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 166def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 167def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 168def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 169 170// Section B.20 - SAVE and RESTORE, p. 117 171def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 172def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 173def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 174def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 175 176// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 177 178// conditional branch class: 179class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 180 let isBranch = 1; 181 let isTerminator = 1; 182 let hasDelaySlot = 1; 183} 184 185let isBarrier = 1 in 186 def BA : BranchV8<0b1000, "ba">; 187def BN : BranchV8<0b0000, "bn">; 188def BNE : BranchV8<0b1001, "bne">; 189def BE : BranchV8<0b0001, "be">; 190def BG : BranchV8<0b1010, "bg">; 191def BLE : BranchV8<0b0010, "ble">; 192def BGE : BranchV8<0b1011, "bge">; 193def BL : BranchV8<0b0011, "bl">; 194def BGU : BranchV8<0b1100, "bgu">; 195def BLEU : BranchV8<0b0100, "bleu">; 196def BCC : BranchV8<0b1101, "bcc">; 197def BCS : BranchV8<0b0101, "bcs">; 198 199// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 200 201// floating-point conditional branch class: 202class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 203 let isBranch = 1; 204 let isTerminator = 1; 205 let hasDelaySlot = 1; 206} 207 208def FBA : FPBranchV8<0b1000, "fba">; 209def FBN : FPBranchV8<0b0000, "fbn">; 210def FBU : FPBranchV8<0b0111, "fbu">; 211def FBG : FPBranchV8<0b0110, "fbg">; 212def FBUG : FPBranchV8<0b0101, "fbug">; 213def FBL : FPBranchV8<0b0100, "fbl">; 214def FBUL : FPBranchV8<0b0011, "fbul">; 215def FBLG : FPBranchV8<0b0010, "fblg">; 216def FBNE : FPBranchV8<0b0001, "fbne">; 217def FBE : FPBranchV8<0b1001, "fbe">; 218def FBUE : FPBranchV8<0b1010, "fbue">; 219def FBGE : FPBranchV8<0b1011, "fbge">; 220def FBUGE: FPBranchV8<0b1100, "fbuge">; 221def FBLE : FPBranchV8<0b1101, "fble">; 222def FBULE: FPBranchV8<0b1110, "fbule">; 223def FBO : FPBranchV8<0b1111, "fbo">; 224 225 226 227// Section B.24 - Call and Link Instruction, p. 125 228// This is the only Format 1 instruction 229let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 230 // pc-relative call: 231 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 232 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 233 def CALL : InstV8 { 234 bits<30> disp; 235 let op = 1; 236 let Inst{29-0} = disp; 237 let Name = "call"; 238 } 239 240 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 241 // be an implicit def): 242 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 243 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 244 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 245} 246 247// Section B.29 - Write State Register Instructions 248def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 249def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 250 251// Convert Integer to Floating-point Instructions, p. 141 252def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 253def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">; 254 255// Convert Floating-point to Integer Instructions, p. 142 256def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">; 257def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">; 258 259// Convert between Floating-point Formats Instructions, p. 143 260def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 261def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 262 263// Floating-point Move Instructions, p. 144 264def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 265def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 266def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 267 268// Floating-point Add and Subtract Instructions, p. 146 269def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 270def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 271def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 272def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 273 274// Floating-point Multiply and Divide Instructions, p. 147 275def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 276def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 277def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 278def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 279def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 280 281// Floating-point Compare Instructions, p. 148 282// Note: the 2nd template arg is different for these guys. 283// Note 2: the result of a FCMP is not available until the 2nd cycle 284// after the instr is retired, but there is no interlock. This behavior 285// is modelled as a delay slot. 286let hasDelaySlot = 1 in { 287 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 288 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 289 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 290 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 291} 292 293