SparcInstrInfo.td revision 860b64cb1efba110bf81bcc243a6fbaae4c655a4
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 47 48def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 49 50def LO10 : SDNodeXForm<imm, [{ 51 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 52 MVT::i32); 53}]>; 54 55def HI22 : SDNodeXForm<imm, [{ 56 // Transformation function: shift the immediate value down into the low bits. 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 58}]>; 59 60def SETHIimm : PatLeaf<(imm), [{ 61 return (((unsigned)N->getZExtValue() >> 10) << 10) == 62 (unsigned)N->getZExtValue(); 63}], HI22>; 64 65// Addressing modes. 66def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 67def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 68 69// Address operands 70def MEMrr : Operand<i32> { 71 let PrintMethod = "printMemOperand"; 72 let MIOperandInfo = (ops IntRegs, IntRegs); 73} 74def MEMri : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, i32imm); 77} 78 79// Branch targets have OtherVT type. 80def brtarget : Operand<OtherVT>; 81def calltarget : Operand<i32>; 82 83// Operand for printing out a condition code. 84let PrintMethod = "printCCOperand" in 85 def CCOp : Operand<i32>; 86 87def SDTSPcmpfcc : 88SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 89def SDTSPbrcc : 90SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 91def SDTSPselectcc : 92SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 93def SDTSPFTOI : 94SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 95def SDTSPITOF : 96SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 97 98def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>; 99def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 100def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 101def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 102 103def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 104def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 105 106def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 107def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 108 109def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 110def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 111 112// These are target-independent nodes, but have target-specific formats. 113def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 114def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 115 SDTCisVT<1, i32> ]>; 116 117def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 118 [SDNPHasChain, SDNPOutGlue]>; 119def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 121 122def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 123def call : SDNode<"SPISD::CALL", SDT_SPCall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 125 SDNPVariadic]>; 126 127def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 128 [SDNPHasChain, SDNPOptInGlue]>; 129 130def flush : SDNode<"SPISD::FLUSH", SDTNone, 131 [SDNPHasChain]>; 132 133def getPCX : Operand<i32> { 134 let PrintMethod = "printGetPCX"; 135} 136 137//===----------------------------------------------------------------------===// 138// SPARC Flag Conditions 139//===----------------------------------------------------------------------===// 140 141// Note that these values must be kept in sync with the CCOp::CondCode enum 142// values. 143class ICC_VAL<int N> : PatLeaf<(i32 N)>; 144def ICC_NE : ICC_VAL< 9>; // Not Equal 145def ICC_E : ICC_VAL< 1>; // Equal 146def ICC_G : ICC_VAL<10>; // Greater 147def ICC_LE : ICC_VAL< 2>; // Less or Equal 148def ICC_GE : ICC_VAL<11>; // Greater or Equal 149def ICC_L : ICC_VAL< 3>; // Less 150def ICC_GU : ICC_VAL<12>; // Greater Unsigned 151def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 152def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 153def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 154def ICC_POS : ICC_VAL<14>; // Positive 155def ICC_NEG : ICC_VAL< 6>; // Negative 156def ICC_VC : ICC_VAL<15>; // Overflow Clear 157def ICC_VS : ICC_VAL< 7>; // Overflow Set 158 159class FCC_VAL<int N> : PatLeaf<(i32 N)>; 160def FCC_U : FCC_VAL<23>; // Unordered 161def FCC_G : FCC_VAL<22>; // Greater 162def FCC_UG : FCC_VAL<21>; // Unordered or Greater 163def FCC_L : FCC_VAL<20>; // Less 164def FCC_UL : FCC_VAL<19>; // Unordered or Less 165def FCC_LG : FCC_VAL<18>; // Less or Greater 166def FCC_NE : FCC_VAL<17>; // Not Equal 167def FCC_E : FCC_VAL<25>; // Equal 168def FCC_UE : FCC_VAL<24>; // Unordered or Equal 169def FCC_GE : FCC_VAL<25>; // Greater or Equal 170def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 171def FCC_LE : FCC_VAL<27>; // Less or Equal 172def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 173def FCC_O : FCC_VAL<29>; // Ordered 174 175//===----------------------------------------------------------------------===// 176// Instruction Class Templates 177//===----------------------------------------------------------------------===// 178 179/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 180multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 181 def rr : F3_1<2, Op3Val, 182 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 183 !strconcat(OpcStr, " $b, $c, $dst"), 184 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 185 def ri : F3_2<2, Op3Val, 186 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 187 !strconcat(OpcStr, " $b, $c, $dst"), 188 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 189} 190 191/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 192/// pattern. 193multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 194 def rr : F3_1<2, Op3Val, 195 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 196 !strconcat(OpcStr, " $b, $c, $dst"), []>; 197 def ri : F3_2<2, Op3Val, 198 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 199 !strconcat(OpcStr, " $b, $c, $dst"), []>; 200} 201 202//===----------------------------------------------------------------------===// 203// Instructions 204//===----------------------------------------------------------------------===// 205 206// Pseudo instructions. 207class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 208 : InstSP<outs, ins, asmstr, pattern>; 209 210// GETPCX for PIC 211let Defs = [O7] in { 212 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 213} 214 215let Defs = [O6], Uses = [O6] in { 216def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 217 "!ADJCALLSTACKDOWN $amt", 218 [(callseq_start timm:$amt)]>; 219def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 220 "!ADJCALLSTACKUP $amt1", 221 [(callseq_end timm:$amt1, timm:$amt2)]>; 222} 223 224let hasSideEffects = 1, mayStore = 1 in 225 let rs2 = 0 in 226 def FLUSH : F3_1<0b10, 0b101011, (outs), (ins), 227 "flushw", 228 [(flush)]>; 229 230// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 231// fpmover pass. 232let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 233 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 234 "!FpMOVD $src, $dst", []>; 235 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 236 "!FpNEGD $src, $dst", 237 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 238 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 239 "!FpABSD $src, $dst", 240 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 241} 242 243// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 244// instruction selection into a branch sequence. This has to handle all 245// permutations of selection between i32/f32/f64 on ICC and FCC. 246 // Expanded after instruction selection. 247let Uses = [ICC], usesCustomInserter = 1 in { 248 def SELECT_CC_Int_ICC 249 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 250 "; SELECT_CC_Int_ICC PSEUDO!", 251 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 252 imm:$Cond))]>; 253 def SELECT_CC_FP_ICC 254 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 255 "; SELECT_CC_FP_ICC PSEUDO!", 256 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 257 imm:$Cond))]>; 258 259 def SELECT_CC_DFP_ICC 260 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 261 "; SELECT_CC_DFP_ICC PSEUDO!", 262 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 263 imm:$Cond))]>; 264} 265 266let usesCustomInserter = 1, Uses = [FCC] in { 267 268 def SELECT_CC_Int_FCC 269 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 270 "; SELECT_CC_Int_FCC PSEUDO!", 271 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 272 imm:$Cond))]>; 273 274 def SELECT_CC_FP_FCC 275 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 276 "; SELECT_CC_FP_FCC PSEUDO!", 277 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 278 imm:$Cond))]>; 279 def SELECT_CC_DFP_FCC 280 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 281 "; SELECT_CC_DFP_FCC PSEUDO!", 282 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 283 imm:$Cond))]>; 284} 285 286 287// Section A.3 - Synthetic Instructions, p. 85 288// special cases of JMPL: 289let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 290 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 291 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 292} 293 294// Section B.1 - Load Integer Instructions, p. 90 295def LDSBrr : F3_1<3, 0b001001, 296 (outs IntRegs:$dst), (ins MEMrr:$addr), 297 "ldsb [$addr], $dst", 298 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 299def LDSBri : F3_2<3, 0b001001, 300 (outs IntRegs:$dst), (ins MEMri:$addr), 301 "ldsb [$addr], $dst", 302 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 303def LDSHrr : F3_1<3, 0b001010, 304 (outs IntRegs:$dst), (ins MEMrr:$addr), 305 "ldsh [$addr], $dst", 306 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 307def LDSHri : F3_2<3, 0b001010, 308 (outs IntRegs:$dst), (ins MEMri:$addr), 309 "ldsh [$addr], $dst", 310 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 311def LDUBrr : F3_1<3, 0b000001, 312 (outs IntRegs:$dst), (ins MEMrr:$addr), 313 "ldub [$addr], $dst", 314 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 315def LDUBri : F3_2<3, 0b000001, 316 (outs IntRegs:$dst), (ins MEMri:$addr), 317 "ldub [$addr], $dst", 318 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 319def LDUHrr : F3_1<3, 0b000010, 320 (outs IntRegs:$dst), (ins MEMrr:$addr), 321 "lduh [$addr], $dst", 322 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 323def LDUHri : F3_2<3, 0b000010, 324 (outs IntRegs:$dst), (ins MEMri:$addr), 325 "lduh [$addr], $dst", 326 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 327def LDrr : F3_1<3, 0b000000, 328 (outs IntRegs:$dst), (ins MEMrr:$addr), 329 "ld [$addr], $dst", 330 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 331def LDri : F3_2<3, 0b000000, 332 (outs IntRegs:$dst), (ins MEMri:$addr), 333 "ld [$addr], $dst", 334 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 335 336// Section B.2 - Load Floating-point Instructions, p. 92 337def LDFrr : F3_1<3, 0b100000, 338 (outs FPRegs:$dst), (ins MEMrr:$addr), 339 "ld [$addr], $dst", 340 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 341def LDFri : F3_2<3, 0b100000, 342 (outs FPRegs:$dst), (ins MEMri:$addr), 343 "ld [$addr], $dst", 344 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 345def LDDFrr : F3_1<3, 0b100011, 346 (outs DFPRegs:$dst), (ins MEMrr:$addr), 347 "ldd [$addr], $dst", 348 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 349def LDDFri : F3_2<3, 0b100011, 350 (outs DFPRegs:$dst), (ins MEMri:$addr), 351 "ldd [$addr], $dst", 352 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 353 354// Section B.4 - Store Integer Instructions, p. 95 355def STBrr : F3_1<3, 0b000101, 356 (outs), (ins MEMrr:$addr, IntRegs:$src), 357 "stb $src, [$addr]", 358 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 359def STBri : F3_2<3, 0b000101, 360 (outs), (ins MEMri:$addr, IntRegs:$src), 361 "stb $src, [$addr]", 362 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 363def STHrr : F3_1<3, 0b000110, 364 (outs), (ins MEMrr:$addr, IntRegs:$src), 365 "sth $src, [$addr]", 366 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 367def STHri : F3_2<3, 0b000110, 368 (outs), (ins MEMri:$addr, IntRegs:$src), 369 "sth $src, [$addr]", 370 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 371def STrr : F3_1<3, 0b000100, 372 (outs), (ins MEMrr:$addr, IntRegs:$src), 373 "st $src, [$addr]", 374 [(store IntRegs:$src, ADDRrr:$addr)]>; 375def STri : F3_2<3, 0b000100, 376 (outs), (ins MEMri:$addr, IntRegs:$src), 377 "st $src, [$addr]", 378 [(store IntRegs:$src, ADDRri:$addr)]>; 379 380// Section B.5 - Store Floating-point Instructions, p. 97 381def STFrr : F3_1<3, 0b100100, 382 (outs), (ins MEMrr:$addr, FPRegs:$src), 383 "st $src, [$addr]", 384 [(store FPRegs:$src, ADDRrr:$addr)]>; 385def STFri : F3_2<3, 0b100100, 386 (outs), (ins MEMri:$addr, FPRegs:$src), 387 "st $src, [$addr]", 388 [(store FPRegs:$src, ADDRri:$addr)]>; 389def STDFrr : F3_1<3, 0b100111, 390 (outs), (ins MEMrr:$addr, DFPRegs:$src), 391 "std $src, [$addr]", 392 [(store DFPRegs:$src, ADDRrr:$addr)]>; 393def STDFri : F3_2<3, 0b100111, 394 (outs), (ins MEMri:$addr, DFPRegs:$src), 395 "std $src, [$addr]", 396 [(store DFPRegs:$src, ADDRri:$addr)]>; 397 398// Section B.9 - SETHI Instruction, p. 104 399def SETHIi: F2_1<0b100, 400 (outs IntRegs:$dst), (ins i32imm:$src), 401 "sethi $src, $dst", 402 [(set IntRegs:$dst, SETHIimm:$src)]>; 403 404// Section B.10 - NOP Instruction, p. 105 405// (It's a special case of SETHI) 406let rd = 0, imm22 = 0 in 407 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 408 409// Section B.11 - Logical Instructions, p. 106 410defm AND : F3_12<"and", 0b000001, and>; 411 412def ANDNrr : F3_1<2, 0b000101, 413 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 414 "andn $b, $c, $dst", 415 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 416def ANDNri : F3_2<2, 0b000101, 417 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 418 "andn $b, $c, $dst", []>; 419 420defm OR : F3_12<"or", 0b000010, or>; 421 422def ORNrr : F3_1<2, 0b000110, 423 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 424 "orn $b, $c, $dst", 425 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 426def ORNri : F3_2<2, 0b000110, 427 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 428 "orn $b, $c, $dst", []>; 429defm XOR : F3_12<"xor", 0b000011, xor>; 430 431def XNORrr : F3_1<2, 0b000111, 432 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 433 "xnor $b, $c, $dst", 434 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 435def XNORri : F3_2<2, 0b000111, 436 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 437 "xnor $b, $c, $dst", []>; 438 439// Section B.12 - Shift Instructions, p. 107 440defm SLL : F3_12<"sll", 0b100101, shl>; 441defm SRL : F3_12<"srl", 0b100110, srl>; 442defm SRA : F3_12<"sra", 0b100111, sra>; 443 444// Section B.13 - Add Instructions, p. 108 445defm ADD : F3_12<"add", 0b000000, add>; 446 447// "LEA" forms of add (patterns to make tblgen happy) 448def LEA_ADDri : F3_2<2, 0b000000, 449 (outs IntRegs:$dst), (ins MEMri:$addr), 450 "add ${addr:arith}, $dst", 451 [(set IntRegs:$dst, ADDRri:$addr)]>; 452 453let Defs = [ICC] in 454 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 455 456let Uses = [ICC] in 457 defm ADDX : F3_12<"addx", 0b001000, adde>; 458 459// Section B.15 - Subtract Instructions, p. 110 460defm SUB : F3_12 <"sub" , 0b000100, sub>; 461let Uses = [ICC] in 462 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 463 464let Defs = [ICC] in 465 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 466 467let Uses = [ICC], Defs = [ICC] in 468 def SUBXCCrr: F3_1<2, 0b011100, 469 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 470 "subxcc $b, $c, $dst", []>; 471 472 473// Section B.18 - Multiply Instructions, p. 113 474let Defs = [Y] in { 475 defm UMUL : F3_12np<"umul", 0b001010>; 476 defm SMUL : F3_12 <"smul", 0b001011, mul>; 477} 478 479// Section B.19 - Divide Instructions, p. 115 480let Defs = [Y] in { 481 defm UDIV : F3_12np<"udiv", 0b001110>; 482 defm SDIV : F3_12np<"sdiv", 0b001111>; 483} 484 485// Section B.20 - SAVE and RESTORE, p. 117 486defm SAVE : F3_12np<"save" , 0b111100>; 487defm RESTORE : F3_12np<"restore", 0b111101>; 488 489// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 490 491// conditional branch class: 492class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 493 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 494 let isBranch = 1; 495 let isTerminator = 1; 496 let hasDelaySlot = 1; 497} 498 499let isBarrier = 1 in 500 def BA : BranchSP<0b1000, (ins brtarget:$dst), 501 "ba $dst", 502 [(br bb:$dst)]>; 503 504// FIXME: the encoding for the JIT should look at the condition field. 505let Uses = [ICC] in 506 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 507 "b$cc $dst", 508 [(SPbricc bb:$dst, imm:$cc)]>; 509 510 511// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 512 513// floating-point conditional branch class: 514class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 515 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 516 let isBranch = 1; 517 let isTerminator = 1; 518 let hasDelaySlot = 1; 519} 520 521// FIXME: the encoding for the JIT should look at the condition field. 522let Uses = [FCC] in 523 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 524 "fb$cc $dst", 525 [(SPbrfcc bb:$dst, imm:$cc)]>; 526 527 528// Section B.24 - Call and Link Instruction, p. 125 529// This is the only Format 1 instruction 530let Uses = [O6], 531 hasDelaySlot = 1, isCall = 1, 532 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 533 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 534 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 535 "call $dst", []> { 536 bits<30> disp; 537 let op = 1; 538 let Inst{29-0} = disp; 539 } 540 541 // indirect calls 542 def JMPLrr : F3_1<2, 0b111000, 543 (outs), (ins MEMrr:$ptr, variable_ops), 544 "call $ptr", 545 [(call ADDRrr:$ptr)]>; 546 def JMPLri : F3_2<2, 0b111000, 547 (outs), (ins MEMri:$ptr, variable_ops), 548 "call $ptr", 549 [(call ADDRri:$ptr)]>; 550} 551 552// Section B.28 - Read State Register Instructions 553let Uses = [Y] in 554 def RDY : F3_1<2, 0b101000, 555 (outs IntRegs:$dst), (ins), 556 "rd %y, $dst", []>; 557 558// Section B.29 - Write State Register Instructions 559let Defs = [Y] in { 560 def WRYrr : F3_1<2, 0b110000, 561 (outs), (ins IntRegs:$b, IntRegs:$c), 562 "wr $b, $c, %y", []>; 563 def WRYri : F3_2<2, 0b110000, 564 (outs), (ins IntRegs:$b, i32imm:$c), 565 "wr $b, $c, %y", []>; 566} 567// Convert Integer to Floating-point Instructions, p. 141 568def FITOS : F3_3<2, 0b110100, 0b011000100, 569 (outs FPRegs:$dst), (ins FPRegs:$src), 570 "fitos $src, $dst", 571 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 572def FITOD : F3_3<2, 0b110100, 0b011001000, 573 (outs DFPRegs:$dst), (ins FPRegs:$src), 574 "fitod $src, $dst", 575 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 576 577// Convert Floating-point to Integer Instructions, p. 142 578def FSTOI : F3_3<2, 0b110100, 0b011010001, 579 (outs FPRegs:$dst), (ins FPRegs:$src), 580 "fstoi $src, $dst", 581 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 582def FDTOI : F3_3<2, 0b110100, 0b011010010, 583 (outs FPRegs:$dst), (ins DFPRegs:$src), 584 "fdtoi $src, $dst", 585 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 586 587// Convert between Floating-point Formats Instructions, p. 143 588def FSTOD : F3_3<2, 0b110100, 0b011001001, 589 (outs DFPRegs:$dst), (ins FPRegs:$src), 590 "fstod $src, $dst", 591 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 592def FDTOS : F3_3<2, 0b110100, 0b011000110, 593 (outs FPRegs:$dst), (ins DFPRegs:$src), 594 "fdtos $src, $dst", 595 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 596 597// Floating-point Move Instructions, p. 144 598def FMOVS : F3_3<2, 0b110100, 0b000000001, 599 (outs FPRegs:$dst), (ins FPRegs:$src), 600 "fmovs $src, $dst", []>; 601def FNEGS : F3_3<2, 0b110100, 0b000000101, 602 (outs FPRegs:$dst), (ins FPRegs:$src), 603 "fnegs $src, $dst", 604 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 605def FABSS : F3_3<2, 0b110100, 0b000001001, 606 (outs FPRegs:$dst), (ins FPRegs:$src), 607 "fabss $src, $dst", 608 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 609 610 611// Floating-point Square Root Instructions, p.145 612def FSQRTS : F3_3<2, 0b110100, 0b000101001, 613 (outs FPRegs:$dst), (ins FPRegs:$src), 614 "fsqrts $src, $dst", 615 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 616def FSQRTD : F3_3<2, 0b110100, 0b000101010, 617 (outs DFPRegs:$dst), (ins DFPRegs:$src), 618 "fsqrtd $src, $dst", 619 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 620 621 622 623// Floating-point Add and Subtract Instructions, p. 146 624def FADDS : F3_3<2, 0b110100, 0b001000001, 625 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 626 "fadds $src1, $src2, $dst", 627 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 628def FADDD : F3_3<2, 0b110100, 0b001000010, 629 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 630 "faddd $src1, $src2, $dst", 631 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 632def FSUBS : F3_3<2, 0b110100, 0b001000101, 633 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 634 "fsubs $src1, $src2, $dst", 635 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 636def FSUBD : F3_3<2, 0b110100, 0b001000110, 637 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 638 "fsubd $src1, $src2, $dst", 639 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 640 641// Floating-point Multiply and Divide Instructions, p. 147 642def FMULS : F3_3<2, 0b110100, 0b001001001, 643 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 644 "fmuls $src1, $src2, $dst", 645 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 646def FMULD : F3_3<2, 0b110100, 0b001001010, 647 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 648 "fmuld $src1, $src2, $dst", 649 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 650def FSMULD : F3_3<2, 0b110100, 0b001101001, 651 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 652 "fsmuld $src1, $src2, $dst", 653 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 654 (fextend FPRegs:$src2)))]>; 655def FDIVS : F3_3<2, 0b110100, 0b001001101, 656 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 657 "fdivs $src1, $src2, $dst", 658 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 659def FDIVD : F3_3<2, 0b110100, 0b001001110, 660 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 661 "fdivd $src1, $src2, $dst", 662 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 663 664// Floating-point Compare Instructions, p. 148 665// Note: the 2nd template arg is different for these guys. 666// Note 2: the result of a FCMP is not available until the 2nd cycle 667// after the instr is retired, but there is no interlock. This behavior 668// is modelled with a forced noop after the instruction. 669let Defs = [FCC] in { 670 def FCMPS : F3_3<2, 0b110101, 0b001010001, 671 (outs), (ins FPRegs:$src1, FPRegs:$src2), 672 "fcmps $src1, $src2\n\tnop", 673 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 674 def FCMPD : F3_3<2, 0b110101, 0b001010010, 675 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 676 "fcmpd $src1, $src2\n\tnop", 677 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 678} 679 680//===----------------------------------------------------------------------===// 681// V9 Instructions 682//===----------------------------------------------------------------------===// 683 684// V9 Conditional Moves. 685let Predicates = [HasV9], Constraints = "$T = $dst" in { 686 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 687 // FIXME: Add instruction encodings for the JIT some day. 688 def MOVICCrr 689 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 690 "mov$cc %icc, $F, $dst", 691 [(set IntRegs:$dst, 692 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 693 def MOVICCri 694 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 695 "mov$cc %icc, $F, $dst", 696 [(set IntRegs:$dst, 697 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 698 699 def MOVFCCrr 700 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 701 "mov$cc %fcc0, $F, $dst", 702 [(set IntRegs:$dst, 703 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 704 def MOVFCCri 705 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 706 "mov$cc %fcc0, $F, $dst", 707 [(set IntRegs:$dst, 708 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 709 710 def FMOVS_ICC 711 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 712 "fmovs$cc %icc, $F, $dst", 713 [(set FPRegs:$dst, 714 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 715 def FMOVD_ICC 716 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 717 "fmovd$cc %icc, $F, $dst", 718 [(set DFPRegs:$dst, 719 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 720 def FMOVS_FCC 721 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 722 "fmovs$cc %fcc0, $F, $dst", 723 [(set FPRegs:$dst, 724 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 725 def FMOVD_FCC 726 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 727 "fmovd$cc %fcc0, $F, $dst", 728 [(set DFPRegs:$dst, 729 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 730 731} 732 733// Floating-Point Move Instructions, p. 164 of the V9 manual. 734let Predicates = [HasV9] in { 735 def FMOVD : F3_3<2, 0b110100, 0b000000010, 736 (outs DFPRegs:$dst), (ins DFPRegs:$src), 737 "fmovd $src, $dst", []>; 738 def FNEGD : F3_3<2, 0b110100, 0b000000110, 739 (outs DFPRegs:$dst), (ins DFPRegs:$src), 740 "fnegd $src, $dst", 741 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 742 def FABSD : F3_3<2, 0b110100, 0b000001010, 743 (outs DFPRegs:$dst), (ins DFPRegs:$src), 744 "fabsd $src, $dst", 745 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 746} 747 748// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 749// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 750def POPCrr : F3_1<2, 0b101110, 751 (outs IntRegs:$dst), (ins IntRegs:$src), 752 "popc $src, $dst", []>, Requires<[HasV9]>; 753def : Pat<(ctpop IntRegs:$src), 754 (POPCrr (SLLri IntRegs:$src, 0))>; 755 756//===----------------------------------------------------------------------===// 757// Non-Instruction Patterns 758//===----------------------------------------------------------------------===// 759 760// Small immediates. 761def : Pat<(i32 simm13:$val), 762 (ORri G0, imm:$val)>; 763// Arbitrary immediates. 764def : Pat<(i32 imm:$val), 765 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 766 767// subc 768def : Pat<(subc IntRegs:$b, IntRegs:$c), 769 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 770def : Pat<(subc IntRegs:$b, simm13:$val), 771 (SUBCCri IntRegs:$b, imm:$val)>; 772 773// Global addresses, constant pool entries 774def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 775def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 776def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 777def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 778 779// Add reg, lo. This is used when taking the addr of a global/constpool entry. 780def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 781 (ADDri IntRegs:$r, tglobaladdr:$in)>; 782def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 783 (ADDri IntRegs:$r, tconstpool:$in)>; 784 785// Calls: 786def : Pat<(call tglobaladdr:$dst), 787 (CALL tglobaladdr:$dst)>; 788def : Pat<(call texternalsym:$dst), 789 (CALL texternalsym:$dst)>; 790 791// Map integer extload's to zextloads. 792def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 793def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 794def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 795def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 796def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 797def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 798 799// zextload bool -> zextload byte 800def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 801def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 802