SparcInstrInfo.td revision 9034b883a463b37dbc4766ff7243dac3a27d0b11
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42def LO10 : SDNodeXForm<imm, [{ 43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 44}]>; 45 46def HI22 : SDNodeXForm<imm, [{ 47 // Transformation function: shift the immediate value down into the low bits. 48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 49}]>; 50 51def SETHIimm : PatLeaf<(imm), [{ 52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 53}], HI22>; 54 55// Addressing modes. 56def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 57def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 58 59// Address operands 60def MEMrr : Operand<i32> { 61 let PrintMethod = "printMemOperand"; 62 let NumMIOperands = 2; 63 let MIOperandInfo = (ops IntRegs, IntRegs); 64} 65def MEMri : Operand<i32> { 66 let PrintMethod = "printMemOperand"; 67 let NumMIOperands = 2; 68 let MIOperandInfo = (ops IntRegs, i32imm); 69} 70 71//===----------------------------------------------------------------------===// 72// Instructions 73//===----------------------------------------------------------------------===// 74 75// Pseudo instructions. 76class PseudoInstV8<string asmstr, dag ops> : InstV8 { 77 let AsmString = asmstr; 78 dag OperandList = ops; 79} 80def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 81def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 82 (ops i32imm:$amt)>; 83def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 84 (ops i32imm:$amt)>; 85//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 86def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 87 (ops IntRegs:$dst)>; 88def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 89 90// Section A.3 - Synthetic Instructions, p. 85 91// special cases of JMPL: 92let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 93 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 94 def RETL: F3_2<2, 0b111000, (ops), 95 "retl", [(ret)]>; 96} 97// CMP is a special case of SUBCC where destination is ignored, by setting it to 98// %g0 (hardwired zero). 99// FIXME: should keep track of the fact that it defs the integer condition codes 100let rd = 0 in 101 def CMPri: F3_2<2, 0b010100, 102 (ops IntRegs:$b, i32imm:$c), 103 "cmp $b, $c", []>; 104 105// Section B.1 - Load Integer Instructions, p. 90 106def LDSBrr : F3_1<3, 0b001001, 107 (ops IntRegs:$dst, MEMrr:$addr), 108 "ldsb [$addr], $dst", 109 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 110def LDSBri : F3_2<3, 0b001001, 111 (ops IntRegs:$dst, MEMri:$addr), 112 "ldsb [$addr], $dst", 113 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 114def LDSHrr : F3_1<3, 0b001010, 115 (ops IntRegs:$dst, MEMrr:$addr), 116 "ldsh [$addr], $dst", 117 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 118def LDSHri : F3_2<3, 0b001010, 119 (ops IntRegs:$dst, MEMri:$addr), 120 "ldsh [$addr], $dst", 121 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 122def LDUBrr : F3_1<3, 0b000001, 123 (ops IntRegs:$dst, MEMrr:$addr), 124 "ldub [$addr], $dst", 125 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 126def LDUBri : F3_2<3, 0b000001, 127 (ops IntRegs:$dst, MEMri:$addr), 128 "ldub [$addr], $dst", 129 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 130def LDUHrr : F3_1<3, 0b000010, 131 (ops IntRegs:$dst, MEMrr:$addr), 132 "lduh [$addr], $dst", 133 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 134def LDUHri : F3_2<3, 0b000010, 135 (ops IntRegs:$dst, MEMri:$addr), 136 "lduh [$addr], $dst", 137 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 138def LDrr : F3_1<3, 0b000000, 139 (ops IntRegs:$dst, MEMrr:$addr), 140 "ld [$addr], $dst", 141 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 142def LDri : F3_2<3, 0b000000, 143 (ops IntRegs:$dst, MEMri:$addr), 144 "ld [$addr], $dst", 145 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 146def LDDrr : F3_1<3, 0b000011, 147 (ops IntRegs:$dst, MEMrr:$addr), 148 "ldd [$addr], $dst", []>; 149def LDDri : F3_2<3, 0b000011, 150 (ops IntRegs:$dst, MEMri:$addr), 151 "ldd [$addr], $dst", []>; 152 153// Section B.2 - Load Floating-point Instructions, p. 92 154def LDFrr : F3_1<3, 0b100000, 155 (ops FPRegs:$dst, MEMrr:$addr), 156 "ld [$addr], $dst", 157 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 158def LDFri : F3_2<3, 0b100000, 159 (ops FPRegs:$dst, MEMri:$addr), 160 "ld [$addr], $dst", 161 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 162def LDDFrr : F3_1<3, 0b100011, 163 (ops DFPRegs:$dst, MEMrr:$addr), 164 "ldd [$addr], $dst", 165 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 166def LDDFri : F3_2<3, 0b100011, 167 (ops DFPRegs:$dst, MEMri:$addr), 168 "ldd [$addr], $dst", 169 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 170 171// Section B.4 - Store Integer Instructions, p. 95 172def STBrr : F3_1<3, 0b000101, 173 (ops MEMrr:$addr, IntRegs:$src), 174 "stb $src, [$addr]", 175 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 176def STBri : F3_2<3, 0b000101, 177 (ops MEMri:$addr, IntRegs:$src), 178 "stb $src, [$addr]", 179 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 180def STHrr : F3_1<3, 0b000110, 181 (ops MEMrr:$addr, IntRegs:$src), 182 "sth $src, [$addr]", 183 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 184def STHri : F3_2<3, 0b000110, 185 (ops MEMri:$addr, IntRegs:$src), 186 "sth $src, [$addr]", 187 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 188def STrr : F3_1<3, 0b000100, 189 (ops MEMrr:$addr, IntRegs:$src), 190 "st $src, [$addr]", 191 [(store IntRegs:$src, ADDRrr:$addr)]>; 192def STri : F3_2<3, 0b000100, 193 (ops MEMri:$addr, IntRegs:$src), 194 "st $src, [$addr]", 195 [(store IntRegs:$src, ADDRri:$addr)]>; 196def STDrr : F3_1<3, 0b000111, 197 (ops MEMrr:$addr, IntRegs:$src), 198 "std $src, [$addr]", []>; 199def STDri : F3_2<3, 0b000111, 200 (ops MEMri:$addr, IntRegs:$src), 201 "std $src, [$addr]", []>; 202 203// Section B.5 - Store Floating-point Instructions, p. 97 204def STFrr : F3_1<3, 0b100100, 205 (ops MEMrr:$addr, FPRegs:$src), 206 "st $src, [$addr]", 207 [(store FPRegs:$src, ADDRrr:$addr)]>; 208def STFri : F3_2<3, 0b100100, 209 (ops MEMri:$addr, FPRegs:$src), 210 "st $src, [$addr]", 211 [(store FPRegs:$src, ADDRri:$addr)]>; 212def STDFrr : F3_1<3, 0b100111, 213 (ops MEMrr:$addr, DFPRegs:$src), 214 "std $src, [$addr]", 215 [(store DFPRegs:$src, ADDRrr:$addr)]>; 216def STDFri : F3_2<3, 0b100111, 217 (ops MEMri:$addr, DFPRegs:$src), 218 "std $src, [$addr]", 219 [(store DFPRegs:$src, ADDRri:$addr)]>; 220 221// Section B.9 - SETHI Instruction, p. 104 222def SETHIi: F2_1<0b100, 223 (ops IntRegs:$dst, i32imm:$src), 224 "sethi $src, $dst", 225 [(set IntRegs:$dst, SETHIimm:$src)]>; 226 227// Section B.10 - NOP Instruction, p. 105 228// (It's a special case of SETHI) 229let rd = 0, imm22 = 0 in 230 def NOP : F2_1<0b100, (ops), "nop", []>; 231 232// Section B.11 - Logical Instructions, p. 106 233def ANDrr : F3_1<2, 0b000001, 234 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 235 "and $b, $c, $dst", 236 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 237def ANDri : F3_2<2, 0b000001, 238 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 239 "and $b, $c, $dst", 240 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 241def ANDNrr : F3_1<2, 0b000101, 242 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 243 "andn $b, $c, $dst", 244 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 245def ANDNri : F3_2<2, 0b000101, 246 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 247 "andn $b, $c, $dst", []>; 248def ORrr : F3_1<2, 0b000010, 249 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 250 "or $b, $c, $dst", 251 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 252def ORri : F3_2<2, 0b000010, 253 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 254 "or $b, $c, $dst", 255 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 256def ORNrr : F3_1<2, 0b000110, 257 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 258 "orn $b, $c, $dst", 259 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 260def ORNri : F3_2<2, 0b000110, 261 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 262 "orn $b, $c, $dst", []>; 263def XORrr : F3_1<2, 0b000011, 264 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 265 "xor $b, $c, $dst", 266 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 267def XORri : F3_2<2, 0b000011, 268 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 269 "xor $b, $c, $dst", 270 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 271def XNORrr : F3_1<2, 0b000111, 272 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 273 "xnor $b, $c, $dst", 274 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>; 275def XNORri : F3_2<2, 0b000111, 276 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 277 "xnor $b, $c, $dst", []>; 278 279// Section B.12 - Shift Instructions, p. 107 280def SLLrr : F3_1<2, 0b100101, 281 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 282 "sll $b, $c, $dst", 283 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 284def SLLri : F3_2<2, 0b100101, 285 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 286 "sll $b, $c, $dst", 287 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 288def SRLrr : F3_1<2, 0b100110, 289 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 290 "srl $b, $c, $dst", 291 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 292def SRLri : F3_2<2, 0b100110, 293 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 294 "srl $b, $c, $dst", 295 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 296def SRArr : F3_1<2, 0b100111, 297 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 298 "sra $b, $c, $dst", 299 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 300def SRAri : F3_2<2, 0b100111, 301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 302 "sra $b, $c, $dst", 303 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 304 305// Section B.13 - Add Instructions, p. 108 306def ADDrr : F3_1<2, 0b000000, 307 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 308 "add $b, $c, $dst", 309 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 310def ADDri : F3_2<2, 0b000000, 311 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 312 "add $b, $c, $dst", 313 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 314def ADDCCrr : F3_1<2, 0b010000, 315 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 316 "addcc $b, $c, $dst", []>; 317def ADDCCri : F3_2<2, 0b010000, 318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 319 "addcc $b, $c, $dst", []>; 320def ADDXrr : F3_1<2, 0b001000, 321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 322 "addx $b, $c, $dst", []>; 323def ADDXri : F3_2<2, 0b001000, 324 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 325 "addx $b, $c, $dst", []>; 326 327// Section B.15 - Subtract Instructions, p. 110 328def SUBrr : F3_1<2, 0b000100, 329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 330 "sub $b, $c, $dst", 331 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 332def SUBri : F3_2<2, 0b000100, 333 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 334 "sub $b, $c, $dst", 335 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 336def SUBXrr : F3_1<2, 0b001100, 337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 338 "subx $b, $c, $dst", []>; 339def SUBXri : F3_2<2, 0b001100, 340 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 341 "subx $b, $c, $dst", []>; 342def SUBCCrr : F3_1<2, 0b010100, 343 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 344 "subcc $b, $c, $dst", []>; 345def SUBCCri : F3_2<2, 0b010100, 346 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 347 "subcc $b, $c, $dst", []>; 348def SUBXCCrr: F3_1<2, 0b011100, 349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 350 "subxcc $b, $c, $dst", []>; 351 352// Section B.18 - Multiply Instructions, p. 113 353def UMULrr : F3_1<2, 0b001010, 354 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 355 "umul $b, $c, $dst", []>; 356def UMULri : F3_2<2, 0b001010, 357 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 358 "umul $b, $c, $dst", []>; 359def SMULrr : F3_1<2, 0b001011, 360 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 361 "smul $b, $c, $dst", []>; 362def SMULri : F3_2<2, 0b001011, 363 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 364 "smul $b, $c, $dst", []>; 365 366// Section B.19 - Divide Instructions, p. 115 367def UDIVrr : F3_1<2, 0b001110, 368 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 369 "udiv $b, $c, $dst", []>; 370def UDIVri : F3_2<2, 0b001110, 371 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 372 "udiv $b, $c, $dst", []>; 373def SDIVrr : F3_1<2, 0b001111, 374 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 375 "sdiv $b, $c, $dst", []>; 376def SDIVri : F3_2<2, 0b001111, 377 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 378 "sdiv $b, $c, $dst", []>; 379 380// Section B.20 - SAVE and RESTORE, p. 117 381def SAVErr : F3_1<2, 0b111100, 382 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 383 "save $b, $c, $dst", []>; 384def SAVEri : F3_2<2, 0b111100, 385 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 386 "save $b, $c, $dst", []>; 387def RESTORErr : F3_1<2, 0b111101, 388 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 389 "restore $b, $c, $dst", []>; 390def RESTOREri : F3_2<2, 0b111101, 391 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 392 "restore $b, $c, $dst", []>; 393 394// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 395 396// conditional branch class: 397class BranchV8<bits<4> cc, dag ops, string asmstr> 398 : F2_2<cc, 0b010, ops, asmstr> { 399 let isBranch = 1; 400 let isTerminator = 1; 401 let hasDelaySlot = 1; 402} 403 404let isBarrier = 1 in 405 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">; 406def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">; 407def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">; 408def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">; 409def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">; 410def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">; 411def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">; 412def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">; 413def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">; 414def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">; 415def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">; 416def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">; 417 418// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 419 420// floating-point conditional branch class: 421class FPBranchV8<bits<4> cc, dag ops, string asmstr> 422 : F2_2<cc, 0b110, ops, asmstr> { 423 let isBranch = 1; 424 let isTerminator = 1; 425 let hasDelaySlot = 1; 426} 427 428def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">; 429def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">; 430def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">; 431def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">; 432def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">; 433def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">; 434def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">; 435def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">; 436def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">; 437def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">; 438def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">; 439def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">; 440def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">; 441def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">; 442def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">; 443def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">; 444 445 446 447// Section B.24 - Call and Link Instruction, p. 125 448// This is the only Format 1 instruction 449let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 450 // pc-relative call: 451 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 452 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 453 def CALL : InstV8 { 454 let OperandList = (ops IntRegs:$dst); 455 bits<30> disp; 456 let op = 1; 457 let Inst{29-0} = disp; 458 let AsmString = "call $dst"; 459 } 460 461 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 462 // be an implicit def): 463 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 464 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 465 def JMPLrr : F3_1<2, 0b111000, 466 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 467 "jmpl $b+$c, $dst", []>; 468} 469 470// Section B.29 - Write State Register Instructions 471def WRrr : F3_1<2, 0b110000, 472 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 473 "wr $b, $c, $dst", []>; 474def WRri : F3_2<2, 0b110000, 475 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 476 "wr $b, $c, $dst", []>; 477 478// Convert Integer to Floating-point Instructions, p. 141 479def FITOS : F3_3<2, 0b110100, 0b011000100, 480 (ops FPRegs:$dst, FPRegs:$src), 481 "fitos $src, $dst">; 482def FITOD : F3_3<2, 0b110100, 0b011001000, 483 (ops DFPRegs:$dst, DFPRegs:$src), 484 "fitod $src, $dst">; 485 486// Convert Floating-point to Integer Instructions, p. 142 487def FSTOI : F3_3<2, 0b110100, 0b011010001, 488 (ops FPRegs:$dst, FPRegs:$src), 489 "fstoi $src, $dst">; 490def FDTOI : F3_3<2, 0b110100, 0b011010010, 491 (ops DFPRegs:$dst, DFPRegs:$src), 492 "fdtoi $src, $dst">; 493 494// Convert between Floating-point Formats Instructions, p. 143 495def FSTOD : F3_3<2, 0b110100, 0b011001001, 496 (ops DFPRegs:$dst, FPRegs:$src), 497 "fstod $src, $dst">; 498def FDTOS : F3_3<2, 0b110100, 0b011000110, 499 (ops FPRegs:$dst, DFPRegs:$src), 500 "fdtos $src, $dst">; 501 502// Floating-point Move Instructions, p. 144 503def FMOVS : F3_3<2, 0b110100, 0b000000001, 504 (ops FPRegs:$dst, FPRegs:$src), 505 "fmovs $src, $dst">; 506def FNEGS : F3_3<2, 0b110100, 0b000000101, 507 (ops FPRegs:$dst, FPRegs:$src), 508 "fnegs $src, $dst">; 509def FABSS : F3_3<2, 0b110100, 0b000001001, 510 (ops FPRegs:$dst, FPRegs:$src), 511 "fabss $src, $dst">; 512 513// Floating-point Add and Subtract Instructions, p. 146 514def FADDS : F3_3<2, 0b110100, 0b001000001, 515 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 516 "fadds $src1, $src2, $dst">; 517def FADDD : F3_3<2, 0b110100, 0b001000010, 518 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 519 "faddd $src1, $src2, $dst">; 520def FSUBS : F3_3<2, 0b110100, 0b001000101, 521 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 522 "fsubs $src1, $src2, $dst">; 523def FSUBD : F3_3<2, 0b110100, 0b001000110, 524 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 525 "fsubd $src1, $src2, $dst">; 526 527// Floating-point Multiply and Divide Instructions, p. 147 528def FMULS : F3_3<2, 0b110100, 0b001001001, 529 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 530 "fmuls $src1, $src2, $dst">; 531def FMULD : F3_3<2, 0b110100, 0b001001010, 532 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 533 "fmuld $src1, $src2, $dst">; 534def FSMULD : F3_3<2, 0b110100, 0b001101001, 535 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 536 "fsmuld $src1, $src2, $dst">; 537def FDIVS : F3_3<2, 0b110100, 0b001001101, 538 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 539 "fdivs $src1, $src2, $dst">; 540def FDIVD : F3_3<2, 0b110100, 0b001001110, 541 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 542 "fdivd $src1, $src2, $dst">; 543 544// Floating-point Compare Instructions, p. 148 545// Note: the 2nd template arg is different for these guys. 546// Note 2: the result of a FCMP is not available until the 2nd cycle 547// after the instr is retired, but there is no interlock. This behavior 548// is modelled with a forced noop after the instruction. 549def FCMPS : F3_3<2, 0b110101, 0b001010001, 550 (ops FPRegs:$src1, FPRegs:$src2), 551 "fcmps $src1, $src2\n\tnop">; 552def FCMPD : F3_3<2, 0b110101, 0b001010010, 553 (ops DFPRegs:$src1, DFPRegs:$src2), 554 "fcmpd $src1, $src2\n\tnop">; 555 556//===----------------------------------------------------------------------===// 557// Non-Instruction Patterns 558//===----------------------------------------------------------------------===// 559 560// Small immediates. 561def : Pat<(i32 simm13:$val), 562 (ORri G0, imm:$val)>; 563// Arbitrary immediates. 564def : Pat<(i32 imm:$val), 565 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 566