SparcInstrInfo.td revision 96b84beb77d5209d2d5db4db9a6dc07461de2f7e
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm, dag ops> : InstV8 { 39 let Name = nm; 40 dag OperandList = ops; 41} 42def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 43def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN", (ops variable_ops)>; 44def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP", (ops variable_ops)>; 45def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE", (ops variable_ops)>; 46def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF", (ops variable_ops)>; 47def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move 48 49// Section A.3 - Synthetic Instructions, p. 85 50// special cases of JMPL: 51let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 52 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 53 def RET : F3_2<2, 0b111000, 54 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ret">; 55 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 56 def RETL: F3_2<2, 0b111000, 57 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "retl">; 58} 59// CMP is a special case of SUBCC where destination is ignored, by setting it to 60// %g0 (hardwired zero). 61// FIXME: should keep track of the fact that it defs the integer condition codes 62let rd = 0 in 63 def CMPri: F3_2<2, 0b010100, 64 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "cmp">; 65 66// Section B.1 - Load Integer Instructions, p. 90 67def LDSB: F3_2<3, 0b001001, 68 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldsb">; 69def LDSH: F3_2<3, 0b001010, 70 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldsh">; 71def LDUB: F3_2<3, 0b000001, 72 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldub">; 73def LDUH: F3_2<3, 0b000010, 74 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "lduh">; 75def LD : F3_2<3, 0b000000, 76 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">; 77def LDD : F3_2<3, 0b000011, 78 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldd">; 79 80// Section B.2 - Load Floating-point Instructions, p. 92 81def LDFrr : F3_1<3, 0b100000, 82 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ld">; 83def LDFri : F3_2<3, 0b100000, 84 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">; 85def LDDFrr : F3_1<3, 0b100011, 86 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ldd">; 87def LDDFri : F3_2<3, 0b100011, 88 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldd">; 89def LDFSRrr: F3_1<3, 0b100001, 90 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ld">; 91def LDFSRri: F3_2<3, 0b100001, 92 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">; 93 94// Section B.4 - Store Integer Instructions, p. 95 95def STB : F3_2<3, 0b000101, 96 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "stb">; 97def STH : F3_2<3, 0b000110, 98 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sth">; 99def ST : F3_2<3, 0b000100, 100 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">; 101def STD : F3_2<3, 0b000111, 102 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">; 103 104// Section B.5 - Store Floating-point Instructions, p. 97 105def STFrr : F3_1<3, 0b100100, 106 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "st">; 107def STFri : F3_2<3, 0b100100, 108 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">; 109def STDFrr : F3_1<3, 0b100111, 110 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "std">; 111def STDFri : F3_2<3, 0b100111, 112 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">; 113def STFSRrr : F3_1<3, 0b100101, 114 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "st">; 115def STFSRri : F3_2<3, 0b100101, 116 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">; 117def STDFQrr : F3_1<3, 0b100110, 118 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "std">; 119def STDFQri : F3_2<3, 0b100110, 120 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">; 121 122// Section B.9 - SETHI Instruction, p. 104 123def SETHIi: F2_1<0b100, "sethi">; 124 125// Section B.10 - NOP Instruction, p. 105 126// (It's a special case of SETHI) 127let rd = 0, imm22 = 0 in 128 def NOP : F2_1<0b100, "nop">; 129 130// Section B.11 - Logical Instructions, p. 106 131def ANDrr : F3_1<2, 0b000001, 132 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "and">; 133def ANDri : F3_2<2, 0b000001, 134 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "and">; 135def ANDCCrr : F3_1<2, 0b010001, 136 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andcc">; 137def ANDCCri : F3_2<2, 0b010001, 138 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andcc">; 139def ANDNrr : F3_1<2, 0b000101, 140 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andn">; 141def ANDNri : F3_2<2, 0b000101, 142 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andn">; 143def ANDNCCrr: F3_1<2, 0b010101, 144 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andncc">; 145def ANDNCCri: F3_2<2, 0b010101, 146 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andncc">; 147def ORrr : F3_1<2, 0b000010, 148 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "or">; 149def ORri : F3_2<2, 0b000010, 150 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "or">; 151def ORCCrr : F3_1<2, 0b010010, 152 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orcc">; 153def ORCCri : F3_2<2, 0b010010, 154 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orcc">; 155def ORNrr : F3_1<2, 0b000110, 156 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orn">; 157def ORNri : F3_2<2, 0b000110, 158 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orn">; 159def ORNCCrr : F3_1<2, 0b010110, 160 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orncc">; 161def ORNCCri : F3_2<2, 0b010110, 162 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orncc">; 163def XORrr : F3_1<2, 0b000011, 164 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xor">; 165def XORri : F3_2<2, 0b000011, 166 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xor">; 167def XORCCrr : F3_1<2, 0b010011, 168 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xorcc">; 169def XORCCri : F3_2<2, 0b010011, 170 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xorcc">; 171def XNORrr : F3_1<2, 0b000111, 172 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xnor">; 173def XNORri : F3_2<2, 0b000111, 174 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xnor">; 175def XNORCCrr: F3_1<2, 0b010111, 176 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xnorcc">; 177def XNORCCri: F3_2<2, 0b010111, 178 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xnorcc">; 179 180// Section B.12 - Shift Instructions, p. 107 181def SLLrr : F3_1<2, 0b100101, 182 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sll">; 183def SLLri : F3_2<2, 0b100101, 184 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sll">; 185def SRLrr : F3_1<2, 0b100110, 186 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "srl">; 187def SRLri : F3_2<2, 0b100110, 188 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "srl">; 189def SRArr : F3_1<2, 0b100111, 190 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sra">; 191def SRAri : F3_2<2, 0b100111, 192 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sra">; 193 194// Section B.13 - Add Instructions, p. 108 195def ADDrr : F3_1<2, 0b000000, 196 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "add">; 197def ADDri : F3_2<2, 0b000000, 198 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "add">; 199def ADDCCrr : F3_1<2, 0b010000, 200 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addcc">; 201def ADDCCri : F3_2<2, 0b010000, 202 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addcc">; 203def ADDXrr : F3_1<2, 0b001000, 204 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addx">; 205def ADDXri : F3_2<2, 0b001000, 206 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addx">; 207def ADDXCCrr: F3_1<2, 0b011000, 208 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addxcc">; 209def ADDXCCri: F3_2<2, 0b011000, 210 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addxcc">; 211 212// Section B.15 - Subtract Instructions, p. 110 213def SUBrr : F3_1<2, 0b000100, 214 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sub">; 215def SUBri : F3_2<2, 0b000100, 216 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sub">; 217def SUBCCrr : F3_1<2, 0b010100, 218 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subcc">; 219def SUBCCri : F3_2<2, 0b010100, 220 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subcc">; 221def SUBXrr : F3_1<2, 0b001100, 222 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subx">; 223def SUBXri : F3_2<2, 0b001100, 224 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subx">; 225def SUBXCCrr: F3_1<2, 0b011100, 226 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subxcc">; 227def SUBXCCri: F3_2<2, 0b011100, 228 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subxcc">; 229 230// Section B.18 - Multiply Instructions, p. 113 231def UMULrr : F3_1<2, 0b001010, 232 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "umul">; 233def UMULri : F3_2<2, 0b001010, 234 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "umul">; 235def SMULrr : F3_1<2, 0b001011, 236 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "smul">; 237def SMULri : F3_2<2, 0b001011, 238 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "smul">; 239def UMULCCrr: F3_1<2, 0b011010, 240 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "umulcc">; 241def UMULCCri: F3_2<2, 0b011010, 242 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "umulcc">; 243def SMULCCrr: F3_1<2, 0b011011, 244 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "smulcc">; 245def SMULCCri: F3_2<2, 0b011011, 246 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "smulcc">; 247 248// Section B.19 - Divide Instructions, p. 115 249def UDIVrr : F3_1<2, 0b001110, 250 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "udiv">; 251def UDIVri : F3_2<2, 0b001110, 252 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "udiv">; 253def SDIVrr : F3_1<2, 0b001111, 254 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sdiv">; 255def SDIVri : F3_2<2, 0b001111, 256 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sdiv">; 257def UDIVCCrr : F3_1<2, 0b011110, 258 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "udivcc">; 259def UDIVCCri : F3_2<2, 0b011110, 260 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "udivcc">; 261def SDIVCCrr : F3_1<2, 0b011111, 262 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sdivcc">; 263def SDIVCCri : F3_2<2, 0b011111, 264 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sdivcc">; 265 266// Section B.20 - SAVE and RESTORE, p. 117 267def SAVErr : F3_1<2, 0b111100, 268 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "save">; 269def SAVEri : F3_2<2, 0b111100, 270 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "save">; 271def RESTORErr : F3_1<2, 0b111101, 272 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "restore">; 273def RESTOREri : F3_2<2, 0b111101, 274 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "restore">; 275 276// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 277 278// conditional branch class: 279class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 280 let isBranch = 1; 281 let isTerminator = 1; 282 let hasDelaySlot = 1; 283} 284 285let isBarrier = 1 in 286 def BA : BranchV8<0b1000, "ba">; 287def BN : BranchV8<0b0000, "bn">; 288def BNE : BranchV8<0b1001, "bne">; 289def BE : BranchV8<0b0001, "be">; 290def BG : BranchV8<0b1010, "bg">; 291def BLE : BranchV8<0b0010, "ble">; 292def BGE : BranchV8<0b1011, "bge">; 293def BL : BranchV8<0b0011, "bl">; 294def BGU : BranchV8<0b1100, "bgu">; 295def BLEU : BranchV8<0b0100, "bleu">; 296def BCC : BranchV8<0b1101, "bcc">; 297def BCS : BranchV8<0b0101, "bcs">; 298 299// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 300 301// floating-point conditional branch class: 302class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 303 let isBranch = 1; 304 let isTerminator = 1; 305 let hasDelaySlot = 1; 306} 307 308def FBA : FPBranchV8<0b1000, "fba">; 309def FBN : FPBranchV8<0b0000, "fbn">; 310def FBU : FPBranchV8<0b0111, "fbu">; 311def FBG : FPBranchV8<0b0110, "fbg">; 312def FBUG : FPBranchV8<0b0101, "fbug">; 313def FBL : FPBranchV8<0b0100, "fbl">; 314def FBUL : FPBranchV8<0b0011, "fbul">; 315def FBLG : FPBranchV8<0b0010, "fblg">; 316def FBNE : FPBranchV8<0b0001, "fbne">; 317def FBE : FPBranchV8<0b1001, "fbe">; 318def FBUE : FPBranchV8<0b1010, "fbue">; 319def FBGE : FPBranchV8<0b1011, "fbge">; 320def FBUGE: FPBranchV8<0b1100, "fbuge">; 321def FBLE : FPBranchV8<0b1101, "fble">; 322def FBULE: FPBranchV8<0b1110, "fbule">; 323def FBO : FPBranchV8<0b1111, "fbo">; 324 325 326 327// Section B.24 - Call and Link Instruction, p. 125 328// This is the only Format 1 instruction 329let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 330 // pc-relative call: 331 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 332 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 333 def CALL : InstV8 { 334 bits<30> disp; 335 let op = 1; 336 let Inst{29-0} = disp; 337 let Name = "call"; 338 } 339 340 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 341 // be an implicit def): 342 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 343 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 344 def JMPLrr : F3_1<2, 0b111000, (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "jmpl">; 345 // jmpl [rs1+rs2], rd 346} 347 348// Section B.29 - Write State Register Instructions 349def WRrr : F3_1<2, 0b110000, 350 (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "wr">; 351def WRri : F3_2<2, 0b110000, 352 (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "wr">; // wr rs1, imm, rd 353 354// Convert Integer to Floating-point Instructions, p. 141 355def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 356def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">; 357 358// Convert Floating-point to Integer Instructions, p. 142 359def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">; 360def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">; 361 362// Convert between Floating-point Formats Instructions, p. 143 363def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 364def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 365 366// Floating-point Move Instructions, p. 144 367def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 368def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 369def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 370 371// Floating-point Add and Subtract Instructions, p. 146 372def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 373def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 374def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 375def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 376 377// Floating-point Multiply and Divide Instructions, p. 147 378def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 379def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 380def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 381def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 382def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 383 384// Floating-point Compare Instructions, p. 148 385// Note: the 2nd template arg is different for these guys. 386// Note 2: the result of a FCMP is not available until the 2nd cycle 387// after the instr is retired, but there is no interlock. This behavior 388// is modelled as a delay slot. 389let hasDelaySlot = 1 in { 390 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 391 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 392 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 393 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 394} 395 396