SparcInstrInfo.td revision c178308b23f796b6f5c15c8b3f742cc7b3336d6b
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 47 48def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 49 50def LO10 : SDNodeXForm<imm, [{ 51 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 52 MVT::i32); 53}]>; 54 55def HI22 : SDNodeXForm<imm, [{ 56 // Transformation function: shift the immediate value down into the low bits. 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 58}]>; 59 60def SETHIimm : PatLeaf<(imm), [{ 61 return (((unsigned)N->getZExtValue() >> 10) << 10) == 62 (unsigned)N->getZExtValue(); 63}], HI22>; 64 65// Addressing modes. 66def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 67def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 68 69// Address operands 70def MEMrr : Operand<i32> { 71 let PrintMethod = "printMemOperand"; 72 let MIOperandInfo = (ops IntRegs, IntRegs); 73} 74def MEMri : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, i32imm); 77} 78 79// Branch targets have OtherVT type. 80def brtarget : Operand<OtherVT>; 81def calltarget : Operand<i32>; 82 83// Operand for printing out a condition code. 84let PrintMethod = "printCCOperand" in 85 def CCOp : Operand<i32>; 86 87def SDTSPcmpfcc : 88SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 89def SDTSPbrcc : 90SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 91def SDTSPselectcc : 92SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 93def SDTSPFTOI : 94SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 95def SDTSPITOF : 96SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 97 98def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>; 99def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 100def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 101def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 102 103def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 104def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 105 106def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 107def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 108 109def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 110def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 111 112// These are target-independent nodes, but have target-specific formats. 113def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 114def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 115 SDTCisVT<1, i32> ]>; 116 117def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 118 [SDNPHasChain, SDNPOutGlue]>; 119def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 121 122def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 123def call : SDNode<"SPISD::CALL", SDT_SPCall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 125 SDNPVariadic]>; 126 127def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 128 [SDNPHasChain, SDNPOptInGlue]>; 129 130def getPCX : Operand<i32> { 131 let PrintMethod = "printGetPCX"; 132} 133 134//===----------------------------------------------------------------------===// 135// SPARC Flag Conditions 136//===----------------------------------------------------------------------===// 137 138// Note that these values must be kept in sync with the CCOp::CondCode enum 139// values. 140class ICC_VAL<int N> : PatLeaf<(i32 N)>; 141def ICC_NE : ICC_VAL< 9>; // Not Equal 142def ICC_E : ICC_VAL< 1>; // Equal 143def ICC_G : ICC_VAL<10>; // Greater 144def ICC_LE : ICC_VAL< 2>; // Less or Equal 145def ICC_GE : ICC_VAL<11>; // Greater or Equal 146def ICC_L : ICC_VAL< 3>; // Less 147def ICC_GU : ICC_VAL<12>; // Greater Unsigned 148def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 149def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 150def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 151def ICC_POS : ICC_VAL<14>; // Positive 152def ICC_NEG : ICC_VAL< 6>; // Negative 153def ICC_VC : ICC_VAL<15>; // Overflow Clear 154def ICC_VS : ICC_VAL< 7>; // Overflow Set 155 156class FCC_VAL<int N> : PatLeaf<(i32 N)>; 157def FCC_U : FCC_VAL<23>; // Unordered 158def FCC_G : FCC_VAL<22>; // Greater 159def FCC_UG : FCC_VAL<21>; // Unordered or Greater 160def FCC_L : FCC_VAL<20>; // Less 161def FCC_UL : FCC_VAL<19>; // Unordered or Less 162def FCC_LG : FCC_VAL<18>; // Less or Greater 163def FCC_NE : FCC_VAL<17>; // Not Equal 164def FCC_E : FCC_VAL<25>; // Equal 165def FCC_UE : FCC_VAL<24>; // Unordered or Equal 166def FCC_GE : FCC_VAL<25>; // Greater or Equal 167def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 168def FCC_LE : FCC_VAL<27>; // Less or Equal 169def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 170def FCC_O : FCC_VAL<29>; // Ordered 171 172//===----------------------------------------------------------------------===// 173// Instruction Class Templates 174//===----------------------------------------------------------------------===// 175 176/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 177multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 178 def rr : F3_1<2, Op3Val, 179 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 180 !strconcat(OpcStr, " $b, $c, $dst"), 181 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 182 def ri : F3_2<2, Op3Val, 183 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 184 !strconcat(OpcStr, " $b, $c, $dst"), 185 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 186} 187 188/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 189/// pattern. 190multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 191 def rr : F3_1<2, Op3Val, 192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 193 !strconcat(OpcStr, " $b, $c, $dst"), []>; 194 def ri : F3_2<2, Op3Val, 195 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 196 !strconcat(OpcStr, " $b, $c, $dst"), []>; 197} 198 199//===----------------------------------------------------------------------===// 200// Instructions 201//===----------------------------------------------------------------------===// 202 203// Pseudo instructions. 204class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 205 : InstSP<outs, ins, asmstr, pattern>; 206 207// GETPCX for PIC 208let Defs = [O7] in { 209 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 210} 211 212let Defs = [O6], Uses = [O6] in { 213def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 214 "!ADJCALLSTACKDOWN $amt", 215 [(callseq_start timm:$amt)]>; 216def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 217 "!ADJCALLSTACKUP $amt1", 218 [(callseq_end timm:$amt1, timm:$amt2)]>; 219} 220 221// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 222// fpmover pass. 223let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 224 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 225 "!FpMOVD $src, $dst", []>; 226 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 227 "!FpNEGD $src, $dst", 228 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 229 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 230 "!FpABSD $src, $dst", 231 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 232} 233 234// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 235// instruction selection into a branch sequence. This has to handle all 236// permutations of selection between i32/f32/f64 on ICC and FCC. 237 // Expanded after instruction selection. 238let Uses = [ICC], usesCustomInserter = 1 in { 239 def SELECT_CC_Int_ICC 240 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 241 "; SELECT_CC_Int_ICC PSEUDO!", 242 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 243 imm:$Cond))]>; 244 def SELECT_CC_FP_ICC 245 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 246 "; SELECT_CC_FP_ICC PSEUDO!", 247 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 248 imm:$Cond))]>; 249 250 def SELECT_CC_DFP_ICC 251 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 252 "; SELECT_CC_DFP_ICC PSEUDO!", 253 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 254 imm:$Cond))]>; 255} 256 257let usesCustomInserter = 1, Uses = [FCC] in { 258 259 def SELECT_CC_Int_FCC 260 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 261 "; SELECT_CC_Int_FCC PSEUDO!", 262 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 263 imm:$Cond))]>; 264 265 def SELECT_CC_FP_FCC 266 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 267 "; SELECT_CC_FP_FCC PSEUDO!", 268 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 269 imm:$Cond))]>; 270 def SELECT_CC_DFP_FCC 271 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 272 "; SELECT_CC_DFP_FCC PSEUDO!", 273 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 274 imm:$Cond))]>; 275} 276 277 278// Section A.3 - Synthetic Instructions, p. 85 279// special cases of JMPL: 280let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 281 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 282 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 283} 284 285// Section B.1 - Load Integer Instructions, p. 90 286def LDSBrr : F3_1<3, 0b001001, 287 (outs IntRegs:$dst), (ins MEMrr:$addr), 288 "ldsb [$addr], $dst", 289 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 290def LDSBri : F3_2<3, 0b001001, 291 (outs IntRegs:$dst), (ins MEMri:$addr), 292 "ldsb [$addr], $dst", 293 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 294def LDSHrr : F3_1<3, 0b001010, 295 (outs IntRegs:$dst), (ins MEMrr:$addr), 296 "ldsh [$addr], $dst", 297 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 298def LDSHri : F3_2<3, 0b001010, 299 (outs IntRegs:$dst), (ins MEMri:$addr), 300 "ldsh [$addr], $dst", 301 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 302def LDUBrr : F3_1<3, 0b000001, 303 (outs IntRegs:$dst), (ins MEMrr:$addr), 304 "ldub [$addr], $dst", 305 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 306def LDUBri : F3_2<3, 0b000001, 307 (outs IntRegs:$dst), (ins MEMri:$addr), 308 "ldub [$addr], $dst", 309 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 310def LDUHrr : F3_1<3, 0b000010, 311 (outs IntRegs:$dst), (ins MEMrr:$addr), 312 "lduh [$addr], $dst", 313 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 314def LDUHri : F3_2<3, 0b000010, 315 (outs IntRegs:$dst), (ins MEMri:$addr), 316 "lduh [$addr], $dst", 317 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 318def LDrr : F3_1<3, 0b000000, 319 (outs IntRegs:$dst), (ins MEMrr:$addr), 320 "ld [$addr], $dst", 321 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 322def LDri : F3_2<3, 0b000000, 323 (outs IntRegs:$dst), (ins MEMri:$addr), 324 "ld [$addr], $dst", 325 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 326 327// Section B.2 - Load Floating-point Instructions, p. 92 328def LDFrr : F3_1<3, 0b100000, 329 (outs FPRegs:$dst), (ins MEMrr:$addr), 330 "ld [$addr], $dst", 331 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 332def LDFri : F3_2<3, 0b100000, 333 (outs FPRegs:$dst), (ins MEMri:$addr), 334 "ld [$addr], $dst", 335 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 336def LDDFrr : F3_1<3, 0b100011, 337 (outs DFPRegs:$dst), (ins MEMrr:$addr), 338 "ldd [$addr], $dst", 339 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 340def LDDFri : F3_2<3, 0b100011, 341 (outs DFPRegs:$dst), (ins MEMri:$addr), 342 "ldd [$addr], $dst", 343 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 344 345// Section B.4 - Store Integer Instructions, p. 95 346def STBrr : F3_1<3, 0b000101, 347 (outs), (ins MEMrr:$addr, IntRegs:$src), 348 "stb $src, [$addr]", 349 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 350def STBri : F3_2<3, 0b000101, 351 (outs), (ins MEMri:$addr, IntRegs:$src), 352 "stb $src, [$addr]", 353 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 354def STHrr : F3_1<3, 0b000110, 355 (outs), (ins MEMrr:$addr, IntRegs:$src), 356 "sth $src, [$addr]", 357 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 358def STHri : F3_2<3, 0b000110, 359 (outs), (ins MEMri:$addr, IntRegs:$src), 360 "sth $src, [$addr]", 361 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 362def STrr : F3_1<3, 0b000100, 363 (outs), (ins MEMrr:$addr, IntRegs:$src), 364 "st $src, [$addr]", 365 [(store IntRegs:$src, ADDRrr:$addr)]>; 366def STri : F3_2<3, 0b000100, 367 (outs), (ins MEMri:$addr, IntRegs:$src), 368 "st $src, [$addr]", 369 [(store IntRegs:$src, ADDRri:$addr)]>; 370 371// Section B.5 - Store Floating-point Instructions, p. 97 372def STFrr : F3_1<3, 0b100100, 373 (outs), (ins MEMrr:$addr, FPRegs:$src), 374 "st $src, [$addr]", 375 [(store FPRegs:$src, ADDRrr:$addr)]>; 376def STFri : F3_2<3, 0b100100, 377 (outs), (ins MEMri:$addr, FPRegs:$src), 378 "st $src, [$addr]", 379 [(store FPRegs:$src, ADDRri:$addr)]>; 380def STDFrr : F3_1<3, 0b100111, 381 (outs), (ins MEMrr:$addr, DFPRegs:$src), 382 "std $src, [$addr]", 383 [(store DFPRegs:$src, ADDRrr:$addr)]>; 384def STDFri : F3_2<3, 0b100111, 385 (outs), (ins MEMri:$addr, DFPRegs:$src), 386 "std $src, [$addr]", 387 [(store DFPRegs:$src, ADDRri:$addr)]>; 388 389// Section B.9 - SETHI Instruction, p. 104 390def SETHIi: F2_1<0b100, 391 (outs IntRegs:$dst), (ins i32imm:$src), 392 "sethi $src, $dst", 393 [(set IntRegs:$dst, SETHIimm:$src)]>; 394 395// Section B.10 - NOP Instruction, p. 105 396// (It's a special case of SETHI) 397let rd = 0, imm22 = 0 in 398 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 399 400// Section B.11 - Logical Instructions, p. 106 401defm AND : F3_12<"and", 0b000001, and>; 402 403def ANDNrr : F3_1<2, 0b000101, 404 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 405 "andn $b, $c, $dst", 406 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 407def ANDNri : F3_2<2, 0b000101, 408 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 409 "andn $b, $c, $dst", []>; 410 411defm OR : F3_12<"or", 0b000010, or>; 412 413def ORNrr : F3_1<2, 0b000110, 414 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 415 "orn $b, $c, $dst", 416 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 417def ORNri : F3_2<2, 0b000110, 418 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 419 "orn $b, $c, $dst", []>; 420defm XOR : F3_12<"xor", 0b000011, xor>; 421 422def XNORrr : F3_1<2, 0b000111, 423 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 424 "xnor $b, $c, $dst", 425 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 426def XNORri : F3_2<2, 0b000111, 427 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 428 "xnor $b, $c, $dst", []>; 429 430// Section B.12 - Shift Instructions, p. 107 431defm SLL : F3_12<"sll", 0b100101, shl>; 432defm SRL : F3_12<"srl", 0b100110, srl>; 433defm SRA : F3_12<"sra", 0b100111, sra>; 434 435// Section B.13 - Add Instructions, p. 108 436defm ADD : F3_12<"add", 0b000000, add>; 437 438// "LEA" forms of add (patterns to make tblgen happy) 439def LEA_ADDri : F3_2<2, 0b000000, 440 (outs IntRegs:$dst), (ins MEMri:$addr), 441 "add ${addr:arith}, $dst", 442 [(set IntRegs:$dst, ADDRri:$addr)]>; 443 444let Defs = [ICC] in 445 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 446 447let Uses = [ICC] in 448 defm ADDX : F3_12<"addx", 0b001000, adde>; 449 450// Section B.15 - Subtract Instructions, p. 110 451defm SUB : F3_12 <"sub" , 0b000100, sub>; 452let Uses = [ICC] in 453 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 454 455let Defs = [ICC] in 456 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 457 458let Uses = [ICC], Defs = [ICC] in 459 def SUBXCCrr: F3_1<2, 0b011100, 460 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 461 "subxcc $b, $c, $dst", []>; 462 463 464// Section B.18 - Multiply Instructions, p. 113 465let Defs = [Y] in { 466 defm UMUL : F3_12np<"umul", 0b001010>; 467 defm SMUL : F3_12 <"smul", 0b001011, mul>; 468} 469 470// Section B.19 - Divide Instructions, p. 115 471let Defs = [Y] in { 472 defm UDIV : F3_12np<"udiv", 0b001110>; 473 defm SDIV : F3_12np<"sdiv", 0b001111>; 474} 475 476// Section B.20 - SAVE and RESTORE, p. 117 477defm SAVE : F3_12np<"save" , 0b111100>; 478defm RESTORE : F3_12np<"restore", 0b111101>; 479 480// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 481 482// conditional branch class: 483class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 484 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 485 let isBranch = 1; 486 let isTerminator = 1; 487 let hasDelaySlot = 1; 488} 489 490let isBarrier = 1 in 491 def BA : BranchSP<0b1000, (ins brtarget:$dst), 492 "ba $dst", 493 [(br bb:$dst)]>; 494 495// FIXME: the encoding for the JIT should look at the condition field. 496let Uses = [ICC] in 497 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 498 "b$cc $dst", 499 [(SPbricc bb:$dst, imm:$cc)]>; 500 501 502// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 503 504// floating-point conditional branch class: 505class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 506 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 507 let isBranch = 1; 508 let isTerminator = 1; 509 let hasDelaySlot = 1; 510} 511 512// FIXME: the encoding for the JIT should look at the condition field. 513let Uses = [FCC] in 514 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 515 "fb$cc $dst", 516 [(SPbrfcc bb:$dst, imm:$cc)]>; 517 518 519// Section B.24 - Call and Link Instruction, p. 125 520// This is the only Format 1 instruction 521let Uses = [O6], 522 hasDelaySlot = 1, isCall = 1, 523 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 524 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 525 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 526 "call $dst", []> { 527 bits<30> disp; 528 let op = 1; 529 let Inst{29-0} = disp; 530 } 531 532 // indirect calls 533 def JMPLrr : F3_1<2, 0b111000, 534 (outs), (ins MEMrr:$ptr, variable_ops), 535 "call $ptr", 536 [(call ADDRrr:$ptr)]>; 537 def JMPLri : F3_2<2, 0b111000, 538 (outs), (ins MEMri:$ptr, variable_ops), 539 "call $ptr", 540 [(call ADDRri:$ptr)]>; 541} 542 543// Section B.28 - Read State Register Instructions 544let Uses = [Y] in 545 def RDY : F3_1<2, 0b101000, 546 (outs IntRegs:$dst), (ins), 547 "rd %y, $dst", []>; 548 549// Section B.29 - Write State Register Instructions 550let Defs = [Y] in { 551 def WRYrr : F3_1<2, 0b110000, 552 (outs), (ins IntRegs:$b, IntRegs:$c), 553 "wr $b, $c, %y", []>; 554 def WRYri : F3_2<2, 0b110000, 555 (outs), (ins IntRegs:$b, i32imm:$c), 556 "wr $b, $c, %y", []>; 557} 558// Convert Integer to Floating-point Instructions, p. 141 559def FITOS : F3_3<2, 0b110100, 0b011000100, 560 (outs FPRegs:$dst), (ins FPRegs:$src), 561 "fitos $src, $dst", 562 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 563def FITOD : F3_3<2, 0b110100, 0b011001000, 564 (outs DFPRegs:$dst), (ins FPRegs:$src), 565 "fitod $src, $dst", 566 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 567 568// Convert Floating-point to Integer Instructions, p. 142 569def FSTOI : F3_3<2, 0b110100, 0b011010001, 570 (outs FPRegs:$dst), (ins FPRegs:$src), 571 "fstoi $src, $dst", 572 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 573def FDTOI : F3_3<2, 0b110100, 0b011010010, 574 (outs FPRegs:$dst), (ins DFPRegs:$src), 575 "fdtoi $src, $dst", 576 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 577 578// Convert between Floating-point Formats Instructions, p. 143 579def FSTOD : F3_3<2, 0b110100, 0b011001001, 580 (outs DFPRegs:$dst), (ins FPRegs:$src), 581 "fstod $src, $dst", 582 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 583def FDTOS : F3_3<2, 0b110100, 0b011000110, 584 (outs FPRegs:$dst), (ins DFPRegs:$src), 585 "fdtos $src, $dst", 586 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 587 588// Floating-point Move Instructions, p. 144 589def FMOVS : F3_3<2, 0b110100, 0b000000001, 590 (outs FPRegs:$dst), (ins FPRegs:$src), 591 "fmovs $src, $dst", []>; 592def FNEGS : F3_3<2, 0b110100, 0b000000101, 593 (outs FPRegs:$dst), (ins FPRegs:$src), 594 "fnegs $src, $dst", 595 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 596def FABSS : F3_3<2, 0b110100, 0b000001001, 597 (outs FPRegs:$dst), (ins FPRegs:$src), 598 "fabss $src, $dst", 599 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 600 601 602// Floating-point Square Root Instructions, p.145 603def FSQRTS : F3_3<2, 0b110100, 0b000101001, 604 (outs FPRegs:$dst), (ins FPRegs:$src), 605 "fsqrts $src, $dst", 606 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 607def FSQRTD : F3_3<2, 0b110100, 0b000101010, 608 (outs DFPRegs:$dst), (ins DFPRegs:$src), 609 "fsqrtd $src, $dst", 610 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 611 612 613 614// Floating-point Add and Subtract Instructions, p. 146 615def FADDS : F3_3<2, 0b110100, 0b001000001, 616 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 617 "fadds $src1, $src2, $dst", 618 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 619def FADDD : F3_3<2, 0b110100, 0b001000010, 620 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 621 "faddd $src1, $src2, $dst", 622 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 623def FSUBS : F3_3<2, 0b110100, 0b001000101, 624 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 625 "fsubs $src1, $src2, $dst", 626 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 627def FSUBD : F3_3<2, 0b110100, 0b001000110, 628 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 629 "fsubd $src1, $src2, $dst", 630 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 631 632// Floating-point Multiply and Divide Instructions, p. 147 633def FMULS : F3_3<2, 0b110100, 0b001001001, 634 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 635 "fmuls $src1, $src2, $dst", 636 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 637def FMULD : F3_3<2, 0b110100, 0b001001010, 638 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 639 "fmuld $src1, $src2, $dst", 640 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 641def FSMULD : F3_3<2, 0b110100, 0b001101001, 642 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 643 "fsmuld $src1, $src2, $dst", 644 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 645 (fextend FPRegs:$src2)))]>; 646def FDIVS : F3_3<2, 0b110100, 0b001001101, 647 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 648 "fdivs $src1, $src2, $dst", 649 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 650def FDIVD : F3_3<2, 0b110100, 0b001001110, 651 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 652 "fdivd $src1, $src2, $dst", 653 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 654 655// Floating-point Compare Instructions, p. 148 656// Note: the 2nd template arg is different for these guys. 657// Note 2: the result of a FCMP is not available until the 2nd cycle 658// after the instr is retired, but there is no interlock. This behavior 659// is modelled with a forced noop after the instruction. 660let Defs = [FCC] in { 661 def FCMPS : F3_3<2, 0b110101, 0b001010001, 662 (outs), (ins FPRegs:$src1, FPRegs:$src2), 663 "fcmps $src1, $src2\n\tnop", 664 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 665 def FCMPD : F3_3<2, 0b110101, 0b001010010, 666 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 667 "fcmpd $src1, $src2\n\tnop", 668 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 669} 670 671//===----------------------------------------------------------------------===// 672// V9 Instructions 673//===----------------------------------------------------------------------===// 674 675// V9 Conditional Moves. 676let Predicates = [HasV9], Constraints = "$T = $dst" in { 677 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 678 // FIXME: Add instruction encodings for the JIT some day. 679 def MOVICCrr 680 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 681 "mov$cc %icc, $F, $dst", 682 [(set IntRegs:$dst, 683 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 684 def MOVICCri 685 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 686 "mov$cc %icc, $F, $dst", 687 [(set IntRegs:$dst, 688 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 689 690 def MOVFCCrr 691 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 692 "mov$cc %fcc0, $F, $dst", 693 [(set IntRegs:$dst, 694 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 695 def MOVFCCri 696 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 697 "mov$cc %fcc0, $F, $dst", 698 [(set IntRegs:$dst, 699 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 700 701 def FMOVS_ICC 702 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 703 "fmovs$cc %icc, $F, $dst", 704 [(set FPRegs:$dst, 705 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 706 def FMOVD_ICC 707 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 708 "fmovd$cc %icc, $F, $dst", 709 [(set DFPRegs:$dst, 710 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 711 def FMOVS_FCC 712 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 713 "fmovs$cc %fcc0, $F, $dst", 714 [(set FPRegs:$dst, 715 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 716 def FMOVD_FCC 717 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 718 "fmovd$cc %fcc0, $F, $dst", 719 [(set DFPRegs:$dst, 720 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 721 722} 723 724// Floating-Point Move Instructions, p. 164 of the V9 manual. 725let Predicates = [HasV9] in { 726 def FMOVD : F3_3<2, 0b110100, 0b000000010, 727 (outs DFPRegs:$dst), (ins DFPRegs:$src), 728 "fmovd $src, $dst", []>; 729 def FNEGD : F3_3<2, 0b110100, 0b000000110, 730 (outs DFPRegs:$dst), (ins DFPRegs:$src), 731 "fnegd $src, $dst", 732 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 733 def FABSD : F3_3<2, 0b110100, 0b000001010, 734 (outs DFPRegs:$dst), (ins DFPRegs:$src), 735 "fabsd $src, $dst", 736 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 737} 738 739// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 740// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 741def POPCrr : F3_1<2, 0b101110, 742 (outs IntRegs:$dst), (ins IntRegs:$src), 743 "popc $src, $dst", []>, Requires<[HasV9]>; 744def : Pat<(ctpop IntRegs:$src), 745 (POPCrr (SLLri IntRegs:$src, 0))>; 746 747//===----------------------------------------------------------------------===// 748// Non-Instruction Patterns 749//===----------------------------------------------------------------------===// 750 751// Small immediates. 752def : Pat<(i32 simm13:$val), 753 (ORri G0, imm:$val)>; 754// Arbitrary immediates. 755def : Pat<(i32 imm:$val), 756 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 757 758// subc 759def : Pat<(subc IntRegs:$b, IntRegs:$c), 760 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 761def : Pat<(subc IntRegs:$b, simm13:$val), 762 (SUBCCri IntRegs:$b, imm:$val)>; 763 764// Global addresses, constant pool entries 765def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 766def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 767def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 768def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 769 770// Add reg, lo. This is used when taking the addr of a global/constpool entry. 771def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 772 (ADDri IntRegs:$r, tglobaladdr:$in)>; 773def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 774 (ADDri IntRegs:$r, tconstpool:$in)>; 775 776// Calls: 777def : Pat<(call tglobaladdr:$dst), 778 (CALL tglobaladdr:$dst)>; 779def : Pat<(call texternalsym:$dst), 780 (CALL texternalsym:$dst)>; 781 782// Map integer extload's to zextloads. 783def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 784def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 785def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 786def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 787def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 788def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 789 790// zextload bool -> zextload byte 791def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 792def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 793