SparcInstrInfo.td revision c42077d37194a1872dc402522d4d7a0e81f83047
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm> : InstV8 { 39 let Name = nm; 40} 41def PHI : PseudoInstV8<"PHI">; 42def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">; 43def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">; 44def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">; 45def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">; 46 47// Section A.3 - Synthetic Instructions, p. 85 48// special cases of JMPL: 49let isReturn = 1, isTerminator = 1, simm13 = 8 in 50 def RET : F3_2<2, 0b111000, "ret">; 51let isReturn = 1, isTerminator = 1, simm13 = 8 in 52 def RETL: F3_2<2, 0b111000, "retl">; 53// CMP is a special case of SUBCC where destination is ignored, by setting it to 54// %g0 (hardwired zero). 55// FIXME: should keep track of the fact that it defs the integer condition codes 56let rd = 0 in 57 def CMPri: F3_2<2, 0b010100, "cmp">; 58 59// Section B.1 - Load Integer Instructions, p. 90 60def LDSB: F3_2<3, 0b001001, "ldsb">; 61def LDSH: F3_2<3, 0b001010, "ldsh">; 62def LDUB: F3_2<3, 0b000001, "ldub">; 63def LDUH: F3_2<3, 0b000010, "lduh">; 64def LD : F3_2<3, 0b000000, "ld">; 65def LDD : F3_2<3, 0b000011, "ldd">; 66 67// Section B.2 - Load Floating-point Instructions, p. 92 68def LDFrr : F3_1<3, 0b100000, "ld">; 69def LDFri : F3_2<3, 0b100000, "ld">; 70def LDDFrr : F3_1<3, 0b100011, "ldd">; 71def LDDFri : F3_2<3, 0b100011, "ldd">; 72def LDFSRrr: F3_1<3, 0b100001, "ld">; 73def LDFSRri: F3_2<3, 0b100001, "ld">; 74 75// Section B.4 - Store Integer Instructions, p. 95 76def STB : F3_2<3, 0b000101, "stb">; 77def STH : F3_2<3, 0b000110, "sth">; 78def ST : F3_2<3, 0b000100, "st">; 79def STD : F3_2<3, 0b000111, "std">; 80 81// Section B.5 - Store Floating-point Instructions, p. 97 82def STFrr : F3_1<3, 0b100100, "st">; 83def STFri : F3_2<3, 0b100100, "st">; 84def STDFrr : F3_1<3, 0b100111, "std">; 85def STDFri : F3_2<3, 0b100111, "std">; 86def STFSRrr : F3_1<3, 0b100101, "st">; 87def STFSRri : F3_2<3, 0b100101, "st">; 88def STDFQrr : F3_1<3, 0b100110, "std">; 89def STDFQri : F3_2<3, 0b100110, "std">; 90 91// Section B.9 - SETHI Instruction, p. 104 92def SETHIi: F2_1<0b100, "sethi">; 93 94// Section B.10 - NOP Instruction, p. 105 95// (It's a special case of SETHI) 96let rd = 0, imm = 0 in 97 def NOP : F2_1<0b100, "nop">; 98 99// Section B.11 - Logical Instructions, p. 106 100def ANDrr : F3_1<2, 0b000001, "and">; 101def ANDri : F3_2<2, 0b000001, "and">; 102def ORrr : F3_1<2, 0b000010, "or">; 103def ORri : F3_2<2, 0b000010, "or">; 104def XORrr : F3_1<2, 0b000011, "xor">; 105def XORri : F3_2<2, 0b000011, "xor">; 106 107// Section B.12 - Shift Instructions, p. 107 108def SLLrr : F3_1<2, 0b100101, "sll">; 109def SLLri : F3_2<2, 0b100101, "sll">; 110def SRLrr : F3_1<2, 0b100110, "srl">; 111def SRLri : F3_2<2, 0b100110, "srl">; 112def SRArr : F3_1<2, 0b100111, "sra">; 113def SRAri : F3_2<2, 0b100111, "sra">; 114 115// Section B.13 - Add Instructions, p. 108 116def ADDrr : F3_1<2, 0b000000, "add">; 117def ADDri : F3_2<2, 0b000000, "add">; 118 119// Section B.15 - Subtract Instructions, p. 110 120def SUBrr : F3_1<2, 0b000100, "sub">; 121def SUBCCrr : F3_1<2, 0b010100, "subcc">; 122def SUBCCri : F3_2<2, 0b010100, "subcc">; 123 124// Section B.18 - Multiply Instructions, p. 113 125def UMULrr : F3_1<2, 0b001010, "umul">; 126def SMULrr : F3_1<2, 0b001011, "smul">; 127 128// Section B.19 - Divide Instructions, p. 115 129def UDIVrr : F3_1<2, 0b001110, "udiv">; 130def UDIVri : F3_2<2, 0b001110, "udiv">; 131def SDIVrr : F3_1<2, 0b001111, "sdiv">; 132def SDIVri : F3_2<2, 0b001111, "sdiv">; 133def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 134def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 135def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 136def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 137 138// Section B.20 - SAVE and RESTORE, p. 117 139def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 140def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 141def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 142def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 143 144// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 145 146// conditional branch class: 147class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 148 let isBranch = 1; 149 let isTerminator = 1; 150} 151 152let isBarrier = 1 in 153 def BA : BranchV8<0b1000, "ba">; 154def BN : BranchV8<0b0000, "bn">; 155def BNE : BranchV8<0b1001, "bne">; 156def BE : BranchV8<0b0001, "be">; 157def BG : BranchV8<0b1010, "bg">; 158def BLE : BranchV8<0b0010, "ble">; 159def BGE : BranchV8<0b1011, "bge">; 160def BL : BranchV8<0b0011, "bl">; 161def BGU : BranchV8<0b1100, "bgu">; 162def BLEU : BranchV8<0b0100, "bleu">; 163def BCC : BranchV8<0b1101, "bcc">; 164def BCS : BranchV8<0b0101, "bcs">; 165 166// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 167 168// floating-point conditional branch class: 169class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 170 let isBranch = 1; 171 let isTerminator = 1; 172} 173 174def FBA : FPBranchV8<0b1000, "fba">; 175def FBN : FPBranchV8<0b0000, "fbn">; 176def FBU : FPBranchV8<0b0111, "fbu">; 177def FBG : FPBranchV8<0b0110, "fbg">; 178def FBUG : FPBranchV8<0b0101, "fbug">; 179def FBL : FPBranchV8<0b0100, "fbl">; 180def FBUL : FPBranchV8<0b0011, "fbul">; 181def FBLG : FPBranchV8<0b0010, "fblg">; 182def FBNE : FPBranchV8<0b0001, "fbne">; 183def FBE : FPBranchV8<0b1001, "fbe">; 184def FBUE : FPBranchV8<0b1010, "fbue">; 185def FBGE : FPBranchV8<0b1011, "fbge">; 186def FBUGE: FPBranchV8<0b1100, "fbuge">; 187def FBLE : FPBranchV8<0b1101, "fble">; 188def FBULE: FPBranchV8<0b1110, "fbule">; 189def FBO : FPBranchV8<0b1111, "fbo">; 190 191// Section B.24 - Call and Link Instruction, p. 125 192// This is the only Format 1 instruction 193def CALL : InstV8 { 194 bits<30> disp; 195 let op = 1; 196 let Inst{29-0} = disp; 197 let Name = "call"; 198 let isCall = 1; 199} 200 201// Section B.25 - Jump and Link, p. 126 202let isCall = 1 in 203 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 204 205// Section B.29 - Write State Register Instructions 206def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 207def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 208 209// Convert Integer to Floating-point Instructions, p. 141 210def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 211def FITOD : F3_3<2, 0b110100, 0b011001000, "fitos">; 212 213// Convert between Floating-point Formats Instructions, p. 143 214def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 215def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 216 217// Floating-point Move Instructions, p. 144 218def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 219def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 220def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 221 222// Floating-point Add and Subtract Instructions, p. 146 223def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 224def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 225def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 226def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 227 228// Floating-point Multiply and Divide Instructions, p. 147 229def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 230def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 231def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 232def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 233def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 234 235// Floating-point Compare Instructions, p. 148 236// Note: the 2nd template arg is different for these guys 237def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 238def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 239def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 240def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 241 242