SparcInstrInfo.td revision d2cd46676c697137be7b57c04e3615ba2cdc00b2
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42//===----------------------------------------------------------------------===// 43// Instructions 44//===----------------------------------------------------------------------===// 45 46// Pseudo instructions. 47class PseudoInstV8<string asmstr, dag ops> : InstV8 { 48 let AsmString = asmstr; 49 dag OperandList = ops; 50} 51def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 52def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 53 (ops i32imm:$amt)>; 54def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 55 (ops i32imm:$amt)>; 56//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 57def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 58 (ops IntRegs:$dst)>; 59def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 60 61// Section A.3 - Synthetic Instructions, p. 85 62// special cases of JMPL: 63let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 64 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 65 def RET : F3_2<2, 0b111000, 66 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 67 "ret $b, $c, $dst", []>; 68 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 69 def RETL: F3_2<2, 0b111000, (ops), 70 "retl", [(ret)]>; 71} 72// CMP is a special case of SUBCC where destination is ignored, by setting it to 73// %g0 (hardwired zero). 74// FIXME: should keep track of the fact that it defs the integer condition codes 75let rd = 0 in 76 def CMPri: F3_2<2, 0b010100, 77 (ops IntRegs:$b, i32imm:$c), 78 "cmp $b, $c", []>; 79 80// Section B.1 - Load Integer Instructions, p. 90 81def LDSB: F3_2<3, 0b001001, 82 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 83 "ldsb [$b+$c], $dst", []>; 84def LDSH: F3_2<3, 0b001010, 85 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 86 "ldsh [$b+$c], $dst", []>; 87def LDUB: F3_2<3, 0b000001, 88 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 89 "ldub [$b+$c], $dst", []>; 90def LDUH: F3_2<3, 0b000010, 91 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 92 "lduh [$b+$c], $dst", []>; 93def LD : F3_2<3, 0b000000, 94 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 95 "ld [$b+$c], $dst", []>; 96def LDD : F3_2<3, 0b000011, 97 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 98 "ldd [$b+$c], $dst", []>; 99 100// Section B.2 - Load Floating-point Instructions, p. 92 101def LDFrr : F3_1<3, 0b100000, 102 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 103 "ld [$b+$c], $dst", []>; 104def LDFri : F3_2<3, 0b100000, 105 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 106 "ld [$b+$c], $dst", []>; 107def LDDFrr : F3_1<3, 0b100011, 108 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 109 "ldd [$b+$c], $dst", []>; 110def LDDFri : F3_2<3, 0b100011, 111 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 112 "ldd [$b+$c], $dst", []>; 113def LDFSRrr: F3_1<3, 0b100001, 114 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 115 "ld [$b+$c], $dst", []>; 116def LDFSRri: F3_2<3, 0b100001, 117 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 118 "ld [$b+$c], $dst", []>; 119 120// Section B.4 - Store Integer Instructions, p. 95 121def STB : F3_2<3, 0b000101, 122 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 123 "stb $src, [$base+$offset]", []>; 124def STH : F3_2<3, 0b000110, 125 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 126 "sth $src, [$base+$offset]", []>; 127def ST : F3_2<3, 0b000100, 128 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 129 "st $src, [$base+$offset]", []>; 130def STD : F3_2<3, 0b000111, 131 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 132 "std $src, [$base+$offset]", []>; 133 134// Section B.5 - Store Floating-point Instructions, p. 97 135def STFrr : F3_1<3, 0b100100, 136 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 137 "st $src, [$base+$offset]", []>; 138def STFri : F3_2<3, 0b100100, 139 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 140 "st $src, [$base+$offset]", []>; 141def STDFrr : F3_1<3, 0b100111, 142 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 143 "std $src, [$base+$offset]", []>; 144def STDFri : F3_2<3, 0b100111, 145 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 146 "std $src, [$base+$offset]", []>; 147def STFSRrr : F3_1<3, 0b100101, 148 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 149 "st $src, [$base+$offset]", []>; 150def STFSRri : F3_2<3, 0b100101, 151 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 152 "st $src, [$base+$offset]", []>; 153def STDFQrr : F3_1<3, 0b100110, 154 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 155 "std $src, [$base+$offset]", []>; 156def STDFQri : F3_2<3, 0b100110, 157 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 158 "std $src, [$base+$offset]", []>; 159 160// Section B.9 - SETHI Instruction, p. 104 161def SETHIi: F2_1<0b100, 162 (ops IntRegs:$dst, i32imm:$src), 163 "sethi $src, $dst">; 164 165// Section B.10 - NOP Instruction, p. 105 166// (It's a special case of SETHI) 167let rd = 0, imm22 = 0 in 168 def NOP : F2_1<0b100, (ops), "nop">; 169 170// Section B.11 - Logical Instructions, p. 106 171def ANDrr : F3_1<2, 0b000001, 172 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 173 "and $b, $c, $dst", 174 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 175def ANDri : F3_2<2, 0b000001, 176 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 177 "and $b, $c, $dst", 178 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 179def ANDCCrr : F3_1<2, 0b010001, 180 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 181 "andcc $b, $c, $dst", []>; 182def ANDCCri : F3_2<2, 0b010001, 183 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 184 "andcc $b, $c, $dst", []>; 185def ANDNrr : F3_1<2, 0b000101, 186 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 187 "andn $b, $c, $dst", []>; 188def ANDNri : F3_2<2, 0b000101, 189 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 190 "andn $b, $c, $dst", []>; 191def ANDNCCrr: F3_1<2, 0b010101, 192 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 193 "andncc $b, $c, $dst", []>; 194def ANDNCCri: F3_2<2, 0b010101, 195 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 196 "andncc $b, $c, $dst", []>; 197def ORrr : F3_1<2, 0b000010, 198 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 199 "or $b, $c, $dst", 200 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 201def ORri : F3_2<2, 0b000010, 202 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 203 "or $b, $c, $dst", 204 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 205def ORCCrr : F3_1<2, 0b010010, 206 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 207 "orcc $b, $c, $dst", []>; 208def ORCCri : F3_2<2, 0b010010, 209 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 210 "orcc $b, $c, $dst", []>; 211def ORNrr : F3_1<2, 0b000110, 212 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 213 "orn $b, $c, $dst", []>; 214def ORNri : F3_2<2, 0b000110, 215 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 216 "orn $b, $c, $dst", []>; 217def ORNCCrr : F3_1<2, 0b010110, 218 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 219 "orncc $b, $c, $dst", []>; 220def ORNCCri : F3_2<2, 0b010110, 221 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 222 "orncc $b, $c, $dst", []>; 223def XORrr : F3_1<2, 0b000011, 224 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 225 "xor $b, $c, $dst", 226 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 227def XORri : F3_2<2, 0b000011, 228 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 229 "xor $b, $c, $dst", 230 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 231def XORCCrr : F3_1<2, 0b010011, 232 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 233 "xorcc $b, $c, $dst", []>; 234def XORCCri : F3_2<2, 0b010011, 235 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 236 "xorcc $b, $c, $dst", []>; 237def XNORrr : F3_1<2, 0b000111, 238 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 239 "xnor $b, $c, $dst", []>; 240def XNORri : F3_2<2, 0b000111, 241 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 242 "xnor $b, $c, $dst", []>; 243def XNORCCrr: F3_1<2, 0b010111, 244 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 245 "xnorcc $b, $c, $dst", []>; 246def XNORCCri: F3_2<2, 0b010111, 247 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 248 "xnorcc $b, $c, $dst", []>; 249 250// Section B.12 - Shift Instructions, p. 107 251def SLLrr : F3_1<2, 0b100101, 252 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 253 "sll $b, $c, $dst", 254 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 255def SLLri : F3_2<2, 0b100101, 256 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 257 "sll $b, $c, $dst", 258 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 259def SRLrr : F3_1<2, 0b100110, 260 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 261 "srl $b, $c, $dst", 262 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 263def SRLri : F3_2<2, 0b100110, 264 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 265 "srl $b, $c, $dst", 266 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 267def SRArr : F3_1<2, 0b100111, 268 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 269 "sra $b, $c, $dst", 270 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 271def SRAri : F3_2<2, 0b100111, 272 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 273 "sra $b, $c, $dst", 274 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 275 276// Section B.13 - Add Instructions, p. 108 277def ADDrr : F3_1<2, 0b000000, 278 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 279 "add $b, $c, $dst", 280 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 281def ADDri : F3_2<2, 0b000000, 282 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 283 "add $b, $c, $dst", 284 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 285def ADDCCrr : F3_1<2, 0b010000, 286 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 287 "addcc $b, $c, $dst", []>; 288def ADDCCri : F3_2<2, 0b010000, 289 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 290 "addcc $b, $c, $dst", []>; 291def ADDXrr : F3_1<2, 0b001000, 292 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 293 "addx $b, $c, $dst", []>; 294def ADDXri : F3_2<2, 0b001000, 295 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 296 "addx $b, $c, $dst", []>; 297def ADDXCCrr: F3_1<2, 0b011000, 298 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 299 "addxcc $b, $c, $dst", []>; 300def ADDXCCri: F3_2<2, 0b011000, 301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 302 "addxcc $b, $c, $dst", []>; 303 304// Section B.15 - Subtract Instructions, p. 110 305def SUBrr : F3_1<2, 0b000100, 306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 307 "sub $b, $c, $dst", 308 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 309def SUBri : F3_2<2, 0b000100, 310 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 311 "sub $b, $c, $dst", 312 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 313def SUBCCrr : F3_1<2, 0b010100, 314 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 315 "subcc $b, $c, $dst", []>; 316def SUBCCri : F3_2<2, 0b010100, 317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 318 "subcc $b, $c, $dst", []>; 319def SUBXrr : F3_1<2, 0b001100, 320 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 321 "subx $b, $c, $dst", []>; 322def SUBXri : F3_2<2, 0b001100, 323 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 324 "subx $b, $c, $dst", []>; 325def SUBXCCrr: F3_1<2, 0b011100, 326 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 327 "subxcc $b, $c, $dst", []>; 328def SUBXCCri: F3_2<2, 0b011100, 329 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 330 "subxcc $b, $c, $dst", []>; 331 332// Section B.18 - Multiply Instructions, p. 113 333def UMULrr : F3_1<2, 0b001010, 334 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 335 "umul $b, $c, $dst", []>; 336def UMULri : F3_2<2, 0b001010, 337 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 338 "umul $b, $c, $dst", []>; 339def SMULrr : F3_1<2, 0b001011, 340 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 341 "smul $b, $c, $dst", []>; 342def SMULri : F3_2<2, 0b001011, 343 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 344 "smul $b, $c, $dst", []>; 345def UMULCCrr: F3_1<2, 0b011010, 346 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 347 "umulcc $b, $c, $dst", []>; 348def UMULCCri: F3_2<2, 0b011010, 349 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 350 "umulcc $b, $c, $dst", []>; 351def SMULCCrr: F3_1<2, 0b011011, 352 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 353 "smulcc $b, $c, $dst", []>; 354def SMULCCri: F3_2<2, 0b011011, 355 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 356 "smulcc $b, $c, $dst", []>; 357 358// Section B.19 - Divide Instructions, p. 115 359def UDIVrr : F3_1<2, 0b001110, 360 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 361 "udiv $b, $c, $dst", []>; 362def UDIVri : F3_2<2, 0b001110, 363 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 364 "udiv $b, $c, $dst", []>; 365def SDIVrr : F3_1<2, 0b001111, 366 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 367 "sdiv $b, $c, $dst", []>; 368def SDIVri : F3_2<2, 0b001111, 369 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 370 "sdiv $b, $c, $dst", []>; 371def UDIVCCrr : F3_1<2, 0b011110, 372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 373 "udivcc $b, $c, $dst", []>; 374def UDIVCCri : F3_2<2, 0b011110, 375 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 376 "udivcc $b, $c, $dst", []>; 377def SDIVCCrr : F3_1<2, 0b011111, 378 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 379 "sdivcc $b, $c, $dst", []>; 380def SDIVCCri : F3_2<2, 0b011111, 381 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 382 "sdivcc $b, $c, $dst", []>; 383 384// Section B.20 - SAVE and RESTORE, p. 117 385def SAVErr : F3_1<2, 0b111100, 386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 387 "save $b, $c, $dst", []>; 388def SAVEri : F3_2<2, 0b111100, 389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 390 "save $b, $c, $dst", []>; 391def RESTORErr : F3_1<2, 0b111101, 392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 393 "restore $b, $c, $dst", []>; 394def RESTOREri : F3_2<2, 0b111101, 395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 396 "restore $b, $c, $dst", []>; 397 398// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 399 400// conditional branch class: 401class BranchV8<bits<4> cc, dag ops, string asmstr> 402 : F2_2<cc, 0b010, ops, asmstr> { 403 let isBranch = 1; 404 let isTerminator = 1; 405 let hasDelaySlot = 1; 406} 407 408let isBarrier = 1 in 409 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">; 410def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">; 411def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">; 412def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">; 413def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">; 414def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">; 415def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">; 416def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">; 417def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">; 418def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">; 419def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">; 420def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">; 421 422// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 423 424// floating-point conditional branch class: 425class FPBranchV8<bits<4> cc, dag ops, string asmstr> 426 : F2_2<cc, 0b110, ops, asmstr> { 427 let isBranch = 1; 428 let isTerminator = 1; 429 let hasDelaySlot = 1; 430} 431 432def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">; 433def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">; 434def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">; 435def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">; 436def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">; 437def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">; 438def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">; 439def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">; 440def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">; 441def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">; 442def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">; 443def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">; 444def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">; 445def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">; 446def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">; 447def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">; 448 449 450 451// Section B.24 - Call and Link Instruction, p. 125 452// This is the only Format 1 instruction 453let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 454 // pc-relative call: 455 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 456 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 457 def CALL : InstV8 { 458 let OperandList = (ops IntRegs:$dst); 459 bits<30> disp; 460 let op = 1; 461 let Inst{29-0} = disp; 462 let AsmString = "call $dst"; 463 } 464 465 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 466 // be an implicit def): 467 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 468 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 469 def JMPLrr : F3_1<2, 0b111000, 470 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 471 "jmpl $b+$c, $dst", []>; 472} 473 474// Section B.29 - Write State Register Instructions 475def WRrr : F3_1<2, 0b110000, 476 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 477 "wr $b, $c, $dst", []>; 478def WRri : F3_2<2, 0b110000, 479 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 480 "wr $b, $c, $dst", []>; 481 482// Convert Integer to Floating-point Instructions, p. 141 483def FITOS : F3_3<2, 0b110100, 0b011000100, 484 (ops FPRegs:$dst, FPRegs:$src), 485 "fitos $src, $dst">; 486def FITOD : F3_3<2, 0b110100, 0b011001000, 487 (ops DFPRegs:$dst, DFPRegs:$src), 488 "fitod $src, $dst">; 489 490// Convert Floating-point to Integer Instructions, p. 142 491def FSTOI : F3_3<2, 0b110100, 0b011010001, 492 (ops FPRegs:$dst, FPRegs:$src), 493 "fstoi $src, $dst">; 494def FDTOI : F3_3<2, 0b110100, 0b011010010, 495 (ops DFPRegs:$dst, DFPRegs:$src), 496 "fdtoi $src, $dst">; 497 498// Convert between Floating-point Formats Instructions, p. 143 499def FSTOD : F3_3<2, 0b110100, 0b011001001, 500 (ops DFPRegs:$dst, FPRegs:$src), 501 "fstod $src, $dst">; 502def FDTOS : F3_3<2, 0b110100, 0b011000110, 503 (ops FPRegs:$dst, DFPRegs:$src), 504 "fdtos $src, $dst">; 505 506// Floating-point Move Instructions, p. 144 507def FMOVS : F3_3<2, 0b110100, 0b000000001, 508 (ops FPRegs:$dst, FPRegs:$src), 509 "fmovs $src, $dst">; 510def FNEGS : F3_3<2, 0b110100, 0b000000101, 511 (ops FPRegs:$dst, FPRegs:$src), 512 "fnegs $src, $dst">; 513def FABSS : F3_3<2, 0b110100, 0b000001001, 514 (ops FPRegs:$dst, FPRegs:$src), 515 "fabss $src, $dst">; 516 517// Floating-point Add and Subtract Instructions, p. 146 518def FADDS : F3_3<2, 0b110100, 0b001000001, 519 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 520 "fadds $src1, $src2, $dst">; 521def FADDD : F3_3<2, 0b110100, 0b001000010, 522 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 523 "faddd $src1, $src2, $dst">; 524def FSUBS : F3_3<2, 0b110100, 0b001000101, 525 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 526 "fsubs $src1, $src2, $dst">; 527def FSUBD : F3_3<2, 0b110100, 0b001000110, 528 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 529 "fsubd $src1, $src2, $dst">; 530 531// Floating-point Multiply and Divide Instructions, p. 147 532def FMULS : F3_3<2, 0b110100, 0b001001001, 533 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 534 "fmuls $src1, $src2, $dst">; 535def FMULD : F3_3<2, 0b110100, 0b001001010, 536 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 537 "fmuld $src1, $src2, $dst">; 538def FSMULD : F3_3<2, 0b110100, 0b001101001, 539 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 540 "fsmuld $src1, $src2, $dst">; 541def FDIVS : F3_3<2, 0b110100, 0b001001101, 542 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 543 "fdivs $src1, $src2, $dst">; 544def FDIVD : F3_3<2, 0b110100, 0b001001110, 545 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 546 "fdivd $src1, $src2, $dst">; 547 548// Floating-point Compare Instructions, p. 148 549// Note: the 2nd template arg is different for these guys. 550// Note 2: the result of a FCMP is not available until the 2nd cycle 551// after the instr is retired, but there is no interlock. This behavior 552// is modelled with a forced noop after the instruction. 553def FCMPS : F3_3<2, 0b110101, 0b001010001, 554 (ops FPRegs:$src1, FPRegs:$src2), 555 "fcmps $src1, $src2\n\tnop">; 556def FCMPD : F3_3<2, 0b110101, 0b001010010, 557 (ops DFPRegs:$src1, DFPRegs:$src2), 558 "fcmpd $src1, $src2\n\tnop">; 559def FCMPES : F3_3<2, 0b110101, 0b001010101, 560 (ops FPRegs:$src1, FPRegs:$src2), 561 "fcmpes $src1, $src2\n\tnop">; 562def FCMPED : F3_3<2, 0b110101, 0b001010110, 563 (ops DFPRegs:$src1, DFPRegs:$src2), 564 "fcmped $src1, $src2\n\tnop">; 565 566//===----------------------------------------------------------------------===// 567// Non-Instruction Patterns 568//===----------------------------------------------------------------------===// 569 570// Small immediates. 571def : Pat<(i32 simm13:$val), 572 (ORri G0, imm:$val)>; 573