SparcInstrInfo.td revision d55e1ca5ef96821d8c96da6f0d79e3f96d810cdd
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42def LO10 : SDNodeXForm<imm, [{ 43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 44}]>; 45 46def HI22 : SDNodeXForm<imm, [{ 47 // Transformation function: shift the immediate value down into the low bits. 48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 49}]>; 50 51def SETHIimm : PatLeaf<(imm), [{ 52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 53}], HI22>; 54 55// Addressing modes. 56def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 57def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 58 59// Address operands 60def MEMrr : Operand<i32> { 61 let PrintMethod = "printMemOperand"; 62 let NumMIOperands = 2; 63 let MIOperandInfo = (ops IntRegs, IntRegs); 64} 65def MEMri : Operand<i32> { 66 let PrintMethod = "printMemOperand"; 67 let NumMIOperands = 2; 68 let MIOperandInfo = (ops IntRegs, i32imm); 69} 70 71//===----------------------------------------------------------------------===// 72// Instructions 73//===----------------------------------------------------------------------===// 74 75// Pseudo instructions. 76class PseudoInstV8<string asmstr, dag ops> : InstV8 { 77 let AsmString = asmstr; 78 dag OperandList = ops; 79} 80def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 81def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 82 (ops i32imm:$amt)>; 83def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 84 (ops i32imm:$amt)>; 85//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 86def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 87 (ops IntRegs:$dst)>; 88def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 89 90// Section A.3 - Synthetic Instructions, p. 85 91// special cases of JMPL: 92let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 94 def RET : F3_2<2, 0b111000, 95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 96 "ret $b, $c, $dst", []>; 97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 98 def RETL: F3_2<2, 0b111000, (ops), 99 "retl", [(ret)]>; 100} 101// CMP is a special case of SUBCC where destination is ignored, by setting it to 102// %g0 (hardwired zero). 103// FIXME: should keep track of the fact that it defs the integer condition codes 104let rd = 0 in 105 def CMPri: F3_2<2, 0b010100, 106 (ops IntRegs:$b, i32imm:$c), 107 "cmp $b, $c", []>; 108 109// Section B.1 - Load Integer Instructions, p. 90 110def LDSBrr : F3_1<3, 0b001001, 111 (ops IntRegs:$dst, MEMrr:$addr), 112 "ldsb [$addr], $dst", 113 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 114def LDSBri : F3_2<3, 0b001001, 115 (ops IntRegs:$dst, MEMri:$addr), 116 "ldsb [$addr], $dst", 117 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 118def LDSHrr : F3_1<3, 0b001010, 119 (ops IntRegs:$dst, MEMrr:$addr), 120 "ldsh [$addr], $dst", 121 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 122def LDSHri : F3_2<3, 0b001010, 123 (ops IntRegs:$dst, MEMri:$addr), 124 "ldsh [$addr], $dst", 125 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 126def LDUBrr : F3_1<3, 0b000001, 127 (ops IntRegs:$dst, MEMrr:$addr), 128 "ldub [$addr], $dst", 129 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 130def LDUBri : F3_2<3, 0b000001, 131 (ops IntRegs:$dst, MEMri:$addr), 132 "ldub [$addr], $dst", 133 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 134def LDUHrr : F3_1<3, 0b000010, 135 (ops IntRegs:$dst, MEMrr:$addr), 136 "lduh [$addr], $dst", 137 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 138def LDUHri : F3_2<3, 0b000010, 139 (ops IntRegs:$dst, MEMri:$addr), 140 "lduh [$addr], $dst", 141 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 142def LDrr : F3_1<3, 0b000000, 143 (ops IntRegs:$dst, MEMrr:$addr), 144 "ld [$addr], $dst", 145 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 146def LDri : F3_2<3, 0b000000, 147 (ops IntRegs:$dst, MEMri:$addr), 148 "ld [$addr], $dst", 149 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 150def LDDrr : F3_1<3, 0b000011, 151 (ops IntRegs:$dst, MEMrr:$addr), 152 "ldd [$addr], $dst", []>; 153def LDDri : F3_2<3, 0b000011, 154 (ops IntRegs:$dst, MEMri:$addr), 155 "ldd [$addr], $dst", []>; 156 157// Section B.2 - Load Floating-point Instructions, p. 92 158def LDFrr : F3_1<3, 0b100000, 159 (ops FPRegs:$dst, MEMrr:$addr), 160 "ld [$addr], $dst", 161 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 162def LDFri : F3_2<3, 0b100000, 163 (ops FPRegs:$dst, MEMri:$addr), 164 "ld [$addr], $dst", 165 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 166def LDDFrr : F3_1<3, 0b100011, 167 (ops DFPRegs:$dst, MEMrr:$addr), 168 "ldd [$addr], $dst", 169 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 170def LDDFri : F3_2<3, 0b100011, 171 (ops DFPRegs:$dst, MEMri:$addr), 172 "ldd [$addr], $dst", 173 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 174 175// Section B.4 - Store Integer Instructions, p. 95 176def STBrr : F3_1<3, 0b000101, 177 (ops MEMrr:$addr, IntRegs:$src), 178 "stb $src, [$addr]", 179 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 180def STBri : F3_2<3, 0b000101, 181 (ops MEMri:$addr, IntRegs:$src), 182 "stb $src, [$addr]", 183 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 184def STHrr : F3_1<3, 0b000110, 185 (ops MEMrr:$addr, IntRegs:$src), 186 "sth $src, [$addr]", 187 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 188def STHri : F3_2<3, 0b000110, 189 (ops MEMri:$addr, IntRegs:$src), 190 "sth $src, [$addr]", 191 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 192def STrr : F3_1<3, 0b000100, 193 (ops MEMrr:$addr, IntRegs:$src), 194 "st $src, [$addr]", 195 [(store IntRegs:$src, ADDRrr:$addr)]>; 196def STri : F3_2<3, 0b000100, 197 (ops MEMri:$addr, IntRegs:$src), 198 "st $src, [$addr]", 199 [(store IntRegs:$src, ADDRri:$addr)]>; 200def STDrr : F3_1<3, 0b000111, 201 (ops MEMrr:$addr, IntRegs:$src), 202 "std $src, [$addr]", []>; 203def STDri : F3_2<3, 0b000111, 204 (ops MEMri:$addr, IntRegs:$src), 205 "std $src, [$addr]", []>; 206 207// Section B.5 - Store Floating-point Instructions, p. 97 208def STFrr : F3_1<3, 0b100100, 209 (ops MEMrr:$addr, IntRegs:$src), 210 "st $src, [$addr]", []>; 211def STFri : F3_2<3, 0b100100, 212 (ops MEMri:$addr, IntRegs:$src), 213 "st $src, [$addr]", []>; 214def STDFrr : F3_1<3, 0b100111, 215 (ops MEMrr:$addr, IntRegs:$src), 216 "std $src, [$addr]", []>; 217def STDFri : F3_2<3, 0b100111, 218 (ops MEMri:$addr, IntRegs:$src), 219 "std $src, [$addr]", []>; 220def STFSRrr : F3_1<3, 0b100101, 221 (ops MEMrr:$addr, IntRegs:$src), 222 "st $src, [$addr]", []>; 223def STFSRri : F3_2<3, 0b100101, 224 (ops MEMri:$addr, IntRegs:$src), 225 "st $src, [$addr]", []>; 226def STDFQrr : F3_1<3, 0b100110, 227 (ops MEMrr:$addr, IntRegs:$src), 228 "std $src, [$addr]", []>; 229def STDFQri : F3_2<3, 0b100110, 230 (ops MEMri:$addr, IntRegs:$src), 231 "std $src, [$addr]", []>; 232 233// Section B.9 - SETHI Instruction, p. 104 234def SETHIi: F2_1<0b100, 235 (ops IntRegs:$dst, i32imm:$src), 236 "sethi $src, $dst", 237 [(set IntRegs:$dst, SETHIimm:$src)]>; 238 239// Section B.10 - NOP Instruction, p. 105 240// (It's a special case of SETHI) 241let rd = 0, imm22 = 0 in 242 def NOP : F2_1<0b100, (ops), "nop", []>; 243 244// Section B.11 - Logical Instructions, p. 106 245def ANDrr : F3_1<2, 0b000001, 246 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 247 "and $b, $c, $dst", 248 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 249def ANDri : F3_2<2, 0b000001, 250 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 251 "and $b, $c, $dst", 252 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 253def ANDCCrr : F3_1<2, 0b010001, 254 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 255 "andcc $b, $c, $dst", []>; 256def ANDCCri : F3_2<2, 0b010001, 257 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 258 "andcc $b, $c, $dst", []>; 259def ANDNrr : F3_1<2, 0b000101, 260 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 261 "andn $b, $c, $dst", []>; 262def ANDNri : F3_2<2, 0b000101, 263 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 264 "andn $b, $c, $dst", []>; 265def ANDNCCrr: F3_1<2, 0b010101, 266 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 267 "andncc $b, $c, $dst", []>; 268def ANDNCCri: F3_2<2, 0b010101, 269 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 270 "andncc $b, $c, $dst", []>; 271def ORrr : F3_1<2, 0b000010, 272 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 273 "or $b, $c, $dst", 274 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 275def ORri : F3_2<2, 0b000010, 276 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 277 "or $b, $c, $dst", 278 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 279def ORCCrr : F3_1<2, 0b010010, 280 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 281 "orcc $b, $c, $dst", []>; 282def ORCCri : F3_2<2, 0b010010, 283 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 284 "orcc $b, $c, $dst", []>; 285def ORNrr : F3_1<2, 0b000110, 286 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 287 "orn $b, $c, $dst", []>; 288def ORNri : F3_2<2, 0b000110, 289 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 290 "orn $b, $c, $dst", []>; 291def ORNCCrr : F3_1<2, 0b010110, 292 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 293 "orncc $b, $c, $dst", []>; 294def ORNCCri : F3_2<2, 0b010110, 295 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 296 "orncc $b, $c, $dst", []>; 297def XORrr : F3_1<2, 0b000011, 298 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 299 "xor $b, $c, $dst", 300 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 301def XORri : F3_2<2, 0b000011, 302 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 303 "xor $b, $c, $dst", 304 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 305def XORCCrr : F3_1<2, 0b010011, 306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 307 "xorcc $b, $c, $dst", []>; 308def XORCCri : F3_2<2, 0b010011, 309 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 310 "xorcc $b, $c, $dst", []>; 311def XNORrr : F3_1<2, 0b000111, 312 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 313 "xnor $b, $c, $dst", []>; 314def XNORri : F3_2<2, 0b000111, 315 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 316 "xnor $b, $c, $dst", []>; 317def XNORCCrr: F3_1<2, 0b010111, 318 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 319 "xnorcc $b, $c, $dst", []>; 320def XNORCCri: F3_2<2, 0b010111, 321 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 322 "xnorcc $b, $c, $dst", []>; 323 324// Section B.12 - Shift Instructions, p. 107 325def SLLrr : F3_1<2, 0b100101, 326 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 327 "sll $b, $c, $dst", 328 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 329def SLLri : F3_2<2, 0b100101, 330 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 331 "sll $b, $c, $dst", 332 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 333def SRLrr : F3_1<2, 0b100110, 334 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 335 "srl $b, $c, $dst", 336 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 337def SRLri : F3_2<2, 0b100110, 338 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 339 "srl $b, $c, $dst", 340 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 341def SRArr : F3_1<2, 0b100111, 342 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 343 "sra $b, $c, $dst", 344 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 345def SRAri : F3_2<2, 0b100111, 346 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 347 "sra $b, $c, $dst", 348 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 349 350// Section B.13 - Add Instructions, p. 108 351def ADDrr : F3_1<2, 0b000000, 352 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 353 "add $b, $c, $dst", 354 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 355def ADDri : F3_2<2, 0b000000, 356 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 357 "add $b, $c, $dst", 358 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 359def ADDCCrr : F3_1<2, 0b010000, 360 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 361 "addcc $b, $c, $dst", []>; 362def ADDCCri : F3_2<2, 0b010000, 363 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 364 "addcc $b, $c, $dst", []>; 365def ADDXrr : F3_1<2, 0b001000, 366 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 367 "addx $b, $c, $dst", []>; 368def ADDXri : F3_2<2, 0b001000, 369 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 370 "addx $b, $c, $dst", []>; 371def ADDXCCrr: F3_1<2, 0b011000, 372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 373 "addxcc $b, $c, $dst", []>; 374def ADDXCCri: F3_2<2, 0b011000, 375 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 376 "addxcc $b, $c, $dst", []>; 377 378// Section B.15 - Subtract Instructions, p. 110 379def SUBrr : F3_1<2, 0b000100, 380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 381 "sub $b, $c, $dst", 382 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 383def SUBri : F3_2<2, 0b000100, 384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 385 "sub $b, $c, $dst", 386 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 387def SUBCCrr : F3_1<2, 0b010100, 388 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 389 "subcc $b, $c, $dst", []>; 390def SUBCCri : F3_2<2, 0b010100, 391 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 392 "subcc $b, $c, $dst", []>; 393def SUBXrr : F3_1<2, 0b001100, 394 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 395 "subx $b, $c, $dst", []>; 396def SUBXri : F3_2<2, 0b001100, 397 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 398 "subx $b, $c, $dst", []>; 399def SUBXCCrr: F3_1<2, 0b011100, 400 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 401 "subxcc $b, $c, $dst", []>; 402def SUBXCCri: F3_2<2, 0b011100, 403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 404 "subxcc $b, $c, $dst", []>; 405 406// Section B.18 - Multiply Instructions, p. 113 407def UMULrr : F3_1<2, 0b001010, 408 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 409 "umul $b, $c, $dst", []>; 410def UMULri : F3_2<2, 0b001010, 411 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 412 "umul $b, $c, $dst", []>; 413def SMULrr : F3_1<2, 0b001011, 414 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 415 "smul $b, $c, $dst", []>; 416def SMULri : F3_2<2, 0b001011, 417 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 418 "smul $b, $c, $dst", []>; 419def UMULCCrr: F3_1<2, 0b011010, 420 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 421 "umulcc $b, $c, $dst", []>; 422def UMULCCri: F3_2<2, 0b011010, 423 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 424 "umulcc $b, $c, $dst", []>; 425def SMULCCrr: F3_1<2, 0b011011, 426 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 427 "smulcc $b, $c, $dst", []>; 428def SMULCCri: F3_2<2, 0b011011, 429 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 430 "smulcc $b, $c, $dst", []>; 431 432// Section B.19 - Divide Instructions, p. 115 433def UDIVrr : F3_1<2, 0b001110, 434 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 435 "udiv $b, $c, $dst", []>; 436def UDIVri : F3_2<2, 0b001110, 437 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 438 "udiv $b, $c, $dst", []>; 439def SDIVrr : F3_1<2, 0b001111, 440 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 441 "sdiv $b, $c, $dst", []>; 442def SDIVri : F3_2<2, 0b001111, 443 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 444 "sdiv $b, $c, $dst", []>; 445def UDIVCCrr : F3_1<2, 0b011110, 446 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 447 "udivcc $b, $c, $dst", []>; 448def UDIVCCri : F3_2<2, 0b011110, 449 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 450 "udivcc $b, $c, $dst", []>; 451def SDIVCCrr : F3_1<2, 0b011111, 452 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 453 "sdivcc $b, $c, $dst", []>; 454def SDIVCCri : F3_2<2, 0b011111, 455 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 456 "sdivcc $b, $c, $dst", []>; 457 458// Section B.20 - SAVE and RESTORE, p. 117 459def SAVErr : F3_1<2, 0b111100, 460 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 461 "save $b, $c, $dst", []>; 462def SAVEri : F3_2<2, 0b111100, 463 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 464 "save $b, $c, $dst", []>; 465def RESTORErr : F3_1<2, 0b111101, 466 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 467 "restore $b, $c, $dst", []>; 468def RESTOREri : F3_2<2, 0b111101, 469 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 470 "restore $b, $c, $dst", []>; 471 472// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 473 474// conditional branch class: 475class BranchV8<bits<4> cc, dag ops, string asmstr> 476 : F2_2<cc, 0b010, ops, asmstr> { 477 let isBranch = 1; 478 let isTerminator = 1; 479 let hasDelaySlot = 1; 480} 481 482let isBarrier = 1 in 483 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">; 484def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">; 485def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">; 486def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">; 487def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">; 488def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">; 489def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">; 490def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">; 491def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">; 492def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">; 493def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">; 494def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">; 495 496// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 497 498// floating-point conditional branch class: 499class FPBranchV8<bits<4> cc, dag ops, string asmstr> 500 : F2_2<cc, 0b110, ops, asmstr> { 501 let isBranch = 1; 502 let isTerminator = 1; 503 let hasDelaySlot = 1; 504} 505 506def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">; 507def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">; 508def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">; 509def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">; 510def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">; 511def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">; 512def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">; 513def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">; 514def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">; 515def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">; 516def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">; 517def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">; 518def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">; 519def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">; 520def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">; 521def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">; 522 523 524 525// Section B.24 - Call and Link Instruction, p. 125 526// This is the only Format 1 instruction 527let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 528 // pc-relative call: 529 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 530 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 531 def CALL : InstV8 { 532 let OperandList = (ops IntRegs:$dst); 533 bits<30> disp; 534 let op = 1; 535 let Inst{29-0} = disp; 536 let AsmString = "call $dst"; 537 } 538 539 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 540 // be an implicit def): 541 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 542 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 543 def JMPLrr : F3_1<2, 0b111000, 544 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 545 "jmpl $b+$c, $dst", []>; 546} 547 548// Section B.29 - Write State Register Instructions 549def WRrr : F3_1<2, 0b110000, 550 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 551 "wr $b, $c, $dst", []>; 552def WRri : F3_2<2, 0b110000, 553 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 554 "wr $b, $c, $dst", []>; 555 556// Convert Integer to Floating-point Instructions, p. 141 557def FITOS : F3_3<2, 0b110100, 0b011000100, 558 (ops FPRegs:$dst, FPRegs:$src), 559 "fitos $src, $dst">; 560def FITOD : F3_3<2, 0b110100, 0b011001000, 561 (ops DFPRegs:$dst, DFPRegs:$src), 562 "fitod $src, $dst">; 563 564// Convert Floating-point to Integer Instructions, p. 142 565def FSTOI : F3_3<2, 0b110100, 0b011010001, 566 (ops FPRegs:$dst, FPRegs:$src), 567 "fstoi $src, $dst">; 568def FDTOI : F3_3<2, 0b110100, 0b011010010, 569 (ops DFPRegs:$dst, DFPRegs:$src), 570 "fdtoi $src, $dst">; 571 572// Convert between Floating-point Formats Instructions, p. 143 573def FSTOD : F3_3<2, 0b110100, 0b011001001, 574 (ops DFPRegs:$dst, FPRegs:$src), 575 "fstod $src, $dst">; 576def FDTOS : F3_3<2, 0b110100, 0b011000110, 577 (ops FPRegs:$dst, DFPRegs:$src), 578 "fdtos $src, $dst">; 579 580// Floating-point Move Instructions, p. 144 581def FMOVS : F3_3<2, 0b110100, 0b000000001, 582 (ops FPRegs:$dst, FPRegs:$src), 583 "fmovs $src, $dst">; 584def FNEGS : F3_3<2, 0b110100, 0b000000101, 585 (ops FPRegs:$dst, FPRegs:$src), 586 "fnegs $src, $dst">; 587def FABSS : F3_3<2, 0b110100, 0b000001001, 588 (ops FPRegs:$dst, FPRegs:$src), 589 "fabss $src, $dst">; 590 591// Floating-point Add and Subtract Instructions, p. 146 592def FADDS : F3_3<2, 0b110100, 0b001000001, 593 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 594 "fadds $src1, $src2, $dst">; 595def FADDD : F3_3<2, 0b110100, 0b001000010, 596 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 597 "faddd $src1, $src2, $dst">; 598def FSUBS : F3_3<2, 0b110100, 0b001000101, 599 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 600 "fsubs $src1, $src2, $dst">; 601def FSUBD : F3_3<2, 0b110100, 0b001000110, 602 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 603 "fsubd $src1, $src2, $dst">; 604 605// Floating-point Multiply and Divide Instructions, p. 147 606def FMULS : F3_3<2, 0b110100, 0b001001001, 607 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 608 "fmuls $src1, $src2, $dst">; 609def FMULD : F3_3<2, 0b110100, 0b001001010, 610 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 611 "fmuld $src1, $src2, $dst">; 612def FSMULD : F3_3<2, 0b110100, 0b001101001, 613 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 614 "fsmuld $src1, $src2, $dst">; 615def FDIVS : F3_3<2, 0b110100, 0b001001101, 616 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 617 "fdivs $src1, $src2, $dst">; 618def FDIVD : F3_3<2, 0b110100, 0b001001110, 619 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 620 "fdivd $src1, $src2, $dst">; 621 622// Floating-point Compare Instructions, p. 148 623// Note: the 2nd template arg is different for these guys. 624// Note 2: the result of a FCMP is not available until the 2nd cycle 625// after the instr is retired, but there is no interlock. This behavior 626// is modelled with a forced noop after the instruction. 627def FCMPS : F3_3<2, 0b110101, 0b001010001, 628 (ops FPRegs:$src1, FPRegs:$src2), 629 "fcmps $src1, $src2\n\tnop">; 630def FCMPD : F3_3<2, 0b110101, 0b001010010, 631 (ops DFPRegs:$src1, DFPRegs:$src2), 632 "fcmpd $src1, $src2\n\tnop">; 633def FCMPES : F3_3<2, 0b110101, 0b001010101, 634 (ops FPRegs:$src1, FPRegs:$src2), 635 "fcmpes $src1, $src2\n\tnop">; 636def FCMPED : F3_3<2, 0b110101, 0b001010110, 637 (ops DFPRegs:$src1, DFPRegs:$src2), 638 "fcmped $src1, $src2\n\tnop">; 639 640//===----------------------------------------------------------------------===// 641// Non-Instruction Patterns 642//===----------------------------------------------------------------------===// 643 644// Small immediates. 645def : Pat<(i32 simm13:$val), 646 (ORri G0, imm:$val)>; 647// Arbitrary immediates. 648def : Pat<(i32 imm:$val), 649 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 650