SparcRegisterInfo.cpp revision 1e06bcbd633175d75d13aaa5695ca0633ba86068 
1//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcRegisterInfo.h"
15#include "Sparc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcSubtarget.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/IR/Type.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Target/TargetInstrInfo.h"
27
28#define GET_REGINFO_TARGET_DESC
29#include "SparcGenRegisterInfo.inc"
30
31using namespace llvm;
32
33static cl::opt<bool>
34ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
35                    cl::desc("Reserve application registers (%g2-%g4)"));
36
37SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
38                                     const TargetInstrInfo &tii)
39  : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
40}
41
42const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
43                                                                         const {
44  static const uint16_t CalleeSavedRegs[] = { 0 };
45  return CalleeSavedRegs;
46}
47
48BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
49  BitVector Reserved(getNumRegs());
50  // FIXME: G1 reserved for now for large imm generation by frame code.
51  Reserved.set(SP::G1);
52
53  // G1-G4 can be used in applications.
54  if (ReserveAppRegisters) {
55    Reserved.set(SP::G2);
56    Reserved.set(SP::G3);
57    Reserved.set(SP::G4);
58  }
59  // G5 is not reserved in 64 bit mode.
60  if (!Subtarget.is64Bit())
61    Reserved.set(SP::G5);
62
63  Reserved.set(SP::O6);
64  Reserved.set(SP::I6);
65  Reserved.set(SP::I7);
66  Reserved.set(SP::G0);
67  Reserved.set(SP::G6);
68  Reserved.set(SP::G7);
69  return Reserved;
70}
71
72const TargetRegisterClass*
73SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
74                                      unsigned Kind) const {
75  return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
76}
77
78void
79SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
80                                       int SPAdj, unsigned FIOperandNum,
81                                       RegScavenger *RS) const {
82  assert(SPAdj == 0 && "Unexpected");
83
84  MachineInstr &MI = *II;
85  DebugLoc dl = MI.getDebugLoc();
86  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
87
88  // Addressable stack objects are accessed using neg. offsets from %fp
89  MachineFunction &MF = *MI.getParent()->getParent();
90  int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
91                   MI.getOperand(FIOperandNum + 1).getImm() +
92                   Subtarget.getStackPointerBias();
93  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
94  unsigned FramePtr = SP::I6;
95  if (FuncInfo->isLeafProc()) {
96    // Use %sp and adjust offset if needed.
97    FramePtr = SP::O6;
98    int stackSize = MF.getFrameInfo()->getStackSize();
99    Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
100  }
101
102  // Replace frame index with a frame pointer reference.
103  if (Offset >= -4096 && Offset <= 4095) {
104    // If the offset is small enough to fit in the immediate field, directly
105    // encode it.
106    MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
107    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
108  } else {
109    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
110    // scavenge a register here instead of reserving G1 all of the time.
111    unsigned OffHi = (unsigned)Offset >> 10U;
112    BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
113    // Emit G1 = G1 + I6
114    BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
115      .addReg(FramePtr);
116    // Insert: G1+%lo(offset) into the user.
117    MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
118    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
119  }
120}
121
122unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
123  return SP::I6;
124}
125
126unsigned SparcRegisterInfo::getEHExceptionRegister() const {
127  llvm_unreachable("What is the exception register");
128}
129
130unsigned SparcRegisterInfo::getEHHandlerRegister() const {
131  llvm_unreachable("What is the exception handler register");
132}
133