SparcRegisterInfo.cpp revision 43dbe05279b753aabda571d9c83eaeb36987001a 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/STLExtras.h"
25using namespace llvm;
26
27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28                                     const TargetInstrInfo &tii)
29  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30    Subtarget(st), TII(tii) {
31}
32
33void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
34                                      MachineBasicBlock::iterator I,
35                                      unsigned DestReg,
36                                      const MachineInstr *Orig) const {
37  MachineInstr *MI = Orig->clone();
38  MI->getOperand(0).setReg(DestReg);
39  MBB.insert(I, MI);
40}
41
42const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
43                                                                         const {
44  static const unsigned CalleeSavedRegs[] = { 0 };
45  return CalleeSavedRegs;
46}
47
48BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
49  BitVector Reserved(getNumRegs());
50  Reserved.set(SP::G2);
51  Reserved.set(SP::G3);
52  Reserved.set(SP::G4);
53  Reserved.set(SP::O6);
54  Reserved.set(SP::I6);
55  Reserved.set(SP::I7);
56  Reserved.set(SP::G0);
57  Reserved.set(SP::G5);
58  Reserved.set(SP::G6);
59  Reserved.set(SP::G7);
60  return Reserved;
61}
62
63
64const TargetRegisterClass* const*
65SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
66  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
67  return CalleeSavedRegClasses;
68}
69
70bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
71  return false;
72}
73
74void SparcRegisterInfo::
75eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
76                              MachineBasicBlock::iterator I) const {
77  MachineInstr &MI = *I;
78  int Size = MI.getOperand(0).getImm();
79  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
80    Size = -Size;
81  if (Size)
82    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
83  MBB.erase(I);
84}
85
86void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
87                                            int SPAdj, RegScavenger *RS) const {
88  assert(SPAdj == 0 && "Unexpected");
89
90  unsigned i = 0;
91  MachineInstr &MI = *II;
92  while (!MI.getOperand(i).isFrameIndex()) {
93    ++i;
94    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
95  }
96
97  int FrameIndex = MI.getOperand(i).getIndex();
98
99  // Addressable stack objects are accessed using neg. offsets from %fp
100  MachineFunction &MF = *MI.getParent()->getParent();
101  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
102               MI.getOperand(i+1).getImm();
103
104  // Replace frame index with a frame pointer reference.
105  if (Offset >= -4096 && Offset <= 4095) {
106    // If the offset is small enough to fit in the immediate field, directly
107    // encode it.
108    MI.getOperand(i).ChangeToRegister(SP::I6, false);
109    MI.getOperand(i+1).ChangeToImmediate(Offset);
110  } else {
111    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
112    // scavenge a register here instead of reserving G1 all of the time.
113    unsigned OffHi = (unsigned)Offset >> 10U;
114    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
115    // Emit G1 = G1 + I6
116    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
117      .addReg(SP::I6);
118    // Insert: G1+%lo(offset) into the user.
119    MI.getOperand(i).ChangeToRegister(SP::G1, false);
120    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
121  }
122}
123
124void SparcRegisterInfo::
125processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
126
127void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
128  MachineBasicBlock &MBB = MF.front();
129  MachineFrameInfo *MFI = MF.getFrameInfo();
130
131  // Get the number of bytes to allocate from the FrameInfo
132  int NumBytes = (int) MFI->getStackSize();
133
134  // Emit the correct save instruction based on the number of bytes in
135  // the frame. Minimum stack frame size according to V8 ABI is:
136  //   16 words for register window spill
137  //    1 word for address of returned aggregate-value
138  // +  6 words for passing parameters on the stack
139  // ----------
140  //   23 words * 4 bytes per word = 92 bytes
141  NumBytes += 92;
142  // Round up to next doubleword boundary -- a double-word boundary
143  // is required by the ABI.
144  NumBytes = (NumBytes + 7) & ~7;
145  NumBytes = -NumBytes;
146
147  if (NumBytes >= -4096) {
148    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
149            SP::O6).addImm(NumBytes).addReg(SP::O6);
150  } else {
151    MachineBasicBlock::iterator InsertPt = MBB.begin();
152    // Emit this the hard way.  This clobbers G1 which we always know is
153    // available here.
154    unsigned OffHi = (unsigned)NumBytes >> 10U;
155    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
156    // Emit G1 = G1 + I6
157    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
158      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
159    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
160      .addReg(SP::O6).addReg(SP::G1);
161  }
162}
163
164void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
165                                     MachineBasicBlock &MBB) const {
166  MachineBasicBlock::iterator MBBI = prior(MBB.end());
167  assert(MBBI->getOpcode() == SP::RETL &&
168         "Can only put epilog before 'retl' instruction!");
169  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
170    .addReg(SP::G0);
171}
172
173unsigned SparcRegisterInfo::getRARegister() const {
174  assert(0 && "What is the return address register");
175  return 0;
176}
177
178unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
179  assert(0 && "What is the frame register");
180  return SP::G1;
181}
182
183unsigned SparcRegisterInfo::getEHExceptionRegister() const {
184  assert(0 && "What is the exception register");
185  return 0;
186}
187
188unsigned SparcRegisterInfo::getEHHandlerRegister() const {
189  assert(0 && "What is the exception handler register");
190  return 0;
191}
192
193int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
194  assert(0 && "What is the dwarf register number");
195  return -1;
196}
197
198#include "SparcGenRegisterInfo.inc"
199
200