SparcRegisterInfo.cpp revision 62819f31440fe1b1415473a89b8683b5b690d5fa 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/STLExtras.h"
25using namespace llvm;
26
27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28                                     const TargetInstrInfo &tii)
29  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30    Subtarget(st), TII(tii) {
31}
32
33void SparcRegisterInfo::
34storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35                    unsigned SrcReg, int FI,
36                    const TargetRegisterClass *RC) const {
37  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38  if (RC == SP::IntRegsRegisterClass)
39    BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40      .addReg(SrcReg);
41  else if (RC == SP::FPRegsRegisterClass)
42    BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43      .addReg(SrcReg);
44  else if (RC == SP::DFPRegsRegisterClass)
45    BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46      .addReg(SrcReg);
47  else
48    assert(0 && "Can't store this register to stack slot");
49}
50
51void SparcRegisterInfo::
52loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53                     unsigned DestReg, int FI,
54                     const TargetRegisterClass *RC) const {
55  if (RC == SP::IntRegsRegisterClass)
56    BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
57  else if (RC == SP::FPRegsRegisterClass)
58    BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
59  else if (RC == SP::DFPRegsRegisterClass)
60    BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
61  else
62    assert(0 && "Can't load this register from stack slot");
63}
64
65void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
66                                     MachineBasicBlock::iterator I,
67                                     unsigned DestReg, unsigned SrcReg,
68                                     const TargetRegisterClass *RC) const {
69  if (RC == SP::IntRegsRegisterClass)
70    BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
71  else if (RC == SP::FPRegsRegisterClass)
72    BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
73  else if (RC == SP::DFPRegsRegisterClass)
74    BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
75      .addReg(SrcReg);
76  else
77    assert (0 && "Can't copy this register");
78}
79
80MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
81                                                   unsigned OpNum,
82                                                   int FI) const {
83  bool isFloat = false;
84  MachineInstr *NewMI = NULL;
85  switch (MI->getOpcode()) {
86  case SP::ORrr:
87    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
88        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
89      if (OpNum == 0)    // COPY -> STORE
90        NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
91                                   .addReg(MI->getOperand(2).getReg());
92      else               // COPY -> LOAD
93        NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
94                      .addFrameIndex(FI).addImm(0);
95    }
96    break;
97  case SP::FMOVS:
98    isFloat = true;
99    // FALLTHROUGH
100  case SP::FMOVD:
101    if (OpNum == 0)  // COPY -> STORE
102      NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
103               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
104    else             // COPY -> LOAD
105      NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
106                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
107    break;
108  }
109
110  if (NewMI)
111    NewMI->copyKillDeadInfo(MI);
112  return NewMI;
113}
114
115const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
116  static const unsigned CalleeSavedRegs[] = { 0 };
117  return CalleeSavedRegs;
118}
119
120BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
121  BitVector Reserved(getNumRegs());
122  Reserved.set(SP::G2);
123  Reserved.set(SP::G3);
124  Reserved.set(SP::G4);
125  Reserved.set(SP::O6);
126  Reserved.set(SP::I6);
127  Reserved.set(SP::I7);
128  Reserved.set(SP::G0);
129  Reserved.set(SP::G5);
130  Reserved.set(SP::G6);
131  Reserved.set(SP::G7);
132  return Reserved;
133}
134
135
136const TargetRegisterClass* const*
137SparcRegisterInfo::getCalleeSavedRegClasses() const {
138  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
139  return CalleeSavedRegClasses;
140}
141
142bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
143  return false;
144}
145
146void SparcRegisterInfo::
147eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
148                              MachineBasicBlock::iterator I) const {
149  MachineInstr &MI = *I;
150  int Size = MI.getOperand(0).getImmedValue();
151  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
152    Size = -Size;
153  if (Size)
154    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
155  MBB.erase(I);
156}
157
158void
159SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
160  unsigned i = 0;
161  MachineInstr &MI = *II;
162  while (!MI.getOperand(i).isFrameIndex()) {
163    ++i;
164    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
165  }
166
167  int FrameIndex = MI.getOperand(i).getFrameIndex();
168
169  // Addressable stack objects are accessed using neg. offsets from %fp
170  MachineFunction &MF = *MI.getParent()->getParent();
171  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
172               MI.getOperand(i+1).getImmedValue();
173
174  // Replace frame index with a frame pointer reference.
175  if (Offset >= -4096 && Offset <= 4095) {
176    // If the offset is small enough to fit in the immediate field, directly
177    // encode it.
178    MI.getOperand(i).ChangeToRegister(SP::I6, false);
179    MI.getOperand(i+1).ChangeToImmediate(Offset);
180  } else {
181    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
182    // scavenge a register here instead of reserving G1 all of the time.
183    unsigned OffHi = (unsigned)Offset >> 10U;
184    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
185    // Emit G1 = G1 + I6
186    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
187      .addReg(SP::I6);
188    // Insert: G1+%lo(offset) into the user.
189    MI.getOperand(i).ChangeToRegister(SP::G1, false);
190    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
191  }
192}
193
194void SparcRegisterInfo::
195processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
196
197void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
198  MachineBasicBlock &MBB = MF.front();
199  MachineFrameInfo *MFI = MF.getFrameInfo();
200
201  // Get the number of bytes to allocate from the FrameInfo
202  int NumBytes = (int) MFI->getStackSize();
203
204  // Emit the correct save instruction based on the number of bytes in
205  // the frame. Minimum stack frame size according to V8 ABI is:
206  //   16 words for register window spill
207  //    1 word for address of returned aggregate-value
208  // +  6 words for passing parameters on the stack
209  // ----------
210  //   23 words * 4 bytes per word = 92 bytes
211  NumBytes += 92;
212  // Round up to next doubleword boundary -- a double-word boundary
213  // is required by the ABI.
214  NumBytes = (NumBytes + 7) & ~7;
215  NumBytes = -NumBytes;
216
217  if (NumBytes >= -4096) {
218    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
219            SP::O6).addImm(NumBytes).addReg(SP::O6);
220  } else {
221    MachineBasicBlock::iterator InsertPt = MBB.begin();
222    // Emit this the hard way.  This clobbers G1 which we always know is
223    // available here.
224    unsigned OffHi = (unsigned)NumBytes >> 10U;
225    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
226    // Emit G1 = G1 + I6
227    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
228      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
229    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
230      .addReg(SP::O6).addReg(SP::G1);
231  }
232}
233
234void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
235                                     MachineBasicBlock &MBB) const {
236  MachineBasicBlock::iterator MBBI = prior(MBB.end());
237  assert(MBBI->getOpcode() == SP::RETL &&
238         "Can only put epilog before 'retl' instruction!");
239  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
240    .addReg(SP::G0);
241}
242
243unsigned SparcRegisterInfo::getRARegister() const {
244  assert(0 && "What is the return address register");
245  return 0;
246}
247
248unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
249  assert(0 && "What is the frame register");
250  return SP::G1;
251}
252
253unsigned SparcRegisterInfo::getEHExceptionRegister() const {
254  assert(0 && "What is the exception register");
255  return 0;
256}
257
258unsigned SparcRegisterInfo::getEHHandlerRegister() const {
259  assert(0 && "What is the exception handler register");
260  return 0;
261}
262
263#include "SparcGenRegisterInfo.inc"
264
265