SparcRegisterInfo.cpp revision 74dfcf12000fcec60e1854f7bb78d481347a0a4b 
1//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SparcV8 implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8RegisterInfo.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/Type.h"
20#include "llvm/ADT/STLExtras.h"
21#include <iostream>
22using namespace llvm;
23
24SparcV8RegisterInfo::SparcV8RegisterInfo()
25  : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26                           V8::ADJCALLSTACKUP) {}
27
28void SparcV8RegisterInfo::
29storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
30                    unsigned SrcReg, int FrameIdx) const {
31  const TargetRegisterClass *RC = getRegClass(SrcReg);
32
33  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
34  if (RC == SparcV8::IntRegsRegisterClass)
35    BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
36      .addReg (SrcReg);
37  else if (RC == SparcV8::FPRegsRegisterClass)
38    BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
39      .addReg (SrcReg);
40  else if (RC == SparcV8::DFPRegsRegisterClass)
41    BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
42      .addReg (SrcReg);
43  else
44    assert (0 && "Can't store this register to stack slot");
45}
46
47void SparcV8RegisterInfo::
48loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
49                     unsigned DestReg, int FrameIdx) const {
50  const TargetRegisterClass *RC = getRegClass(DestReg);
51  if (RC == SparcV8::IntRegsRegisterClass)
52    BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
53  else if (RC == SparcV8::FPRegsRegisterClass)
54    BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
55      .addSImm (0);
56  else if (RC == SparcV8::DFPRegsRegisterClass)
57    BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
58      .addSImm (0);
59  else
60    assert(0 && "Can't load this register from stack slot");
61}
62
63void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
64                                       MachineBasicBlock::iterator I,
65                                       unsigned DestReg, unsigned SrcReg,
66                                       const TargetRegisterClass *RC) const {
67  if (RC == SparcV8::IntRegsRegisterClass)
68    BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
69  else if (RC == SparcV8::FPRegsRegisterClass)
70    BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
71  else
72    assert (0 && "Can't copy this register");
73}
74
75void SparcV8RegisterInfo::
76eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
77                              MachineBasicBlock::iterator I) const {
78  std::cerr
79    << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
80    << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
81  abort();
82}
83
84void
85SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
86  unsigned i = 0;
87  MachineInstr &MI = *II;
88  while (!MI.getOperand(i).isFrameIndex()) {
89    ++i;
90    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
91  }
92
93  int FrameIndex = MI.getOperand(i).getFrameIndex();
94
95  // Replace frame index with a frame pointer reference
96  MI.SetMachineOperandReg (i, V8::FP);
97
98  // Addressable stack objects are accessed using neg. offsets from %fp
99  MachineFunction &MF = *MI.getParent()->getParent();
100  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
101               MI.getOperand(i+1).getImmedValue();
102  // note: Offset < 0
103  MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
104}
105
106void SparcV8RegisterInfo::
107processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
108
109void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
110  MachineBasicBlock &MBB = MF.front();
111  MachineFrameInfo *MFI = MF.getFrameInfo();
112
113  // Get the number of bytes to allocate from the FrameInfo
114  int NumBytes = (int) MFI->getStackSize();
115
116  // Emit the correct save instruction based on the number of bytes in the frame.
117  // Minimum stack frame size according to V8 ABI is:
118  //   16 words for register window spill
119  //    1 word for address of returned aggregate-value
120  // +  6 words for passing parameters on the stack
121  // ----------
122  //   23 words * 4 bytes per word = 92 bytes
123  NumBytes += 92;
124  // Round up to next doubleword boundary -- a double-word boundary
125  // is required by the ABI.
126  NumBytes = (NumBytes + 7) & ~7;
127  BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
128          V8::SP).addImm(-NumBytes).addReg(V8::SP);
129}
130
131void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
132                                       MachineBasicBlock &MBB) const {
133  MachineBasicBlock::iterator MBBI = prior(MBB.end());
134  assert(MBBI->getOpcode() == V8::RETL &&
135         "Can only put epilog before 'retl' instruction!");
136  BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
137}
138
139#include "SparcV8GenRegisterInfo.inc"
140
141const TargetRegisterClass*
142SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
143  switch (Ty->getTypeID()) {
144  case Type::FloatTyID:  return &FPRegsInstance;
145  case Type::DoubleTyID: return &DFPRegsInstance;
146  case Type::LongTyID:
147  case Type::ULongTyID:  assert(0 && "Long values do not fit in registers!");
148  default:               assert(0 && "Invalid type to getClass!");
149  case Type::BoolTyID:
150  case Type::SByteTyID:
151  case Type::UByteTyID:
152  case Type::ShortTyID:
153  case Type::UShortTyID:
154  case Type::IntTyID:
155  case Type::UIntTyID:
156  case Type::PointerTyID: return &IntRegsInstance;
157  }
158}
159
160