SparcRegisterInfo.cpp revision 7c90f73a1b06040d971a3dd95a491031ae6238d5 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/Type.h"
21#include "llvm/ADT/STLExtras.h"
22#include <iostream>
23using namespace llvm;
24
25SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
26  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
27    Subtarget(st) {
28}
29
30void SparcRegisterInfo::
31storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
32                    unsigned SrcReg, int FI,
33                    const TargetRegisterClass *RC) const {
34  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
35  if (RC == SP::IntRegsRegisterClass)
36    BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
37  else if (RC == SP::FPRegsRegisterClass)
38    BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
39  else if (RC == SP::DFPRegsRegisterClass)
40    BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
41  else
42    assert(0 && "Can't store this register to stack slot");
43}
44
45void SparcRegisterInfo::
46loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
47                     unsigned DestReg, int FI,
48                     const TargetRegisterClass *RC) const {
49  if (RC == SP::IntRegsRegisterClass)
50    BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
51  else if (RC == SP::FPRegsRegisterClass)
52    BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
53  else if (RC == SP::DFPRegsRegisterClass)
54    BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
55  else
56    assert(0 && "Can't load this register from stack slot");
57}
58
59void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
60                                     MachineBasicBlock::iterator I,
61                                     unsigned DestReg, unsigned SrcReg,
62                                     const TargetRegisterClass *RC) const {
63  if (RC == SP::IntRegsRegisterClass)
64    BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
65  else if (RC == SP::FPRegsRegisterClass)
66    BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
67  else if (RC == SP::DFPRegsRegisterClass)
68    BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
69            1, DestReg).addReg(SrcReg);
70  else
71    assert (0 && "Can't copy this register");
72}
73
74MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
75                                                   unsigned OpNum,
76                                                   int FI) const {
77  bool isFloat = false;
78  switch (MI->getOpcode()) {
79  case SP::ORrr:
80    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
81        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
82      if (OpNum == 0)    // COPY -> STORE
83        return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
84                                   .addReg(MI->getOperand(2).getReg());
85      else               // COPY -> LOAD
86        return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
87                      .addFrameIndex(FI).addImm(0);
88    }
89    break;
90  case SP::FMOVS:
91    isFloat = true;
92    // FALLTHROUGH
93  case SP::FMOVD:
94    if (OpNum == 0)  // COPY -> STORE
95      return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
96               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
97    else             // COPY -> LOAD
98      return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
99                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
100    break;
101  }
102  return 0;
103}
104
105void SparcRegisterInfo::
106eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
107                              MachineBasicBlock::iterator I) const {
108  MachineInstr &MI = *I;
109  int Size = MI.getOperand(0).getImmedValue();
110  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
111    Size = -Size;
112  if (Size)
113    BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size);
114  MBB.erase(I);
115}
116
117void
118SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
119  unsigned i = 0;
120  MachineInstr &MI = *II;
121  while (!MI.getOperand(i).isFrameIndex()) {
122    ++i;
123    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
124  }
125
126  int FrameIndex = MI.getOperand(i).getFrameIndex();
127
128  // Addressable stack objects are accessed using neg. offsets from %fp
129  MachineFunction &MF = *MI.getParent()->getParent();
130  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
131               MI.getOperand(i+1).getImmedValue();
132
133  // Replace frame index with a frame pointer reference.
134  if (Offset >= -4096 && Offset <= 4095) {
135    // If the offset is small enough to fit in the immediate field, directly
136    // encode it.
137    MI.SetMachineOperandReg(i, SP::I6);
138    MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
139  } else {
140    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
141    // scavenge a register here instead of reserving G1 all of the time.
142    unsigned OffHi = (unsigned)Offset >> 10U;
143    BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
144    // Emit G1 = G1 + I6
145    BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
146            SP::G1).addReg(SP::G1).addReg(SP::I6);
147    // Insert: G1+%lo(offset) into the user.
148    MI.SetMachineOperandReg(i, SP::G1);
149    MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
150                              Offset & ((1 << 10)-1));
151  }
152}
153
154void SparcRegisterInfo::
155processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
156
157void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
158  MachineBasicBlock &MBB = MF.front();
159  MachineFrameInfo *MFI = MF.getFrameInfo();
160
161  // Get the number of bytes to allocate from the FrameInfo
162  int NumBytes = (int) MFI->getStackSize();
163
164  // Emit the correct save instruction based on the number of bytes in
165  // the frame. Minimum stack frame size according to V8 ABI is:
166  //   16 words for register window spill
167  //    1 word for address of returned aggregate-value
168  // +  6 words for passing parameters on the stack
169  // ----------
170  //   23 words * 4 bytes per word = 92 bytes
171  NumBytes += 92;
172  // Round up to next doubleword boundary -- a double-word boundary
173  // is required by the ABI.
174  NumBytes = (NumBytes + 7) & ~7;
175  NumBytes = -NumBytes;
176
177  if (NumBytes >= -4096) {
178    BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
179            SP::O6).addImm(NumBytes).addReg(SP::O6);
180  } else {
181    MachineBasicBlock::iterator InsertPt = MBB.begin();
182    // Emit this the hard way.  This clobbers G1 which we always know is
183    // available here.
184    unsigned OffHi = (unsigned)NumBytes >> 10U;
185    BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
186    // Emit G1 = G1 + I6
187    BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
188      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
189    BuildMI(MBB, InsertPt, SP::SAVErr, 2,
190            SP::O6).addReg(SP::O6).addReg(SP::G1);
191  }
192}
193
194void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
195                                     MachineBasicBlock &MBB) const {
196  MachineBasicBlock::iterator MBBI = prior(MBB.end());
197  assert(MBBI->getOpcode() == SP::RETL &&
198         "Can only put epilog before 'retl' instruction!");
199  BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
200}
201
202#include "SparcGenRegisterInfo.inc"
203
204