SparcRegisterInfo.cpp revision a284cbf667e11660840dc7bae3ee9eeaa3c7cbd2 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/STLExtras.h"
24using namespace llvm;
25
26SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
27                                     const TargetInstrInfo &tii)
28  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
29    Subtarget(st), TII(tii) {
30}
31
32void SparcRegisterInfo::
33storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
34                    unsigned SrcReg, int FI,
35                    const TargetRegisterClass *RC) const {
36  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
37  if (RC == SP::IntRegsRegisterClass)
38    BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
39      .addReg(SrcReg);
40  else if (RC == SP::FPRegsRegisterClass)
41    BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
42      .addReg(SrcReg);
43  else if (RC == SP::DFPRegsRegisterClass)
44    BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
45      .addReg(SrcReg);
46  else
47    assert(0 && "Can't store this register to stack slot");
48}
49
50void SparcRegisterInfo::
51loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
52                     unsigned DestReg, int FI,
53                     const TargetRegisterClass *RC) const {
54  if (RC == SP::IntRegsRegisterClass)
55    BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
56  else if (RC == SP::FPRegsRegisterClass)
57    BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
58  else if (RC == SP::DFPRegsRegisterClass)
59    BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
60  else
61    assert(0 && "Can't load this register from stack slot");
62}
63
64void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
65                                     MachineBasicBlock::iterator I,
66                                     unsigned DestReg, unsigned SrcReg,
67                                     const TargetRegisterClass *RC) const {
68  if (RC == SP::IntRegsRegisterClass)
69    BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
70  else if (RC == SP::FPRegsRegisterClass)
71    BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
72  else if (RC == SP::DFPRegsRegisterClass)
73    BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
74      .addReg(SrcReg);
75  else
76    assert (0 && "Can't copy this register");
77}
78
79MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
80                                                   unsigned OpNum,
81                                                   int FI) const {
82  bool isFloat = false;
83  MachineInstr *NewMI = NULL;
84  switch (MI->getOpcode()) {
85  case SP::ORrr:
86    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
87        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
88      if (OpNum == 0)    // COPY -> STORE
89        NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
90                                   .addReg(MI->getOperand(2).getReg());
91      else               // COPY -> LOAD
92        NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
93                      .addFrameIndex(FI).addImm(0);
94    }
95    break;
96  case SP::FMOVS:
97    isFloat = true;
98    // FALLTHROUGH
99  case SP::FMOVD:
100    if (OpNum == 0)  // COPY -> STORE
101      NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
102               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
103    else             // COPY -> LOAD
104      NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
105                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
106    break;
107  }
108
109  if (NewMI)
110    NewMI->copyKillDeadInfo(MI);
111  return NewMI;
112}
113
114const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
115  static const unsigned CalleeSavedRegs[] = { 0 };
116  return CalleeSavedRegs;
117}
118
119const TargetRegisterClass* const*
120SparcRegisterInfo::getCalleeSavedRegClasses() const {
121  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
122  return CalleeSavedRegClasses;
123}
124
125bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
126  return false;
127}
128
129void SparcRegisterInfo::
130eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
131                              MachineBasicBlock::iterator I) const {
132  MachineInstr &MI = *I;
133  int Size = MI.getOperand(0).getImmedValue();
134  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
135    Size = -Size;
136  if (Size)
137    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
138  MBB.erase(I);
139}
140
141void
142SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
143  unsigned i = 0;
144  MachineInstr &MI = *II;
145  while (!MI.getOperand(i).isFrameIndex()) {
146    ++i;
147    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
148  }
149
150  int FrameIndex = MI.getOperand(i).getFrameIndex();
151
152  // Addressable stack objects are accessed using neg. offsets from %fp
153  MachineFunction &MF = *MI.getParent()->getParent();
154  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
155               MI.getOperand(i+1).getImmedValue();
156
157  // Replace frame index with a frame pointer reference.
158  if (Offset >= -4096 && Offset <= 4095) {
159    // If the offset is small enough to fit in the immediate field, directly
160    // encode it.
161    MI.getOperand(i).ChangeToRegister(SP::I6, false);
162    MI.getOperand(i+1).ChangeToImmediate(Offset);
163  } else {
164    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
165    // scavenge a register here instead of reserving G1 all of the time.
166    unsigned OffHi = (unsigned)Offset >> 10U;
167    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
168    // Emit G1 = G1 + I6
169    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
170      .addReg(SP::I6);
171    // Insert: G1+%lo(offset) into the user.
172    MI.getOperand(i).ChangeToRegister(SP::G1, false);
173    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
174  }
175}
176
177void SparcRegisterInfo::
178processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
179
180void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
181  MachineBasicBlock &MBB = MF.front();
182  MachineFrameInfo *MFI = MF.getFrameInfo();
183
184  // Get the number of bytes to allocate from the FrameInfo
185  int NumBytes = (int) MFI->getStackSize();
186
187  // Emit the correct save instruction based on the number of bytes in
188  // the frame. Minimum stack frame size according to V8 ABI is:
189  //   16 words for register window spill
190  //    1 word for address of returned aggregate-value
191  // +  6 words for passing parameters on the stack
192  // ----------
193  //   23 words * 4 bytes per word = 92 bytes
194  NumBytes += 92;
195  // Round up to next doubleword boundary -- a double-word boundary
196  // is required by the ABI.
197  NumBytes = (NumBytes + 7) & ~7;
198  NumBytes = -NumBytes;
199
200  if (NumBytes >= -4096) {
201    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
202            SP::O6).addImm(NumBytes).addReg(SP::O6);
203  } else {
204    MachineBasicBlock::iterator InsertPt = MBB.begin();
205    // Emit this the hard way.  This clobbers G1 which we always know is
206    // available here.
207    unsigned OffHi = (unsigned)NumBytes >> 10U;
208    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
209    // Emit G1 = G1 + I6
210    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
211      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
212    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
213      .addReg(SP::O6).addReg(SP::G1);
214  }
215}
216
217void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
218                                     MachineBasicBlock &MBB) const {
219  MachineBasicBlock::iterator MBBI = prior(MBB.end());
220  assert(MBBI->getOpcode() == SP::RETL &&
221         "Can only put epilog before 'retl' instruction!");
222  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
223    .addReg(SP::G0);
224}
225
226unsigned SparcRegisterInfo::getRARegister() const {
227  assert(0 && "What is the return address register");
228  return 0;
229}
230
231unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
232  assert(0 && "What is the frame register");
233  return SP::G1;
234}
235
236#include "SparcGenRegisterInfo.inc"
237
238