SparcRegisterInfo.cpp revision b9c2fd964ee7dd7823ac71db8443055e4d0f1c15
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the SPARC implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcRegisterInfo.h" 16#include "SparcSubtarget.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineLocation.h" 21#include "llvm/Support/ErrorHandling.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Type.h" 24#include "llvm/ADT/BitVector.h" 25#include "llvm/ADT/STLExtras.h" 26using namespace llvm; 27 28SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, 29 const TargetInstrInfo &tii) 30 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 31 Subtarget(st), TII(tii) { 32} 33 34const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 35 const { 36 static const unsigned CalleeSavedRegs[] = { 0 }; 37 return CalleeSavedRegs; 38} 39 40BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 41 BitVector Reserved(getNumRegs()); 42 Reserved.set(SP::G2); 43 Reserved.set(SP::G3); 44 Reserved.set(SP::G4); 45 Reserved.set(SP::O6); 46 Reserved.set(SP::I6); 47 Reserved.set(SP::I7); 48 Reserved.set(SP::G0); 49 Reserved.set(SP::G5); 50 Reserved.set(SP::G6); 51 Reserved.set(SP::G7); 52 return Reserved; 53} 54 55 56const TargetRegisterClass* const* 57SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 58 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 }; 59 return CalleeSavedRegClasses; 60} 61 62bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const { 63 return false; 64} 65 66void SparcRegisterInfo:: 67eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 68 MachineBasicBlock::iterator I) const { 69 MachineInstr &MI = *I; 70 DebugLoc dl = MI.getDebugLoc(); 71 int Size = MI.getOperand(0).getImm(); 72 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 73 Size = -Size; 74 if (Size) 75 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); 76 MBB.erase(I); 77} 78 79unsigned 80SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 81 int SPAdj, int *Value, 82 RegScavenger *RS) const { 83 assert(SPAdj == 0 && "Unexpected"); 84 85 unsigned i = 0; 86 MachineInstr &MI = *II; 87 DebugLoc dl = MI.getDebugLoc(); 88 while (!MI.getOperand(i).isFI()) { 89 ++i; 90 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 91 } 92 93 int FrameIndex = MI.getOperand(i).getIndex(); 94 95 // Addressable stack objects are accessed using neg. offsets from %fp 96 MachineFunction &MF = *MI.getParent()->getParent(); 97 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 98 MI.getOperand(i+1).getImm(); 99 100 // Replace frame index with a frame pointer reference. 101 if (Offset >= -4096 && Offset <= 4095) { 102 // If the offset is small enough to fit in the immediate field, directly 103 // encode it. 104 MI.getOperand(i).ChangeToRegister(SP::I6, false); 105 MI.getOperand(i+1).ChangeToImmediate(Offset); 106 } else { 107 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to 108 // scavenge a register here instead of reserving G1 all of the time. 109 unsigned OffHi = (unsigned)Offset >> 10U; 110 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 111 // Emit G1 = G1 + I6 112 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 113 .addReg(SP::I6); 114 // Insert: G1+%lo(offset) into the user. 115 MI.getOperand(i).ChangeToRegister(SP::G1, false); 116 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); 117 } 118 return 0; 119} 120 121void SparcRegisterInfo:: 122processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 123 124void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { 125 MachineBasicBlock &MBB = MF.front(); 126 MachineFrameInfo *MFI = MF.getFrameInfo(); 127 MachineBasicBlock::iterator MBBI = MBB.begin(); 128 DebugLoc dl = (MBBI != MBB.end() ? 129 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 130 131 // Get the number of bytes to allocate from the FrameInfo 132 int NumBytes = (int) MFI->getStackSize(); 133 134 // Emit the correct save instruction based on the number of bytes in 135 // the frame. Minimum stack frame size according to V8 ABI is: 136 // 16 words for register window spill 137 // 1 word for address of returned aggregate-value 138 // + 6 words for passing parameters on the stack 139 // ---------- 140 // 23 words * 4 bytes per word = 92 bytes 141 NumBytes += 92; 142 143 // Round up to next doubleword boundary -- a double-word boundary 144 // is required by the ABI. 145 NumBytes = (NumBytes + 7) & ~7; 146 NumBytes = -NumBytes; 147 148 if (NumBytes >= -4096) { 149 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) 150 .addReg(SP::O6).addImm(NumBytes); 151 } else { 152 // Emit this the hard way. This clobbers G1 which we always know is 153 // available here. 154 unsigned OffHi = (unsigned)NumBytes >> 10U; 155 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 156 // Emit G1 = G1 + I6 157 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) 158 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); 159 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) 160 .addReg(SP::O6).addReg(SP::G1); 161 } 162} 163 164void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, 165 MachineBasicBlock &MBB) const { 166 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 167 DebugLoc dl = MBBI->getDebugLoc(); 168 assert(MBBI->getOpcode() == SP::RETL && 169 "Can only put epilog before 'retl' instruction!"); 170 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) 171 .addReg(SP::G0); 172} 173 174unsigned SparcRegisterInfo::getRARegister() const { 175 return SP::I7; 176} 177 178unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 179 return SP::I6; 180} 181 182unsigned SparcRegisterInfo::getEHExceptionRegister() const { 183 llvm_unreachable("What is the exception register"); 184 return 0; 185} 186 187unsigned SparcRegisterInfo::getEHHandlerRegister() const { 188 llvm_unreachable("What is the exception handler register"); 189 return 0; 190} 191 192int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 193 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 194} 195 196#include "SparcGenRegisterInfo.inc" 197 198