SparcRegisterInfo.cpp revision bf2c8b3c96f5c885095a10b0fcb29438f92d73c2
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the SPARC implementation of the MRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcRegisterInfo.h" 16#include "SparcSubtarget.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineLocation.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Type.h" 23#include "llvm/ADT/BitVector.h" 24#include "llvm/ADT/STLExtras.h" 25using namespace llvm; 26 27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, 28 const TargetInstrInfo &tii) 29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 30 Subtarget(st), TII(tii) { 31} 32 33void SparcRegisterInfo:: 34storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 35 unsigned SrcReg, int FI, 36 const TargetRegisterClass *RC) const { 37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 38 if (RC == SP::IntRegsRegisterClass) 39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0) 40 .addReg(SrcReg, false, false, true); 41 else if (RC == SP::FPRegsRegisterClass) 42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0) 43 .addReg(SrcReg, false, false, true); 44 else if (RC == SP::DFPRegsRegisterClass) 45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0) 46 .addReg(SrcReg, false, false, true); 47 else 48 assert(0 && "Can't store this register to stack slot"); 49} 50 51void SparcRegisterInfo:: 52loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 53 unsigned DestReg, int FI, 54 const TargetRegisterClass *RC) const { 55 if (RC == SP::IntRegsRegisterClass) 56 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 57 else if (RC == SP::FPRegsRegisterClass) 58 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); 59 else if (RC == SP::DFPRegsRegisterClass) 60 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); 61 else 62 assert(0 && "Can't load this register from stack slot"); 63} 64 65void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 66 MachineBasicBlock::iterator I, 67 unsigned DestReg, unsigned SrcReg, 68 const TargetRegisterClass *RC) const { 69 if (RC == SP::IntRegsRegisterClass) 70 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); 71 else if (RC == SP::FPRegsRegisterClass) 72 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg); 73 else if (RC == SP::DFPRegsRegisterClass) 74 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) 75 .addReg(SrcReg); 76 else 77 assert (0 && "Can't copy this register"); 78} 79 80void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator I, 82 unsigned DestReg, 83 const MachineInstr *Orig) const { 84 MachineInstr *MI = Orig->clone(); 85 MI->getOperand(0).setReg(DestReg); 86 MBB.insert(I, MI); 87} 88 89MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI, 90 unsigned OpNum, 91 int FI) const { 92 bool isFloat = false; 93 MachineInstr *NewMI = NULL; 94 switch (MI->getOpcode()) { 95 case SP::ORrr: 96 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& 97 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { 98 if (OpNum == 0) // COPY -> STORE 99 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0) 100 .addReg(MI->getOperand(2).getReg()); 101 else // COPY -> LOAD 102 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg()) 103 .addFrameIndex(FI).addImm(0); 104 } 105 break; 106 case SP::FMOVS: 107 isFloat = true; 108 // FALLTHROUGH 109 case SP::FMOVD: 110 if (OpNum == 0) // COPY -> STORE 111 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri)) 112 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg()); 113 else // COPY -> LOAD 114 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri), 115 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0); 116 break; 117 } 118 119 if (NewMI) 120 NewMI->copyKillDeadInfo(MI); 121 return NewMI; 122} 123 124const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const { 125 static const unsigned CalleeSavedRegs[] = { 0 }; 126 return CalleeSavedRegs; 127} 128 129BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 130 BitVector Reserved(getNumRegs()); 131 Reserved.set(SP::G2); 132 Reserved.set(SP::G3); 133 Reserved.set(SP::G4); 134 Reserved.set(SP::O6); 135 Reserved.set(SP::I6); 136 Reserved.set(SP::I7); 137 Reserved.set(SP::G0); 138 Reserved.set(SP::G5); 139 Reserved.set(SP::G6); 140 Reserved.set(SP::G7); 141 return Reserved; 142} 143 144 145const TargetRegisterClass* const* 146SparcRegisterInfo::getCalleeSavedRegClasses() const { 147 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 }; 148 return CalleeSavedRegClasses; 149} 150 151bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const { 152 return false; 153} 154 155void SparcRegisterInfo:: 156eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 157 MachineBasicBlock::iterator I) const { 158 MachineInstr &MI = *I; 159 int Size = MI.getOperand(0).getImmedValue(); 160 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 161 Size = -Size; 162 if (Size) 163 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); 164 MBB.erase(I); 165} 166 167void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 168 RegScavenger *RS) const { 169 unsigned i = 0; 170 MachineInstr &MI = *II; 171 while (!MI.getOperand(i).isFrameIndex()) { 172 ++i; 173 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 174 } 175 176 int FrameIndex = MI.getOperand(i).getFrameIndex(); 177 178 // Addressable stack objects are accessed using neg. offsets from %fp 179 MachineFunction &MF = *MI.getParent()->getParent(); 180 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 181 MI.getOperand(i+1).getImmedValue(); 182 183 // Replace frame index with a frame pointer reference. 184 if (Offset >= -4096 && Offset <= 4095) { 185 // If the offset is small enough to fit in the immediate field, directly 186 // encode it. 187 MI.getOperand(i).ChangeToRegister(SP::I6, false); 188 MI.getOperand(i+1).ChangeToImmediate(Offset); 189 } else { 190 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to 191 // scavenge a register here instead of reserving G1 all of the time. 192 unsigned OffHi = (unsigned)Offset >> 10U; 193 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 194 // Emit G1 = G1 + I6 195 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 196 .addReg(SP::I6); 197 // Insert: G1+%lo(offset) into the user. 198 MI.getOperand(i).ChangeToRegister(SP::G1, false); 199 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); 200 } 201} 202 203void SparcRegisterInfo:: 204processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 205 206void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { 207 MachineBasicBlock &MBB = MF.front(); 208 MachineFrameInfo *MFI = MF.getFrameInfo(); 209 210 // Get the number of bytes to allocate from the FrameInfo 211 int NumBytes = (int) MFI->getStackSize(); 212 213 // Emit the correct save instruction based on the number of bytes in 214 // the frame. Minimum stack frame size according to V8 ABI is: 215 // 16 words for register window spill 216 // 1 word for address of returned aggregate-value 217 // + 6 words for passing parameters on the stack 218 // ---------- 219 // 23 words * 4 bytes per word = 92 bytes 220 NumBytes += 92; 221 // Round up to next doubleword boundary -- a double-word boundary 222 // is required by the ABI. 223 NumBytes = (NumBytes + 7) & ~7; 224 NumBytes = -NumBytes; 225 226 if (NumBytes >= -4096) { 227 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri), 228 SP::O6).addImm(NumBytes).addReg(SP::O6); 229 } else { 230 MachineBasicBlock::iterator InsertPt = MBB.begin(); 231 // Emit this the hard way. This clobbers G1 which we always know is 232 // available here. 233 unsigned OffHi = (unsigned)NumBytes >> 10U; 234 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 235 // Emit G1 = G1 + I6 236 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1) 237 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); 238 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6) 239 .addReg(SP::O6).addReg(SP::G1); 240 } 241} 242 243void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, 244 MachineBasicBlock &MBB) const { 245 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 246 assert(MBBI->getOpcode() == SP::RETL && 247 "Can only put epilog before 'retl' instruction!"); 248 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) 249 .addReg(SP::G0); 250} 251 252unsigned SparcRegisterInfo::getRARegister() const { 253 assert(0 && "What is the return address register"); 254 return 0; 255} 256 257unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { 258 assert(0 && "What is the frame register"); 259 return SP::G1; 260} 261 262unsigned SparcRegisterInfo::getEHExceptionRegister() const { 263 assert(0 && "What is the exception register"); 264 return 0; 265} 266 267unsigned SparcRegisterInfo::getEHHandlerRegister() const { 268 assert(0 && "What is the exception handler register"); 269 return 0; 270} 271 272#include "SparcGenRegisterInfo.inc" 273 274