SparcRegisterInfo.cpp revision d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/STLExtras.h"
25using namespace llvm;
26
27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28                                     const TargetInstrInfo &tii)
29  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30    Subtarget(st), TII(tii) {
31}
32
33void SparcRegisterInfo::
34storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35                    unsigned SrcReg, bool isKill, int FI,
36                    const TargetRegisterClass *RC) const {
37  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38  if (RC == SP::IntRegsRegisterClass)
39    BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40      .addReg(SrcReg, false, false, isKill);
41  else if (RC == SP::FPRegsRegisterClass)
42    BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43      .addReg(SrcReg, false, false, isKill);
44  else if (RC == SP::DFPRegsRegisterClass)
45    BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46      .addReg(SrcReg, false, false, isKill);
47  else
48    assert(0 && "Can't store this register to stack slot");
49}
50
51void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
52                                       bool isKill,
53                                       SmallVectorImpl<MachineOperand> &Addr,
54                                       const TargetRegisterClass *RC,
55                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
56  unsigned Opc = 0;
57  if (RC == SP::IntRegsRegisterClass)
58    Opc = SP::STri;
59  else if (RC == SP::FPRegsRegisterClass)
60    Opc = SP::STFri;
61  else if (RC == SP::DFPRegsRegisterClass)
62    Opc = SP::STDFri;
63  else
64    assert(0 && "Can't load this register");
65  MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
66  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
67    MachineOperand &MO = Addr[i];
68    if (MO.isRegister())
69      MIB.addReg(MO.getReg());
70    else if (MO.isImmediate())
71      MIB.addImm(MO.getImmedValue());
72    else
73      MIB.addFrameIndex(MO.getFrameIndex());
74  }
75  MIB.addReg(SrcReg, false, false, isKill);
76  NewMIs.push_back(MIB);
77  return;
78}
79
80void SparcRegisterInfo::
81loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
82                     unsigned DestReg, int FI,
83                     const TargetRegisterClass *RC) const {
84  if (RC == SP::IntRegsRegisterClass)
85    BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
86  else if (RC == SP::FPRegsRegisterClass)
87    BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
88  else if (RC == SP::DFPRegsRegisterClass)
89    BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
90  else
91    assert(0 && "Can't load this register from stack slot");
92}
93
94void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
95                                        SmallVectorImpl<MachineOperand> &Addr,
96                                        const TargetRegisterClass *RC,
97                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
98  unsigned Opc = 0;
99  if (RC == SP::IntRegsRegisterClass)
100    Opc = SP::LDri;
101  else if (RC == SP::FPRegsRegisterClass)
102    Opc = SP::LDFri;
103  else if (RC == SP::DFPRegsRegisterClass)
104    Opc = SP::LDDFri;
105  else
106    assert(0 && "Can't load this register");
107  MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
108  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
109    MachineOperand &MO = Addr[i];
110    if (MO.isRegister())
111      MIB.addReg(MO.getReg());
112    else if (MO.isImmediate())
113      MIB.addImm(MO.getImmedValue());
114    else
115      MIB.addFrameIndex(MO.getFrameIndex());
116  }
117  NewMIs.push_back(MIB);
118  return;
119}
120
121void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
122                                     MachineBasicBlock::iterator I,
123                                     unsigned DestReg, unsigned SrcReg,
124                                     const TargetRegisterClass *DestRC,
125                                     const TargetRegisterClass *SrcRC) const {
126  if (DestRC != SrcRC) {
127    cerr << "Not yet supported!";
128    abort();
129  }
130
131  if (DestRC == SP::IntRegsRegisterClass)
132    BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
133  else if (DestRC == SP::FPRegsRegisterClass)
134    BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
135  else if (DestRC == SP::DFPRegsRegisterClass)
136    BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
137      .addReg(SrcReg);
138  else
139    assert (0 && "Can't copy this register");
140}
141
142void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
143                                      MachineBasicBlock::iterator I,
144                                      unsigned DestReg,
145                                      const MachineInstr *Orig) const {
146  MachineInstr *MI = Orig->clone();
147  MI->getOperand(0).setReg(DestReg);
148  MBB.insert(I, MI);
149}
150
151MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
152                                                 SmallVectorImpl<unsigned> &Ops,
153                                                 int FI) const {
154  if (Ops.size() != 1) return NULL;
155
156  unsigned OpNum = Ops[0];
157  bool isFloat = false;
158  MachineInstr *NewMI = NULL;
159  switch (MI->getOpcode()) {
160  case SP::ORrr:
161    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
162        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
163      if (OpNum == 0)    // COPY -> STORE
164        NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
165                                   .addReg(MI->getOperand(2).getReg());
166      else               // COPY -> LOAD
167        NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
168                      .addFrameIndex(FI).addImm(0);
169    }
170    break;
171  case SP::FMOVS:
172    isFloat = true;
173    // FALLTHROUGH
174  case SP::FMOVD:
175    if (OpNum == 0)  // COPY -> STORE
176      NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
177               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
178    else             // COPY -> LOAD
179      NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
180                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
181    break;
182  }
183
184  if (NewMI)
185    NewMI->copyKillDeadInfo(MI);
186  return NewMI;
187}
188
189const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
190                                                                         const {
191  static const unsigned CalleeSavedRegs[] = { 0 };
192  return CalleeSavedRegs;
193}
194
195BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
196  BitVector Reserved(getNumRegs());
197  Reserved.set(SP::G2);
198  Reserved.set(SP::G3);
199  Reserved.set(SP::G4);
200  Reserved.set(SP::O6);
201  Reserved.set(SP::I6);
202  Reserved.set(SP::I7);
203  Reserved.set(SP::G0);
204  Reserved.set(SP::G5);
205  Reserved.set(SP::G6);
206  Reserved.set(SP::G7);
207  return Reserved;
208}
209
210
211const TargetRegisterClass* const*
212SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
213  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
214  return CalleeSavedRegClasses;
215}
216
217bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
218  return false;
219}
220
221void SparcRegisterInfo::
222eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
223                              MachineBasicBlock::iterator I) const {
224  MachineInstr &MI = *I;
225  int Size = MI.getOperand(0).getImmedValue();
226  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
227    Size = -Size;
228  if (Size)
229    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
230  MBB.erase(I);
231}
232
233void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
234                                            int SPAdj, RegScavenger *RS) const {
235  assert(SPAdj == 0 && "Unexpected");
236
237  unsigned i = 0;
238  MachineInstr &MI = *II;
239  while (!MI.getOperand(i).isFrameIndex()) {
240    ++i;
241    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
242  }
243
244  int FrameIndex = MI.getOperand(i).getFrameIndex();
245
246  // Addressable stack objects are accessed using neg. offsets from %fp
247  MachineFunction &MF = *MI.getParent()->getParent();
248  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
249               MI.getOperand(i+1).getImmedValue();
250
251  // Replace frame index with a frame pointer reference.
252  if (Offset >= -4096 && Offset <= 4095) {
253    // If the offset is small enough to fit in the immediate field, directly
254    // encode it.
255    MI.getOperand(i).ChangeToRegister(SP::I6, false);
256    MI.getOperand(i+1).ChangeToImmediate(Offset);
257  } else {
258    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
259    // scavenge a register here instead of reserving G1 all of the time.
260    unsigned OffHi = (unsigned)Offset >> 10U;
261    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
262    // Emit G1 = G1 + I6
263    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
264      .addReg(SP::I6);
265    // Insert: G1+%lo(offset) into the user.
266    MI.getOperand(i).ChangeToRegister(SP::G1, false);
267    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
268  }
269}
270
271void SparcRegisterInfo::
272processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
273
274void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
275  MachineBasicBlock &MBB = MF.front();
276  MachineFrameInfo *MFI = MF.getFrameInfo();
277
278  // Get the number of bytes to allocate from the FrameInfo
279  int NumBytes = (int) MFI->getStackSize();
280
281  // Emit the correct save instruction based on the number of bytes in
282  // the frame. Minimum stack frame size according to V8 ABI is:
283  //   16 words for register window spill
284  //    1 word for address of returned aggregate-value
285  // +  6 words for passing parameters on the stack
286  // ----------
287  //   23 words * 4 bytes per word = 92 bytes
288  NumBytes += 92;
289  // Round up to next doubleword boundary -- a double-word boundary
290  // is required by the ABI.
291  NumBytes = (NumBytes + 7) & ~7;
292  NumBytes = -NumBytes;
293
294  if (NumBytes >= -4096) {
295    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
296            SP::O6).addImm(NumBytes).addReg(SP::O6);
297  } else {
298    MachineBasicBlock::iterator InsertPt = MBB.begin();
299    // Emit this the hard way.  This clobbers G1 which we always know is
300    // available here.
301    unsigned OffHi = (unsigned)NumBytes >> 10U;
302    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
303    // Emit G1 = G1 + I6
304    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
305      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
306    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
307      .addReg(SP::O6).addReg(SP::G1);
308  }
309}
310
311void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
312                                     MachineBasicBlock &MBB) const {
313  MachineBasicBlock::iterator MBBI = prior(MBB.end());
314  assert(MBBI->getOpcode() == SP::RETL &&
315         "Can only put epilog before 'retl' instruction!");
316  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
317    .addReg(SP::G0);
318}
319
320unsigned SparcRegisterInfo::getRARegister() const {
321  assert(0 && "What is the return address register");
322  return 0;
323}
324
325unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
326  assert(0 && "What is the frame register");
327  return SP::G1;
328}
329
330unsigned SparcRegisterInfo::getEHExceptionRegister() const {
331  assert(0 && "What is the exception register");
332  return 0;
333}
334
335unsigned SparcRegisterInfo::getEHHandlerRegister() const {
336  assert(0 && "What is the exception handler register");
337  return 0;
338}
339
340int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
341  assert(0 && "What is the dwarf register number");
342  return -1;
343}
344
345#include "SparcGenRegisterInfo.inc"
346
347