SparcRegisterInfo.cpp revision f6372aa1cc568df19da7c5023e83c75aa9404a07 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/STLExtras.h"
25using namespace llvm;
26
27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28                                     const TargetInstrInfo &tii)
29  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30    Subtarget(st), TII(tii) {
31}
32
33void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
34                                      MachineBasicBlock::iterator I,
35                                      unsigned DestReg,
36                                      const MachineInstr *Orig) const {
37  MachineInstr *MI = Orig->clone();
38  MI->getOperand(0).setReg(DestReg);
39  MBB.insert(I, MI);
40}
41
42MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
43                                                 SmallVectorImpl<unsigned> &Ops,
44                                                 int FI) const {
45  if (Ops.size() != 1) return NULL;
46
47  unsigned OpNum = Ops[0];
48  bool isFloat = false;
49  MachineInstr *NewMI = NULL;
50  switch (MI->getOpcode()) {
51  case SP::ORrr:
52    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
53        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
54      if (OpNum == 0)    // COPY -> STORE
55        NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
56                                   .addReg(MI->getOperand(2).getReg());
57      else               // COPY -> LOAD
58        NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
59                      .addFrameIndex(FI).addImm(0);
60    }
61    break;
62  case SP::FMOVS:
63    isFloat = true;
64    // FALLTHROUGH
65  case SP::FMOVD:
66    if (OpNum == 0)  // COPY -> STORE
67      NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
68               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
69    else             // COPY -> LOAD
70      NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
71                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
72    break;
73  }
74
75  if (NewMI)
76    NewMI->copyKillDeadInfo(MI);
77  return NewMI;
78}
79
80const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
81                                                                         const {
82  static const unsigned CalleeSavedRegs[] = { 0 };
83  return CalleeSavedRegs;
84}
85
86BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
87  BitVector Reserved(getNumRegs());
88  Reserved.set(SP::G2);
89  Reserved.set(SP::G3);
90  Reserved.set(SP::G4);
91  Reserved.set(SP::O6);
92  Reserved.set(SP::I6);
93  Reserved.set(SP::I7);
94  Reserved.set(SP::G0);
95  Reserved.set(SP::G5);
96  Reserved.set(SP::G6);
97  Reserved.set(SP::G7);
98  return Reserved;
99}
100
101
102const TargetRegisterClass* const*
103SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
104  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
105  return CalleeSavedRegClasses;
106}
107
108bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
109  return false;
110}
111
112void SparcRegisterInfo::
113eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
114                              MachineBasicBlock::iterator I) const {
115  MachineInstr &MI = *I;
116  int Size = MI.getOperand(0).getImm();
117  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
118    Size = -Size;
119  if (Size)
120    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
121  MBB.erase(I);
122}
123
124void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
125                                            int SPAdj, RegScavenger *RS) const {
126  assert(SPAdj == 0 && "Unexpected");
127
128  unsigned i = 0;
129  MachineInstr &MI = *II;
130  while (!MI.getOperand(i).isFrameIndex()) {
131    ++i;
132    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
133  }
134
135  int FrameIndex = MI.getOperand(i).getIndex();
136
137  // Addressable stack objects are accessed using neg. offsets from %fp
138  MachineFunction &MF = *MI.getParent()->getParent();
139  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
140               MI.getOperand(i+1).getImm();
141
142  // Replace frame index with a frame pointer reference.
143  if (Offset >= -4096 && Offset <= 4095) {
144    // If the offset is small enough to fit in the immediate field, directly
145    // encode it.
146    MI.getOperand(i).ChangeToRegister(SP::I6, false);
147    MI.getOperand(i+1).ChangeToImmediate(Offset);
148  } else {
149    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
150    // scavenge a register here instead of reserving G1 all of the time.
151    unsigned OffHi = (unsigned)Offset >> 10U;
152    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
153    // Emit G1 = G1 + I6
154    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
155      .addReg(SP::I6);
156    // Insert: G1+%lo(offset) into the user.
157    MI.getOperand(i).ChangeToRegister(SP::G1, false);
158    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
159  }
160}
161
162void SparcRegisterInfo::
163processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
164
165void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
166  MachineBasicBlock &MBB = MF.front();
167  MachineFrameInfo *MFI = MF.getFrameInfo();
168
169  // Get the number of bytes to allocate from the FrameInfo
170  int NumBytes = (int) MFI->getStackSize();
171
172  // Emit the correct save instruction based on the number of bytes in
173  // the frame. Minimum stack frame size according to V8 ABI is:
174  //   16 words for register window spill
175  //    1 word for address of returned aggregate-value
176  // +  6 words for passing parameters on the stack
177  // ----------
178  //   23 words * 4 bytes per word = 92 bytes
179  NumBytes += 92;
180  // Round up to next doubleword boundary -- a double-word boundary
181  // is required by the ABI.
182  NumBytes = (NumBytes + 7) & ~7;
183  NumBytes = -NumBytes;
184
185  if (NumBytes >= -4096) {
186    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
187            SP::O6).addImm(NumBytes).addReg(SP::O6);
188  } else {
189    MachineBasicBlock::iterator InsertPt = MBB.begin();
190    // Emit this the hard way.  This clobbers G1 which we always know is
191    // available here.
192    unsigned OffHi = (unsigned)NumBytes >> 10U;
193    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
194    // Emit G1 = G1 + I6
195    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
196      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
197    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
198      .addReg(SP::O6).addReg(SP::G1);
199  }
200}
201
202void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
203                                     MachineBasicBlock &MBB) const {
204  MachineBasicBlock::iterator MBBI = prior(MBB.end());
205  assert(MBBI->getOpcode() == SP::RETL &&
206         "Can only put epilog before 'retl' instruction!");
207  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
208    .addReg(SP::G0);
209}
210
211unsigned SparcRegisterInfo::getRARegister() const {
212  assert(0 && "What is the return address register");
213  return 0;
214}
215
216unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
217  assert(0 && "What is the frame register");
218  return SP::G1;
219}
220
221unsigned SparcRegisterInfo::getEHExceptionRegister() const {
222  assert(0 && "What is the exception register");
223  return 0;
224}
225
226unsigned SparcRegisterInfo::getEHHandlerRegister() const {
227  assert(0 && "What is the exception handler register");
228  return 0;
229}
230
231int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
232  assert(0 && "What is the dwarf register number");
233  return -1;
234}
235
236#include "SparcGenRegisterInfo.inc"
237
238