SparcRegisterInfo.td revision 1002013ed383e1083a5b63698ab215a2fd0f5d99 
1//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10//  Declarations that describe the SparcV8 register file 
11//
12//===----------------------------------------------------------------------===//
13
14// Registers are identified with 5-bit ID numbers.
15// Ri - 32-bit integer registers
16class Ri<bits<5> num, string name> : Register<name> {
17  field bits<5> Num = num;
18}
19// Rf - 32-bit floating-point registers
20class Rf<bits<5> num, string name> : Register<name> {
21  field bits<5> Num = num;
22}
23// Rd - Slots in the FP register file for 64-bit floating-point values.
24class Rd<bits<5> num, string name, list<Register> aliases>
25  : RegisterGroup<name, aliases> {
26  field bits<5> Num = num;
27}
28// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
29// WIM, TBR, etc registers
30class Rs<bits<5> num, string name> : Register<name> {
31  field bits<5> Num = num;
32}
33
34let Namespace = "V8" in {
35  def G0 : Ri< 0, "G0">;    def G1 : Ri< 1, "G1">;
36  def G2 : Ri< 2, "G2">;    def G3 : Ri< 3, "G3">;
37  def G4 : Ri< 4, "G4">;    def G5 : Ri< 5, "G5">;
38  def G6 : Ri< 6, "G6">;    def G7 : Ri< 7, "G7">;
39  def O0 : Ri< 8, "O0">;    def O1 : Ri< 9, "G1">;
40  def O2 : Ri<10, "O2">;    def O3 : Ri<11, "O3">;
41  def O4 : Ri<12, "O4">;    def O5 : Ri<13, "O5">;
42  def O6 : Ri<14, "O6">;    def O7 : Ri<15, "O7">;
43  def L0 : Ri<16, "L0">;    def L1 : Ri<17, "L1">;
44  def L2 : Ri<18, "L2">;    def L3 : Ri<19, "L3">;
45  def L4 : Ri<20, "L4">;    def L5 : Ri<21, "L5">;
46  def L6 : Ri<22, "L6">;    def L7 : Ri<23, "L7">;
47  def I0 : Ri<24, "I0">;    def I1 : Ri<25, "I1">;
48  def I2 : Ri<26, "I2">;    def I3 : Ri<27, "I3">;
49  def I4 : Ri<28, "I4">;    def I5 : Ri<29, "I5">;
50  def I6 : Ri<30, "I6">;    def I7 : Ri<31, "I7">;
51
52  // Standard register aliases.
53  def SP : Ri<14, "SP">;    def FP : Ri<30, "FP">;
54
55  // Floating-point registers:
56  def F0  : Rf< 0, "F0" >; def F1  : Rf< 1, "F1" >;
57  def F2  : Rf< 2, "F2" >; def F3  : Rf< 3, "F3" >;
58  def F4  : Rf< 4, "F4" >; def F5  : Rf< 5, "F5" >;
59  def F6  : Rf< 6, "F6" >; def F7  : Rf< 7, "F7" >;
60  def F8  : Rf< 8, "F8" >; def F9  : Rf< 9, "F9" >;
61  def F10 : Rf<10, "F10">; def F11 : Rf<11, "F11">;
62  def F12 : Rf<12, "F12">; def F13 : Rf<13, "F13">;
63  def F14 : Rf<14, "F14">; def F15 : Rf<15, "F15">;
64  def F16 : Rf<16, "F16">; def F17 : Rf<17, "F17">;
65  def F18 : Rf<18, "F18">; def F19 : Rf<19, "F19">;
66  def F20 : Rf<20, "F20">; def F21 : Rf<21, "F21">;
67  def F22 : Rf<22, "F22">; def F23 : Rf<23, "F23">;
68  def F24 : Rf<24, "F24">; def F25 : Rf<25, "F25">;
69  def F26 : Rf<26, "F26">; def F27 : Rf<27, "F27">;
70  def F28 : Rf<28, "F28">; def F29 : Rf<29, "F29">;
71  def F30 : Rf<30, "F30">; def F31 : Rf<31, "F31">;
72
73  // Aliases of the F* registers used to hold 64-bit fp values (doubles).  Make
74  // sure to tell the register file generator that the double-fp
75  // pseudo-registers alias the registers used for single-fp values.
76  def D0  : Rd< 0,  "F0", [ F0, F1]>;  def D1  : Rd< 2,  "F2", [ F2, F3]>;
77  def D2  : Rd< 4,  "F4", [ F4, F5]>;  def D3  : Rd< 6,  "F6", [ F6, F7]>;
78  def D4  : Rd< 8,  "F8", [ F8, F9]>;  def D5  : Rd<10, "F10", [F10,F11]>;
79  def D6  : Rd<12, "F12", [F12,F13]>;  def D7  : Rd<14, "F14", [F14,F15]>;
80  def D8  : Rd<16, "F16", [F16,F17]>;  def D9  : Rd<18, "F18", [F18,F19]>;
81  def D10 : Rd<20, "F20", [F20,F21]>;  def D11 : Rd<22, "F22", [F22,F23]>;
82  def D12 : Rd<24, "F24", [F24,F25]>;  def D13 : Rd<26, "F26", [F26,F27]>;
83  def D14 : Rd<28, "F28", [F28,F29]>;  def D15 : Rd<30, "F30", [F30,F31]>;
84
85  // The Y register.
86  def Y   : Rs<0, "Y">;
87}
88
89// Register classes.
90//
91// FIXME: the register order should be defined in terms of the preferred
92// allocation order...
93//
94def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
95                                     I0, I1, I2, I3, I4, I5,
96                                     G1, G2, G3, G4, G5, G6, G7,
97                                     O0, O1, O2, O3, O4, O5, O7,
98                                     // Non-allocatable regs
99                                     O6, I6, I7, G0]> {
100  let Methods = [{
101    iterator allocation_order_end(MachineFunction &MF) const {
102      return end()-4;  // Don't allocate special registers
103    }
104  }];
105}
106
107def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
108  F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
109  F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
110
111def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
112  D8, D9, D10, D11, D12, D13, D14, D15]>;
113
114