SparcRegisterInfo.td revision 4b92ed6d584aaa34eab7a3ef60d277617adb9aca 
1//===- SparcV8RegisterInfo.td - SparcV8 Register defs ------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Declarations that describe the SparcV8 register file 
12//===----------------------------------------------------------------------===//
13
14class SparcReg<string n> : Register<n> {
15  field bits<5> Num;
16  let Namespace = "V8";
17}
18
19include "../SparcRegisterInfo.td"
20
21// Register classes.
22//
23// FIXME: the register order should be defined in terms of the preferred
24// allocation order...
25//
26def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
27                                     I0, I1, I2, I3, I4, I5,
28                                     G1,
29                                     O0, O1, O2, O3, O4, O5, O7,
30                                     // Non-allocatable regs:
31                                     G2, G3, G4, // FIXME: OK for use only in
32                                                 // applications, not libraries.
33                                     O6, // stack ptr
34                                     I6, // frame ptr
35                                     I7, // return address
36                                     G0, // constant zero
37                                     G5, G6, G7 // reserved for kernel
38                                     ]> {
39  let Methods = [{
40    iterator allocation_order_end(MachineFunction &MF) const {
41      return end()-10;  // Don't allocate special registers
42    }
43  }];
44}
45
46def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
47  F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
48  F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
49
50def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
51  D8, D9, D10, D11, D12, D13, D14, D15]>;
52