SparcRegisterInfo.td revision db486a6d5311944f61b92db9f6074944dbbdb242
1//===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Sparc register file 12//===----------------------------------------------------------------------===// 13 14class SparcReg<string n> : Register<n> { 15 field bits<5> Num; 16 let Namespace = "SP"; 17} 18 19class SparcCtrlReg<string n>: Register<n> { 20 let Namespace = "SP"; 21} 22 23// Registers are identified with 5-bit ID numbers. 24// Ri - 32-bit integer registers 25class Ri<bits<5> num, string n> : SparcReg<n> { 26 let Num = num; 27} 28// Rf - 32-bit floating-point registers 29class Rf<bits<5> num, string n> : SparcReg<n> { 30 let Num = num; 31} 32// Rd - Slots in the FP register file for 64-bit floating-point values. 33class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { 34 let Num = num; 35 let SubRegs = subregs; 36} 37 38// Control Registers 39def ICC : SparcCtrlReg<"ICC">; 40def FCC : SparcCtrlReg<"FCC">; 41 42// Integer registers 43def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 44def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 45def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 46def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 47def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 48def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 49def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 50def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 51def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 52def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 53def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 54def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 55def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 56def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 57def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 58def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 59def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 60def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 61def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 62def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 63def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 64def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 65def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 66def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 67def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 68def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 69def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 70def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 71def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 72def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 73def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 74def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 75 76// Floating-point registers 77def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 78def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 79def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 80def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 81def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 82def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 83def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 84def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 85def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 86def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 87def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 88def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 89def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 90def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 91def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 92def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 93def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 94def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 95def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 96def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 97def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 98def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 99def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 100def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 101def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 102def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 103def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 104def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 105def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 106def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 107def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 108def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 109 110// Aliases of the F* registers used to hold 64-bit fp values (doubles) 111def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>; 112def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>; 113def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>; 114def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>; 115def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>; 116def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[42]>; 117def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[44]>; 118def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[46]>; 119def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[48]>; 120def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[50]>; 121def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[52]>; 122def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[54]>; 123def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[56]>; 124def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[58]>; 125def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[60]>; 126def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[62]>; 127 128// Register classes. 129// 130// FIXME: the register order should be defined in terms of the preferred 131// allocation order... 132// 133def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7, 134 I0, I1, I2, I3, I4, I5, 135 O0, O1, O2, O3, O4, O5, O7, 136 137 // FIXME: G1 reserved for now for large imm generation by frame code. 138 G1, 139 // Non-allocatable regs: 140 G2, G3, G4, // FIXME: OK for use only in 141 // applications, not libraries. 142 O6, // stack ptr 143 I6, // frame ptr 144 I7, // return address 145 G0, // constant zero 146 G5, G6, G7 // reserved for kernel 147 ]> { 148 let MethodProtos = [{ 149 iterator allocation_order_end(const MachineFunction &MF) const; 150 }]; 151 let MethodBodies = [{ 152 IntRegsClass::iterator 153 IntRegsClass::allocation_order_end(const MachineFunction &MF) const { 154 // FIXME: These special regs should be taken out of the regclass! 155 return end()-10 // Don't allocate special registers 156 -1; // FIXME: G1 reserved for large imm generation by frame code. 157 } 158 }]; 159} 160 161def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, 162 F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, 163 F23, F24, F25, F26, F27, F28, F29, F30, F31]>; 164 165def DFPRegs : RegisterClass<"SP", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, 166 D8, D9, D10, D11, D12, D13, D14, D15]>; 167