SparcRegisterInfo.td revision f54d912e32d19037391a59fc37336486b280187d 
1//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10//  Declarations that describe the SparcV8 register file 
11//
12//===----------------------------------------------------------------------===//
13
14// Registers are identified with 5-bit ID numbers.
15// Ri - 32-bit integer registers
16class Ri<bits<5> num> : Register {
17  field bits<5> Num = num;
18}
19// Rl - Slots in the integer register file for 64-bit integer values.
20class Rl<bits<5> num> : Register {
21  field bits<5> Num = num;
22}
23// Rf - 32-bit floating-point registers
24class Rf<bits<5> num> : Register {
25  field bits<5> Num = num;
26}
27// Rd - Slots in the FP register file for 64-bit floating-point values.
28class Rd<bits<5> num> : Register {
29  field bits<5> Num = num;
30}
31// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
32// WIM, TBR, etc registers
33class Rs<bits<5> num> : Register {
34  field bits<5> Num = num;
35}
36
37let Namespace = "V8" in {
38  def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
39  def G4 : Ri< 4>;    def G5 : Ri< 5>;    def G6 : Ri< 6>;    def G7 : Ri< 7>;
40  def O0 : Ri< 8>;    def O1 : Ri< 9>;    def O2 : Ri<10>;    def O3 : Ri<11>;
41  def O4 : Ri<12>;    def O5 : Ri<13>;    def O6 : Ri<14>;    def O7 : Ri<15>;
42  def L0 : Ri<16>;    def L1 : Ri<17>;    def L2 : Ri<18>;    def L3 : Ri<19>;
43  def L4 : Ri<20>;    def L5 : Ri<21>;    def L6 : Ri<22>;    def L7 : Ri<23>;
44  def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
45  def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
46
47  // Aliases of the Ri registers used to hold 64-bit integer values.
48  def LG2 : Rl< 2>; def LG4 : Rl< 4>; def LG6 : Rl< 6>;
49  def LO0 : Rl< 8>; def LO2 : Rl<10>; def LO4 : Rl<12>;
50  def LL0 : Rl<16>; def LL2 : Rl<18>; def LL4 : Rl<20>; def LL6 : Rl<22>;
51  def LI0 : Rl<24>; def LI2 : Rl<26>; def LI4 : Rl<28>;
52
53  // Standard register aliases.
54  def SP : Ri<14>;    def FP : Ri<30>;
55
56  // Floating-point registers:
57  def F0  : Rf< 0>; def F1  : Rf< 1>; def F2  : Rf< 2>; def F3  : Rf< 3>;
58  def F4  : Rf< 4>; def F5  : Rf< 5>; def F6  : Rf< 6>; def F7  : Rf< 7>;
59  def F8  : Rf< 8>; def F9  : Rf< 9>; def F10 : Rf<10>; def F11 : Rf<11>;
60  def F12 : Rf<12>; def F13 : Rf<13>; def F14 : Rf<14>; def F15 : Rf<15>;
61  def F16 : Rf<16>; def F17 : Rf<17>; def F18 : Rf<18>; def F19 : Rf<19>;
62  def F20 : Rf<20>; def F21 : Rf<21>; def F22 : Rf<22>; def F23 : Rf<23>;
63  def F24 : Rf<24>; def F25 : Rf<25>; def F26 : Rf<26>; def F27 : Rf<27>;
64  def F28 : Rf<28>; def F29 : Rf<29>; def F30 : Rf<30>; def F31 : Rf<31>;
65
66  // Aliases of the F* registers used to hold 64-bit fp values (doubles).
67  def D0  : Rd< 0>; def D1  : Rd< 2>; def D2  : Rd< 4>; def D3  : Rd< 6>;
68  def D4  : Rd< 8>; def D5  : Rd<10>; def D6  : Rd<12>; def D7  : Rd<14>;
69  def D8  : Rd<16>; def D9  : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>;
70  def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>;
71
72  // The Y register.
73  def Y   : Rs<0>;
74}
75
76
77// Register classes.
78//
79// FIXME: the register order should be defined in terms of the preferred
80// allocation order...
81//
82def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
83                                     I0, I1, I2, I3, I4, I5,
84                                     G1, G2, G3, G4, G5, G6, G7,
85                                     O0, O1, O2, O3, O4, O5, O7,
86                                     // Non-allocatable regs
87                                     O6, I6, I7, G0]> {
88  let Methods = [{
89    iterator allocation_order_end(MachineFunction &MF) const {
90      return end()-4;  // Don't allocate special registers
91    }
92  }];
93}
94
95def LongRegs : RegisterClass<i64, 8, [LL0, LL2, LL4, LL6, LI0, LI2,
96  LI4, LG2, LG4, LG6, LO0, LO2, LO4]>;
97
98def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
99  F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
100  F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
101
102def DFPRegs : RegisterClass<f64, 8, [D0, D1, D2, D3, D4, D5, D6, D7,
103  D8, D9, D10, D11, D12, D13, D14, D15]>;
104
105// Tell the register file generator that the double-fp pseudo-registers
106// alias the registers used for single-fp values.
107def : RegisterAliases<D0, [F0, F1]>;
108def : RegisterAliases<D1, [F2, F3]>;
109def : RegisterAliases<D2, [F4, F5]>;
110def : RegisterAliases<D3, [F6, F7]>;
111def : RegisterAliases<D4, [F8, F9]>;
112def : RegisterAliases<D5, [F10, F11]>;
113def : RegisterAliases<D6, [F12, F13]>;
114def : RegisterAliases<D7, [F14, F15]>;
115def : RegisterAliases<D8, [F16, F17]>;
116def : RegisterAliases<D9, [F18, F19]>;
117def : RegisterAliases<D10, [F20, F21]>;
118def : RegisterAliases<D11, [F22, F23]>;
119def : RegisterAliases<D12, [F24, F25]>;
120def : RegisterAliases<D13, [F26, F27]>;
121def : RegisterAliases<D14, [F28, F29]>;
122def : RegisterAliases<D15, [F30, F31]>;
123
124// Tell the register file generator that the long integer pseudo-registers
125// alias the registers used for single-word integer values.
126def : RegisterAliases<LL0, [L0, L1]>;
127def : RegisterAliases<LL2, [L2, L3]>;
128def : RegisterAliases<LL4, [L4, L5]>;
129def : RegisterAliases<LL6, [L6, L7]>;
130def : RegisterAliases<LI0, [I0, I1]>;
131def : RegisterAliases<LI2, [I2, I3]>;
132def : RegisterAliases<LI4, [I4, I5]>;
133def : RegisterAliases<LG2, [G2, G3]>;
134def : RegisterAliases<LG4, [G4, G5]>;
135def : RegisterAliases<LG6, [G6, G7]>;
136def : RegisterAliases<LO0, [O0, O1]>;
137def : RegisterAliases<LO2, [O2, O3]>;
138def : RegisterAliases<LO4, [O4, O5]>;
139