SystemZISelDAGToDAG.cpp revision 86a735396ab4804a06e76d1b4ce49dbd44c35827
1//===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SystemZ target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SystemZTargetMachine.h" 15#include "llvm/Analysis/AliasAnalysis.h" 16#include "llvm/CodeGen/SelectionDAGISel.h" 17#include "llvm/Support/Debug.h" 18#include "llvm/Support/raw_ostream.h" 19 20using namespace llvm; 21 22namespace { 23// Used to build addressing modes. 24struct SystemZAddressingMode { 25 // The shape of the address. 26 enum AddrForm { 27 // base+displacement 28 FormBD, 29 30 // base+displacement+index for load and store operands 31 FormBDXNormal, 32 33 // base+displacement+index for load address operands 34 FormBDXLA, 35 36 // base+displacement+index+ADJDYNALLOC 37 FormBDXDynAlloc 38 }; 39 AddrForm Form; 40 41 // The type of displacement. The enum names here correspond directly 42 // to the definitions in SystemZOperand.td. We could split them into 43 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it. 44 enum DispRange { 45 Disp12Only, 46 Disp12Pair, 47 Disp20Only, 48 Disp20Only128, 49 Disp20Pair 50 }; 51 DispRange DR; 52 53 // The parts of the address. The address is equivalent to: 54 // 55 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 56 SDValue Base; 57 int64_t Disp; 58 SDValue Index; 59 bool IncludesDynAlloc; 60 61 SystemZAddressingMode(AddrForm form, DispRange dr) 62 : Form(form), DR(dr), Base(), Disp(0), Index(), 63 IncludesDynAlloc(false) {} 64 65 // True if the address can have an index register. 66 bool hasIndexField() { return Form != FormBD; } 67 68 // True if the address can (and must) include ADJDYNALLOC. 69 bool isDynAlloc() { return Form == FormBDXDynAlloc; } 70 71 void dump() { 72 errs() << "SystemZAddressingMode " << this << '\n'; 73 74 errs() << " Base "; 75 if (Base.getNode() != 0) 76 Base.getNode()->dump(); 77 else 78 errs() << "null\n"; 79 80 if (hasIndexField()) { 81 errs() << " Index "; 82 if (Index.getNode() != 0) 83 Index.getNode()->dump(); 84 else 85 errs() << "null\n"; 86 } 87 88 errs() << " Disp " << Disp; 89 if (IncludesDynAlloc) 90 errs() << " + ADJDYNALLOC"; 91 errs() << '\n'; 92 } 93}; 94 95// Return a mask with Count low bits set. 96static uint64_t allOnes(unsigned int Count) { 97 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1; 98} 99 100// Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation 101// given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and 102// Rotate (I5). The combined operand value is effectively: 103// 104// (or (rotl Input, Rotate), ~Mask) 105// 106// for RNSBG and: 107// 108// (and (rotl Input, Rotate), Mask) 109// 110// otherwise. The output value has BitSize bits, although Input may be 111// narrower (in which case the upper bits are don't care). 112struct RxSBGOperands { 113 RxSBGOperands(unsigned Op, SDValue N) 114 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()), 115 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63), 116 Rotate(0) {} 117 118 unsigned Opcode; 119 unsigned BitSize; 120 uint64_t Mask; 121 SDValue Input; 122 unsigned Start; 123 unsigned End; 124 unsigned Rotate; 125}; 126 127class SystemZDAGToDAGISel : public SelectionDAGISel { 128 const SystemZTargetLowering &Lowering; 129 const SystemZSubtarget &Subtarget; 130 131 // Used by SystemZOperands.td to create integer constants. 132 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { 133 return CurDAG->getTargetConstant(Imm, Node->getValueType(0)); 134 } 135 136 const SystemZTargetMachine &getTargetMachine() const { 137 return static_cast<const SystemZTargetMachine &>(TM); 138 } 139 140 const SystemZInstrInfo *getInstrInfo() const { 141 return getTargetMachine().getInstrInfo(); 142 } 143 144 // Try to fold more of the base or index of AM into AM, where IsBase 145 // selects between the base and index. 146 bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const; 147 148 // Try to describe N in AM, returning true on success. 149 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const; 150 151 // Extract individual target operands from matched address AM. 152 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 153 SDValue &Base, SDValue &Disp) const; 154 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 155 SDValue &Base, SDValue &Disp, SDValue &Index) const; 156 157 // Try to match Addr as a FormBD address with displacement type DR. 158 // Return true on success, storing the base and displacement in 159 // Base and Disp respectively. 160 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 161 SDValue &Base, SDValue &Disp) const; 162 163 // Try to match Addr as a FormBDX address with displacement type DR. 164 // Return true on success and if the result had no index. Store the 165 // base and displacement in Base and Disp respectively. 166 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 167 SDValue &Base, SDValue &Disp) const; 168 169 // Try to match Addr as a FormBDX* address of form Form with 170 // displacement type DR. Return true on success, storing the base, 171 // displacement and index in Base, Disp and Index respectively. 172 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form, 173 SystemZAddressingMode::DispRange DR, SDValue Addr, 174 SDValue &Base, SDValue &Disp, SDValue &Index) const; 175 176 // PC-relative address matching routines used by SystemZOperands.td. 177 bool selectPCRelAddress(SDValue Addr, SDValue &Target) const { 178 if (SystemZISD::isPCREL(Addr.getOpcode())) { 179 Target = Addr.getOperand(0); 180 return true; 181 } 182 return false; 183 } 184 185 // BD matching routines used by SystemZOperands.td. 186 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 187 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp); 188 } 189 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 190 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 191 } 192 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { 193 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp); 194 } 195 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 196 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 197 } 198 199 // MVI matching routines used by SystemZOperands.td. 200 bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 201 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 202 } 203 bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const { 204 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 205 } 206 207 // BDX matching routines used by SystemZOperands.td. 208 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 209 SDValue &Index) const { 210 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 211 SystemZAddressingMode::Disp12Only, 212 Addr, Base, Disp, Index); 213 } 214 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 215 SDValue &Index) const { 216 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 217 SystemZAddressingMode::Disp12Pair, 218 Addr, Base, Disp, Index); 219 } 220 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 221 SDValue &Index) const { 222 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc, 223 SystemZAddressingMode::Disp12Only, 224 Addr, Base, Disp, Index); 225 } 226 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, 227 SDValue &Index) const { 228 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 229 SystemZAddressingMode::Disp20Only, 230 Addr, Base, Disp, Index); 231 } 232 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, 233 SDValue &Index) const { 234 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 235 SystemZAddressingMode::Disp20Only128, 236 Addr, Base, Disp, Index); 237 } 238 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 239 SDValue &Index) const { 240 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 241 SystemZAddressingMode::Disp20Pair, 242 Addr, Base, Disp, Index); 243 } 244 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 245 SDValue &Index) const { 246 return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 247 SystemZAddressingMode::Disp12Pair, 248 Addr, Base, Disp, Index); 249 } 250 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 251 SDValue &Index) const { 252 return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 253 SystemZAddressingMode::Disp20Pair, 254 Addr, Base, Disp, Index); 255 } 256 257 // Check whether (or Op (and X InsertMask)) is effectively an insertion 258 // of X into bits InsertMask of some Y != Op. Return true if so and 259 // set Op to that Y. 260 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const; 261 262 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used. 263 // Return true on success. 264 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const; 265 266 // Try to fold some of RxSBG.Input into other fields of RxSBG. 267 // Return true on success. 268 bool expandRxSBG(RxSBGOperands &RxSBG) const; 269 270 // Return an undefined value of type VT. 271 SDValue getUNDEF(SDLoc DL, EVT VT) const; 272 273 // Convert N to VT, if it isn't already. 274 SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const; 275 276 // Try to implement AND or shift node N using RISBG with the zero flag set. 277 // Return the selected node on success, otherwise return null. 278 SDNode *tryRISBGZero(SDNode *N); 279 280 // Try to use RISBG or Opcode to implement OR or XOR node N. 281 // Return the selected node on success, otherwise return null. 282 SDNode *tryRxSBG(SDNode *N, unsigned Opcode); 283 284 // If Op0 is null, then Node is a constant that can be loaded using: 285 // 286 // (Opcode UpperVal LowerVal) 287 // 288 // If Op0 is nonnull, then Node can be implemented using: 289 // 290 // (Opcode (Opcode Op0 UpperVal) LowerVal) 291 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 292 uint64_t UpperVal, uint64_t LowerVal); 293 294 // Return true if Load and Store are loads and stores of the same size 295 // and are guaranteed not to overlap. Such operations can be implemented 296 // using block (SS-format) instructions. 297 // 298 // Partial overlap would lead to incorrect code, since the block operations 299 // are logically bytewise, even though they have a fast path for the 300 // non-overlapping case. We also need to avoid full overlap (i.e. two 301 // addresses that might be equal at run time) because although that case 302 // would be handled correctly, it might be implemented by millicode. 303 bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const; 304 305 // N is a (store (load Y), X) pattern. Return true if it can use an MVC 306 // from Y to X. 307 bool storeLoadCanUseMVC(SDNode *N) const; 308 309 // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true 310 // if A[1 - I] == X and if N can use a block operation like NC from A[I] 311 // to X. 312 bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const; 313 314public: 315 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 316 : SelectionDAGISel(TM, OptLevel), 317 Lowering(*TM.getTargetLowering()), 318 Subtarget(*TM.getSubtargetImpl()) { } 319 320 // Override MachineFunctionPass. 321 virtual const char *getPassName() const LLVM_OVERRIDE { 322 return "SystemZ DAG->DAG Pattern Instruction Selection"; 323 } 324 325 // Override SelectionDAGISel. 326 virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE; 327 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 328 char ConstraintCode, 329 std::vector<SDValue> &OutOps) 330 LLVM_OVERRIDE; 331 332 // Include the pieces autogenerated from the target description. 333 #include "SystemZGenDAGISel.inc" 334}; 335} // end anonymous namespace 336 337FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 338 CodeGenOpt::Level OptLevel) { 339 return new SystemZDAGToDAGISel(TM, OptLevel); 340} 341 342// Return true if Val should be selected as a displacement for an address 343// with range DR. Here we're interested in the range of both the instruction 344// described by DR and of any pairing instruction. 345static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 346 switch (DR) { 347 case SystemZAddressingMode::Disp12Only: 348 return isUInt<12>(Val); 349 350 case SystemZAddressingMode::Disp12Pair: 351 case SystemZAddressingMode::Disp20Only: 352 case SystemZAddressingMode::Disp20Pair: 353 return isInt<20>(Val); 354 355 case SystemZAddressingMode::Disp20Only128: 356 return isInt<20>(Val) && isInt<20>(Val + 8); 357 } 358 llvm_unreachable("Unhandled displacement range"); 359} 360 361// Change the base or index in AM to Value, where IsBase selects 362// between the base and index. 363static void changeComponent(SystemZAddressingMode &AM, bool IsBase, 364 SDValue Value) { 365 if (IsBase) 366 AM.Base = Value; 367 else 368 AM.Index = Value; 369} 370 371// The base or index of AM is equivalent to Value + ADJDYNALLOC, 372// where IsBase selects between the base and index. Try to fold the 373// ADJDYNALLOC into AM. 374static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, 375 SDValue Value) { 376 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) { 377 changeComponent(AM, IsBase, Value); 378 AM.IncludesDynAlloc = true; 379 return true; 380 } 381 return false; 382} 383 384// The base of AM is equivalent to Base + Index. Try to use Index as 385// the index register. 386static bool expandIndex(SystemZAddressingMode &AM, SDValue Base, 387 SDValue Index) { 388 if (AM.hasIndexField() && !AM.Index.getNode()) { 389 AM.Base = Base; 390 AM.Index = Index; 391 return true; 392 } 393 return false; 394} 395 396// The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 397// between the base and index. Try to fold Op1 into AM's displacement. 398static bool expandDisp(SystemZAddressingMode &AM, bool IsBase, 399 SDValue Op0, uint64_t Op1) { 400 // First try adjusting the displacement. 401 int64_t TestDisp = AM.Disp + Op1; 402 if (selectDisp(AM.DR, TestDisp)) { 403 changeComponent(AM, IsBase, Op0); 404 AM.Disp = TestDisp; 405 return true; 406 } 407 408 // We could consider forcing the displacement into a register and 409 // using it as an index, but it would need to be carefully tuned. 410 return false; 411} 412 413bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM, 414 bool IsBase) const { 415 SDValue N = IsBase ? AM.Base : AM.Index; 416 unsigned Opcode = N.getOpcode(); 417 if (Opcode == ISD::TRUNCATE) { 418 N = N.getOperand(0); 419 Opcode = N.getOpcode(); 420 } 421 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { 422 SDValue Op0 = N.getOperand(0); 423 SDValue Op1 = N.getOperand(1); 424 425 unsigned Op0Code = Op0->getOpcode(); 426 unsigned Op1Code = Op1->getOpcode(); 427 428 if (Op0Code == SystemZISD::ADJDYNALLOC) 429 return expandAdjDynAlloc(AM, IsBase, Op1); 430 if (Op1Code == SystemZISD::ADJDYNALLOC) 431 return expandAdjDynAlloc(AM, IsBase, Op0); 432 433 if (Op0Code == ISD::Constant) 434 return expandDisp(AM, IsBase, Op1, 435 cast<ConstantSDNode>(Op0)->getSExtValue()); 436 if (Op1Code == ISD::Constant) 437 return expandDisp(AM, IsBase, Op0, 438 cast<ConstantSDNode>(Op1)->getSExtValue()); 439 440 if (IsBase && expandIndex(AM, Op0, Op1)) 441 return true; 442 } 443 if (Opcode == SystemZISD::PCREL_OFFSET) { 444 SDValue Full = N.getOperand(0); 445 SDValue Base = N.getOperand(1); 446 SDValue Anchor = Base.getOperand(0); 447 uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() - 448 cast<GlobalAddressSDNode>(Anchor)->getOffset()); 449 return expandDisp(AM, IsBase, Base, Offset); 450 } 451 return false; 452} 453 454// Return true if an instruction with displacement range DR should be 455// used for displacement value Val. selectDisp(DR, Val) must already hold. 456static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 457 assert(selectDisp(DR, Val) && "Invalid displacement"); 458 switch (DR) { 459 case SystemZAddressingMode::Disp12Only: 460 case SystemZAddressingMode::Disp20Only: 461 case SystemZAddressingMode::Disp20Only128: 462 return true; 463 464 case SystemZAddressingMode::Disp12Pair: 465 // Use the other instruction if the displacement is too large. 466 return isUInt<12>(Val); 467 468 case SystemZAddressingMode::Disp20Pair: 469 // Use the other instruction if the displacement is small enough. 470 return !isUInt<12>(Val); 471 } 472 llvm_unreachable("Unhandled displacement range"); 473} 474 475// Return true if Base + Disp + Index should be performed by LA(Y). 476static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) { 477 // Don't use LA(Y) for constants. 478 if (!Base) 479 return false; 480 481 // Always use LA(Y) for frame addresses, since we know that the destination 482 // register is almost always (perhaps always) going to be different from 483 // the frame register. 484 if (Base->getOpcode() == ISD::FrameIndex) 485 return true; 486 487 if (Disp) { 488 // Always use LA(Y) if there is a base, displacement and index. 489 if (Index) 490 return true; 491 492 // Always use LA if the displacement is small enough. It should always 493 // be no worse than AGHI (and better if it avoids a move). 494 if (isUInt<12>(Disp)) 495 return true; 496 497 // For similar reasons, always use LAY if the constant is too big for AGHI. 498 // LAY should be no worse than AGFI. 499 if (!isInt<16>(Disp)) 500 return true; 501 } else { 502 // Don't use LA for plain registers. 503 if (!Index) 504 return false; 505 506 // Don't use LA for plain addition if the index operand is only used 507 // once. It should be a natural two-operand addition in that case. 508 if (Index->hasOneUse()) 509 return false; 510 511 // Prefer addition if the second operation is sign-extended, in the 512 // hope of using AGF. 513 unsigned IndexOpcode = Index->getOpcode(); 514 if (IndexOpcode == ISD::SIGN_EXTEND || 515 IndexOpcode == ISD::SIGN_EXTEND_INREG) 516 return false; 517 } 518 519 // Don't use LA for two-operand addition if either operand is only 520 // used once. The addition instructions are better in that case. 521 if (Base->hasOneUse()) 522 return false; 523 524 return true; 525} 526 527// Return true if Addr is suitable for AM, updating AM if so. 528bool SystemZDAGToDAGISel::selectAddress(SDValue Addr, 529 SystemZAddressingMode &AM) const { 530 // Start out assuming that the address will need to be loaded separately, 531 // then try to extend it as much as we can. 532 AM.Base = Addr; 533 534 // First try treating the address as a constant. 535 if (Addr.getOpcode() == ISD::Constant && 536 expandDisp(AM, true, SDValue(), 537 cast<ConstantSDNode>(Addr)->getSExtValue())) 538 ; 539 else 540 // Otherwise try expanding each component. 541 while (expandAddress(AM, true) || 542 (AM.Index.getNode() && expandAddress(AM, false))) 543 continue; 544 545 // Reject cases where it isn't profitable to use LA(Y). 546 if (AM.Form == SystemZAddressingMode::FormBDXLA && 547 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) 548 return false; 549 550 // Reject cases where the other instruction in a pair should be used. 551 if (!isValidDisp(AM.DR, AM.Disp)) 552 return false; 553 554 // Make sure that ADJDYNALLOC is included where necessary. 555 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) 556 return false; 557 558 DEBUG(AM.dump()); 559 return true; 560} 561 562// Insert a node into the DAG at least before Pos. This will reposition 563// the node as needed, and will assign it a node ID that is <= Pos's ID. 564// Note that this does *not* preserve the uniqueness of node IDs! 565// The selection DAG must no longer depend on their uniqueness when this 566// function is used. 567static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { 568 if (N.getNode()->getNodeId() == -1 || 569 N.getNode()->getNodeId() > Pos->getNodeId()) { 570 DAG->RepositionNode(Pos, N.getNode()); 571 N.getNode()->setNodeId(Pos->getNodeId()); 572 } 573} 574 575void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 576 EVT VT, SDValue &Base, 577 SDValue &Disp) const { 578 Base = AM.Base; 579 if (!Base.getNode()) 580 // Register 0 means "no base". This is mostly useful for shifts. 581 Base = CurDAG->getRegister(0, VT); 582 else if (Base.getOpcode() == ISD::FrameIndex) { 583 // Lower a FrameIndex to a TargetFrameIndex. 584 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); 585 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); 586 } else if (Base.getValueType() != VT) { 587 // Truncate values from i64 to i32, for shifts. 588 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && 589 "Unexpected truncation"); 590 SDLoc DL(Base); 591 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); 592 insertDAGNode(CurDAG, Base.getNode(), Trunc); 593 Base = Trunc; 594 } 595 596 // Lower the displacement to a TargetConstant. 597 Disp = CurDAG->getTargetConstant(AM.Disp, VT); 598} 599 600void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 601 EVT VT, SDValue &Base, 602 SDValue &Disp, 603 SDValue &Index) const { 604 getAddressOperands(AM, VT, Base, Disp); 605 606 Index = AM.Index; 607 if (!Index.getNode()) 608 // Register 0 means "no index". 609 Index = CurDAG->getRegister(0, VT); 610} 611 612bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR, 613 SDValue Addr, SDValue &Base, 614 SDValue &Disp) const { 615 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR); 616 if (!selectAddress(Addr, AM)) 617 return false; 618 619 getAddressOperands(AM, Addr.getValueType(), Base, Disp); 620 return true; 621} 622 623bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR, 624 SDValue Addr, SDValue &Base, 625 SDValue &Disp) const { 626 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR); 627 if (!selectAddress(Addr, AM) || AM.Index.getNode()) 628 return false; 629 630 getAddressOperands(AM, Addr.getValueType(), Base, Disp); 631 return true; 632} 633 634bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form, 635 SystemZAddressingMode::DispRange DR, 636 SDValue Addr, SDValue &Base, 637 SDValue &Disp, SDValue &Index) const { 638 SystemZAddressingMode AM(Form, DR); 639 if (!selectAddress(Addr, AM)) 640 return false; 641 642 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index); 643 return true; 644} 645 646bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op, 647 uint64_t InsertMask) const { 648 // We're only interested in cases where the insertion is into some operand 649 // of Op, rather than into Op itself. The only useful case is an AND. 650 if (Op.getOpcode() != ISD::AND) 651 return false; 652 653 // We need a constant mask. 654 ConstantSDNode *MaskNode = 655 dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode()); 656 if (!MaskNode) 657 return false; 658 659 // It's not an insertion of Op.getOperand(0) if the two masks overlap. 660 uint64_t AndMask = MaskNode->getZExtValue(); 661 if (InsertMask & AndMask) 662 return false; 663 664 // It's only an insertion if all bits are covered or are known to be zero. 665 // The inner check covers all cases but is more expensive. 666 uint64_t Used = allOnes(Op.getValueType().getSizeInBits()); 667 if (Used != (AndMask | InsertMask)) { 668 APInt KnownZero, KnownOne; 669 CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne); 670 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue())) 671 return false; 672 } 673 674 Op = Op.getOperand(0); 675 return true; 676} 677 678bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, 679 uint64_t Mask) const { 680 const SystemZInstrInfo *TII = getInstrInfo(); 681 if (RxSBG.Rotate != 0) 682 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); 683 Mask &= RxSBG.Mask; 684 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) { 685 RxSBG.Mask = Mask; 686 return true; 687 } 688 return false; 689} 690 691// Return true if any bits of (RxSBG.Input & Mask) are significant. 692static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) { 693 // Rotate the mask in the same way as RxSBG.Input is rotated. 694 if (RxSBG.Rotate != 0) 695 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))); 696 return (Mask & RxSBG.Mask) != 0; 697} 698 699bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const { 700 SDValue N = RxSBG.Input; 701 unsigned Opcode = N.getOpcode(); 702 switch (Opcode) { 703 case ISD::AND: { 704 if (RxSBG.Opcode == SystemZ::RNSBG) 705 return false; 706 707 ConstantSDNode *MaskNode = 708 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 709 if (!MaskNode) 710 return false; 711 712 SDValue Input = N.getOperand(0); 713 uint64_t Mask = MaskNode->getZExtValue(); 714 if (!refineRxSBGMask(RxSBG, Mask)) { 715 // If some bits of Input are already known zeros, those bits will have 716 // been removed from the mask. See if adding them back in makes the 717 // mask suitable. 718 APInt KnownZero, KnownOne; 719 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); 720 Mask |= KnownZero.getZExtValue(); 721 if (!refineRxSBGMask(RxSBG, Mask)) 722 return false; 723 } 724 RxSBG.Input = Input; 725 return true; 726 } 727 728 case ISD::OR: { 729 if (RxSBG.Opcode != SystemZ::RNSBG) 730 return false; 731 732 ConstantSDNode *MaskNode = 733 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 734 if (!MaskNode) 735 return false; 736 737 SDValue Input = N.getOperand(0); 738 uint64_t Mask = ~MaskNode->getZExtValue(); 739 if (!refineRxSBGMask(RxSBG, Mask)) { 740 // If some bits of Input are already known ones, those bits will have 741 // been removed from the mask. See if adding them back in makes the 742 // mask suitable. 743 APInt KnownZero, KnownOne; 744 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); 745 Mask &= ~KnownOne.getZExtValue(); 746 if (!refineRxSBGMask(RxSBG, Mask)) 747 return false; 748 } 749 RxSBG.Input = Input; 750 return true; 751 } 752 753 case ISD::ROTL: { 754 // Any 64-bit rotate left can be merged into the RxSBG. 755 if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64) 756 return false; 757 ConstantSDNode *CountNode 758 = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 759 if (!CountNode) 760 return false; 761 762 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63; 763 RxSBG.Input = N.getOperand(0); 764 return true; 765 } 766 767 case ISD::SIGN_EXTEND: 768 case ISD::ZERO_EXTEND: 769 case ISD::ANY_EXTEND: { 770 // Check that the extension bits are don't-care (i.e. are masked out 771 // by the final mask). 772 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); 773 if (maskMatters(RxSBG, allOnes(RxSBG.BitSize) - allOnes(InnerBitSize))) 774 return false; 775 776 RxSBG.Input = N.getOperand(0); 777 return true; 778 } 779 780 case ISD::SHL: { 781 ConstantSDNode *CountNode = 782 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 783 if (!CountNode) 784 return false; 785 786 uint64_t Count = CountNode->getZExtValue(); 787 unsigned BitSize = N.getValueType().getSizeInBits(); 788 if (Count < 1 || Count >= BitSize) 789 return false; 790 791 if (RxSBG.Opcode == SystemZ::RNSBG) { 792 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom 793 // count bits from RxSBG.Input are ignored. 794 if (maskMatters(RxSBG, allOnes(Count))) 795 return false; 796 } else { 797 // Treat (shl X, count) as (and (rotl X, count), ~0<<count). 798 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count)) 799 return false; 800 } 801 802 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63; 803 RxSBG.Input = N.getOperand(0); 804 return true; 805 } 806 807 case ISD::SRL: 808 case ISD::SRA: { 809 ConstantSDNode *CountNode = 810 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 811 if (!CountNode) 812 return false; 813 814 uint64_t Count = CountNode->getZExtValue(); 815 unsigned BitSize = N.getValueType().getSizeInBits(); 816 if (Count < 1 || Count >= BitSize) 817 return false; 818 819 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { 820 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top 821 // count bits from RxSBG.Input are ignored. 822 if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count))) 823 return false; 824 } else { 825 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), 826 // which is similar to SLL above. 827 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count))) 828 return false; 829 } 830 831 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63; 832 RxSBG.Input = N.getOperand(0); 833 return true; 834 } 835 default: 836 return false; 837 } 838} 839 840SDValue SystemZDAGToDAGISel::getUNDEF(SDLoc DL, EVT VT) const { 841 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT); 842 return SDValue(N, 0); 843} 844 845SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) const { 846 if (N.getValueType() == MVT::i32 && VT == MVT::i64) 847 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, 848 DL, VT, getUNDEF(DL, MVT::i64), N); 849 if (N.getValueType() == MVT::i64 && VT == MVT::i32) 850 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); 851 assert(N.getValueType() == VT && "Unexpected value types"); 852 return N; 853} 854 855SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { 856 EVT VT = N->getValueType(0); 857 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0)); 858 unsigned Count = 0; 859 while (expandRxSBG(RISBG)) 860 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND) 861 Count += 1; 862 if (Count == 0) 863 return 0; 864 if (Count == 1) { 865 // Prefer to use normal shift instructions over RISBG, since they can handle 866 // all cases and are sometimes shorter. 867 if (N->getOpcode() != ISD::AND) 868 return 0; 869 870 // Prefer register extensions like LLC over RISBG. Also prefer to start 871 // out with normal ANDs if one instruction would be enough. We can convert 872 // these ANDs into an RISBG later if a three-address instruction is useful. 873 if (VT == MVT::i32 || 874 RISBG.Mask == 0xff || 875 RISBG.Mask == 0xffff || 876 SystemZ::isImmLF(~RISBG.Mask) || 877 SystemZ::isImmHF(~RISBG.Mask)) { 878 // Force the new mask into the DAG, since it may include known-one bits. 879 ConstantSDNode *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode()); 880 if (MaskN->getZExtValue() != RISBG.Mask) { 881 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT); 882 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask); 883 return SelectCode(N); 884 } 885 return 0; 886 } 887 } 888 889 unsigned Opcode = SystemZ::RISBG; 890 EVT OpcodeVT = MVT::i64; 891 if (VT == MVT::i32 && Subtarget.hasHighWord()) { 892 Opcode = SystemZ::RISBMux; 893 OpcodeVT = MVT::i32; 894 RISBG.Start &= 31; 895 RISBG.End &= 31; 896 } 897 SDValue Ops[5] = { 898 getUNDEF(SDLoc(N), OpcodeVT), 899 convertTo(SDLoc(N), OpcodeVT, RISBG.Input), 900 CurDAG->getTargetConstant(RISBG.Start, MVT::i32), 901 CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32), 902 CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32) 903 }; 904 N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops); 905 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode(); 906} 907 908SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) { 909 // Try treating each operand of N as the second operand of the RxSBG 910 // and see which goes deepest. 911 RxSBGOperands RxSBG[] = { 912 RxSBGOperands(Opcode, N->getOperand(0)), 913 RxSBGOperands(Opcode, N->getOperand(1)) 914 }; 915 unsigned Count[] = { 0, 0 }; 916 for (unsigned I = 0; I < 2; ++I) 917 while (expandRxSBG(RxSBG[I])) 918 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND) 919 Count[I] += 1; 920 921 // Do nothing if neither operand is suitable. 922 if (Count[0] == 0 && Count[1] == 0) 923 return 0; 924 925 // Pick the deepest second operand. 926 unsigned I = Count[0] > Count[1] ? 0 : 1; 927 SDValue Op0 = N->getOperand(I ^ 1); 928 929 // Prefer IC for character insertions from memory. 930 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0) 931 if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode())) 932 if (Load->getMemoryVT() == MVT::i8) 933 return 0; 934 935 // See whether we can avoid an AND in the first operand by converting 936 // ROSBG to RISBG. 937 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) 938 Opcode = SystemZ::RISBG; 939 940 EVT VT = N->getValueType(0); 941 SDValue Ops[5] = { 942 convertTo(SDLoc(N), MVT::i64, Op0), 943 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input), 944 CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32), 945 CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32), 946 CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32) 947 }; 948 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops); 949 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode(); 950} 951 952SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node, 953 SDValue Op0, uint64_t UpperVal, 954 uint64_t LowerVal) { 955 EVT VT = Node->getValueType(0); 956 SDLoc DL(Node); 957 SDValue Upper = CurDAG->getConstant(UpperVal, VT); 958 if (Op0.getNode()) 959 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); 960 Upper = SDValue(Select(Upper.getNode()), 0); 961 962 SDValue Lower = CurDAG->getConstant(LowerVal, VT); 963 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); 964 return Or.getNode(); 965} 966 967bool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store, 968 LoadSDNode *Load) const { 969 // Check that the two memory operands have the same size. 970 if (Load->getMemoryVT() != Store->getMemoryVT()) 971 return false; 972 973 // Volatility stops an access from being decomposed. 974 if (Load->isVolatile() || Store->isVolatile()) 975 return false; 976 977 // There's no chance of overlap if the load is invariant. 978 if (Load->isInvariant()) 979 return true; 980 981 // Otherwise we need to check whether there's an alias. 982 const Value *V1 = Load->getSrcValue(); 983 const Value *V2 = Store->getSrcValue(); 984 if (!V1 || !V2) 985 return false; 986 987 // Reject equality. 988 uint64_t Size = Load->getMemoryVT().getStoreSize(); 989 int64_t End1 = Load->getSrcValueOffset() + Size; 990 int64_t End2 = Store->getSrcValueOffset() + Size; 991 if (V1 == V2 && End1 == End2) 992 return false; 993 994 return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()), 995 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo())); 996} 997 998bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const { 999 StoreSDNode *Store = cast<StoreSDNode>(N); 1000 LoadSDNode *Load = cast<LoadSDNode>(Store->getValue()); 1001 1002 // Prefer not to use MVC if either address can use ... RELATIVE LONG 1003 // instructions. 1004 uint64_t Size = Load->getMemoryVT().getStoreSize(); 1005 if (Size > 1 && Size <= 8) { 1006 // Prefer LHRL, LRL and LGRL. 1007 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) 1008 return false; 1009 // Prefer STHRL, STRL and STGRL. 1010 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) 1011 return false; 1012 } 1013 1014 return canUseBlockOperation(Store, Load); 1015} 1016 1017bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N, 1018 unsigned I) const { 1019 StoreSDNode *StoreA = cast<StoreSDNode>(N); 1020 LoadSDNode *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I)); 1021 LoadSDNode *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I)); 1022 return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB); 1023} 1024 1025SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { 1026 // Dump information about the Node being selected 1027 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 1028 1029 // If we have a custom node, we already have selected! 1030 if (Node->isMachineOpcode()) { 1031 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 1032 Node->setNodeId(-1); 1033 return 0; 1034 } 1035 1036 unsigned Opcode = Node->getOpcode(); 1037 SDNode *ResNode = 0; 1038 switch (Opcode) { 1039 case ISD::OR: 1040 if (Node->getOperand(1).getOpcode() != ISD::Constant) 1041 ResNode = tryRxSBG(Node, SystemZ::ROSBG); 1042 goto or_xor; 1043 1044 case ISD::XOR: 1045 if (Node->getOperand(1).getOpcode() != ISD::Constant) 1046 ResNode = tryRxSBG(Node, SystemZ::RXSBG); 1047 // Fall through. 1048 or_xor: 1049 // If this is a 64-bit operation in which both 32-bit halves are nonzero, 1050 // split the operation into two. 1051 if (!ResNode && Node->getValueType(0) == MVT::i64) 1052 if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) { 1053 uint64_t Val = Op1->getZExtValue(); 1054 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) 1055 Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0), 1056 Val - uint32_t(Val), uint32_t(Val)); 1057 } 1058 break; 1059 1060 case ISD::AND: 1061 if (Node->getOperand(1).getOpcode() != ISD::Constant) 1062 ResNode = tryRxSBG(Node, SystemZ::RNSBG); 1063 // Fall through. 1064 case ISD::ROTL: 1065 case ISD::SHL: 1066 case ISD::SRL: 1067 if (!ResNode) 1068 ResNode = tryRISBGZero(Node); 1069 break; 1070 1071 case ISD::Constant: 1072 // If this is a 64-bit constant that is out of the range of LLILF, 1073 // LLIHF and LGFI, split it into two 32-bit pieces. 1074 if (Node->getValueType(0) == MVT::i64) { 1075 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue(); 1076 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) 1077 Node = splitLargeImmediate(ISD::OR, Node, SDValue(), 1078 Val - uint32_t(Val), uint32_t(Val)); 1079 } 1080 break; 1081 1082 case ISD::ATOMIC_LOAD_SUB: 1083 // Try to convert subtractions of constants to additions. 1084 if (ConstantSDNode *Op2 = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 1085 uint64_t Value = -Op2->getZExtValue(); 1086 EVT VT = Node->getValueType(0); 1087 if (VT == MVT::i32 || isInt<32>(Value)) { 1088 SDValue Ops[] = { Node->getOperand(0), Node->getOperand(1), 1089 CurDAG->getConstant(int32_t(Value), VT) }; 1090 Node = CurDAG->MorphNodeTo(Node, ISD::ATOMIC_LOAD_ADD, 1091 Node->getVTList(), Ops, array_lengthof(Ops)); 1092 } 1093 } 1094 break; 1095 1096 case SystemZISD::SELECT_CCMASK: { 1097 SDValue Op0 = Node->getOperand(0); 1098 SDValue Op1 = Node->getOperand(1); 1099 // Prefer to put any load first, so that it can be matched as a 1100 // conditional load. 1101 if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) { 1102 SDValue CCValid = Node->getOperand(2); 1103 SDValue CCMask = Node->getOperand(3); 1104 uint64_t ConstCCValid = 1105 cast<ConstantSDNode>(CCValid.getNode())->getZExtValue(); 1106 uint64_t ConstCCMask = 1107 cast<ConstantSDNode>(CCMask.getNode())->getZExtValue(); 1108 // Invert the condition. 1109 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, 1110 CCMask.getValueType()); 1111 SDValue Op4 = Node->getOperand(4); 1112 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); 1113 } 1114 break; 1115 } 1116 } 1117 1118 // Select the default instruction 1119 if (!ResNode) 1120 ResNode = SelectCode(Node); 1121 1122 DEBUG(errs() << "=> "; 1123 if (ResNode == NULL || ResNode == Node) 1124 Node->dump(CurDAG); 1125 else 1126 ResNode->dump(CurDAG); 1127 errs() << "\n"; 1128 ); 1129 return ResNode; 1130} 1131 1132bool SystemZDAGToDAGISel:: 1133SelectInlineAsmMemoryOperand(const SDValue &Op, 1134 char ConstraintCode, 1135 std::vector<SDValue> &OutOps) { 1136 assert(ConstraintCode == 'm' && "Unexpected constraint code"); 1137 // Accept addresses with short displacements, which are compatible 1138 // with Q, R, S and T. But keep the index operand for future expansion. 1139 SDValue Base, Disp, Index; 1140 if (!selectBDXAddr(SystemZAddressingMode::FormBD, 1141 SystemZAddressingMode::Disp12Only, 1142 Op, Base, Disp, Index)) 1143 return true; 1144 OutOps.push_back(Base); 1145 OutOps.push_back(Disp); 1146 OutOps.push_back(Index); 1147 return false; 1148} 1149