| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 86a735396ab4804a06e76d1b4ce49dbd44c35827 |
|
26-Nov-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
Merging r195731:
------------------------------------------------------------------------
r195731 | rsandifo | 2013-11-26 10:53:16 +0000 (Tue, 26 Nov 2013) | 7 lines
[SystemZ] Fix incorrect use of RISBG for a zero-extended right shift
We would wrongly transform the testcase into the equivalent of an AND with 1.
The problem was that, when testing whether the shifted-in bits of the right
shift were significant, we used the width of the final zero-extended result
rather than the width of the shifted value.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| d77a7669ec1a6bba7e45791b1aa1e65a603dda92 |
|
16-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Handle extensions in RxSBG optimizations
The input to an RxSBG operation can be narrower as long as the upper bits
are don't care. This fixes a FIXME added in r192783.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| f985f01574956da0d42e33d440deb63bf153d354 |
|
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Extend 32-bit RISBG optimizations to high words
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 745ca1eed7dc0a056b066f16aea750ce6fa8a530 |
|
30-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Rename subregs and add subreg_h32
Use subreg_hNN and subreg_lNN for the high and low NN bits of a register.
List the low registers first, so that subreg_l32 also means the low 32
bits of a 128-bit register.
Floats are stored in the upper 32 bits of a 64-bit register, so they
should use subreg_h32 rather than subreg_l32.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 0548a5487ab8648c7c017f87c507ea1bc38bbb1f |
|
27-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Rein back the use of block operations
The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations. For correctness reasons, it rejects any case
in which the regions might partially overlap. However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.
This fixes a performance regression seen in bzip2. We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 8dac19c0708c9bd0da0b832014918e00ded44d86 |
|
27-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Improve handling of PC-relative addresses
The backend previously folded offsets into PC-relative addresses
whereever possible. That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL). But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.
Fixes a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
|
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 7c7b431d2fa3ead0a2a24c4dd81fc92f293203dd |
|
13-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use getTarget{Insert,Extract}Subreg rather than getMachineNode
Just a clean-up, no behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 16277c4698f36a756c540fae326874774156aaed |
|
05-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 65ddcfa8c1c05aeecd9d4fb062bb121e376aaceb |
|
23-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Prefer LHI;ST... over LAY;MV...
If we had a store of an integer to memory, and the integer and store size
were suitable for a form of MV..., we used MV... no matter what. We could
then have sequences like:
lay %r2, 0(%r3,%r4)
mvi 0(%r2), 4
In these cases it seems better to force the constant into a register
and use a normal store:
lhi %r2, 4
stc %r2, 0(%r3, %r4)
since %r2 is more likely to be hoisted and is easier to rematerialize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 15715fb689a5c7a2476c943a7b06616bd6d67d5e |
|
31-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Be more careful about inverting CC masks (conditional loads)
Extend r187495 to conditional loads. I split this out because the
easiest way seemed to be to force a particular operand order in
SystemZISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| b3f912b510f8040690864126351b7021980558bb |
|
31-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source. I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead. The AND IMMEDIATE form is shorter
and is less likely to be cracked.
This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register. The patch uses the z196 instruction RISBLG for this instead.
This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now. Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 722a26d63e717f5cfbf924e042f4f300bfee1328 |
|
18-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use RNSBG
This should be the last of the R.SBG patches for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 9dffd71d0af3d78ee1f21865dd064fb43bc623be |
|
18-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Generalize RxSBG SRA case
The original code only folded SRA into ROTATE ... SELECTED BITS
if there was no outer shift. This patch splits out that check
and generalises it slightly. The extra cases aren't really that
interesting, but this is paving the way for RNSBG support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 30a132f7676ec5465a2245cb94e7bd9214ea8eb7 |
|
18-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use RXSBG
Extend the previous R.SBG patches to handle XORs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| efb6c52efb4116b6a6d6c99192db68ab69025119 |
|
18-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Rename and formatting fixes
In hindsight, using "RISBG" for something that can be any type of
R.SBG instruction was a bit confusing, so this renames it to RxSBG.
That might not be the best choice either, since there is an instruction
called RXSBG, but hopefully the lower-case letter stands out enough.
While there I fixed a couple of GNUisms that had crept in --
sorry about that!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 7f6d84230c0e21b4f841a0b28a1e494fe327d2b7 |
|
17-Jul-2013 |
Aaron Ballman <aaron@aaronballman.com> |
Silencing an MSVC warning about signed vs unsigned comparison mismatches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| de25544a73acbb1dd99c948ccbea81eedcd34bc9 |
|
16-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use ROSBG and non-zero form of RISBG for OR nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 376452165863fad987c890d9773e6eb87742a3e1 |
|
16-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use RISBG for (shift (and ...))
Another patch in the series to make more use of R.SBG. This one extends
r186072 and r186073 to handle cases where the AND is inside the shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 261e2877ebcb3c6139ddcc67992662494232b096 |
|
11-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use zeroing form of RISBG for shift-and-AND sequences
Extend r186072 to handle shifts and ANDs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9 |
|
11-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.
It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 2e015ef9bb40e5d9f98db9a9509b9986873089ea |
|
09-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use MVC for simple load/store pairs
Look for patterns of the form (store (load ...), ...) in which the two
locations are known not to partially overlap. (Identical locations are OK.)
These sequences are better implemented by MVC unless either the load or
the store could use RELATIVE LONG instructions.
The testcase showed that we weren't using LHRL and LGHRL for extload16,
only sextloadi16. The patch fixes that too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07 |
|
06-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[SystemZ] Add back end
This adds the actual lib/Target/SystemZ target files necessary to
implement the SystemZ target. Note that at this point, the target
cannot yet be built since the configure bits are missing. Those
will be provided shortly by a follow-on patch.
This version of the patch incorporates feedback from reviews by
Chris Lattner and Anton Korobeynikov. Thanks to all reviewers!
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 29074ccf6cb00a3cbe32a3b7809d970ecaf8c9bf |
|
25-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Remove the SystemZ backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 17aa68055beed6faa48ca3a995c5b6fdf5092fd4 |
|
04-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 05ce4898710e3dd2dcc5f44f4aec4693ec0a42a6 |
|
29-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
were overspecified when inheriting sub-subregisters, for instance:
R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.
This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| c159fba712292f9a3de4f6841dbd6a3f3cefb2d2 |
|
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use enums instead of literals for SystemZ subregisters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 7c306da505e2d7f64e160890b274a47fa0740962 |
|
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 014bf215c3457bb34fee348265e8f63a70b4d503 |
|
15-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| eeb3a00b84b7767d236ec8cf0619b9217fc247b9 |
|
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 39784e158a49c4920a3219fcab2841fe9250826c |
|
04-Jan-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix invalid chain folding for memory variant of sdiv / udiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 73bb251cd7a535fb93bb3a52eda61555fb253f41 |
|
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 43ed267db3512823a9698f810be4e64bee227270 |
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23-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix some refactos for iostream changes (in -Asserts mode).
- The world needs better C++ refactoring tools, can I get an Amen!?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 4437ae213d5435390f0750213b53ec807c047f22 |
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23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate uses of cerr()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 893e1c90a03a53cf13f73849324e83612688428a |
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23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate the last DOUTs from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
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11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| e50ed30282bb5b4a9ed952580523f2dda16215ac |
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11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 19c29f53f274870eb033389fd0ca98e6c98f03e0 |
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17-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix 'may be used uninitialized' warning.
- Anton, please review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 7df8462038c4393771a0961c60a2686169e4fd9a |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 54681eca6900295a5592fba82ccf6120e0a65db2 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix logic inversion for RI-mode address selection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| b6831cb044a7f3dccd5ad80cd36b98175b9646ad |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Unbreak mvi and friends - emit only 'significant' part of the operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 8bd0db7615269a909b8d588d7659de8277e785d1 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 09e39001da6a17531b32849964899ccaf50c2cb9 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use divide single for 32 bit signed divides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| e3a7f7a2b20ad791626f58e16d76a514ea66b62b |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove redundand register move
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 0a42d2b4376526dbef25834b29a39fa684f9a902 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Properly handle divides. As a bonus - implement memory versions of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 014d4639d8ca98382886d89aa445444ca6b59c21 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
32 bit shifts have only 12 bit displacements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 4656760d9c3a5c982f72b8fa26b542069ed69700 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 1ed1e3ecd489e469a5d9a3727139cecb8615bb9c |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 720e3b00b869950bdc09ad065d92174772903da0 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add support for 12 bit displacements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 3166a9ac5c81621bb7f58f8cd4311694af26fa29 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
32-bit ri addressing mode has only 12-bit displacement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| c4368a1507ac072a4b5da5d7dbcbf66bdfe6595f |
|
16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 3240740ef4a473912ababc42d17dd33d0b1b2898 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do not truncate sign bits for negative imms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 711d5b68e07a24c07ff2f514b32fe526c065791f |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add address computation stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 961bb6f43026964004c0b811bd19fdf1735db5bc |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add stores and truncstores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| dc28955b3f48116fe76ef98c778aa64e51ef62db |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add patterns for various extloads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 3360da97724aee08ea8d0af11d8589da33bcbba4 |
|
16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 9e4816e09f50e3c4ef7368a188966944b8167ab4 |
|
16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add shifts and reg-imm address matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| da308c9a67d044bdba181b8564f4ecfd65b94b43 |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add bunch of reg-imm movs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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| 89edcd0927aa56584686c94bbb6914ce9f445e3a |
|
16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide masked reg-imm 'or' and 'and'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|
| 4403b930f867f61b48304a23a6843026b0b9a32a |
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16-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Let's start another backend :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
|