SystemZISelDAGToDAG.cpp revision e3a7f7a2b20ad791626f58e16d76a514ea66b62b
1//==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SystemZ target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SystemZ.h" 15#include "SystemZISelLowering.h" 16#include "SystemZTargetMachine.h" 17#include "llvm/DerivedTypes.h" 18#include "llvm/Function.h" 19#include "llvm/Intrinsics.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/SelectionDAGISel.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/Support/Debug.h" 31using namespace llvm; 32 33static const unsigned subreg_32bit = 1; 34static const unsigned subreg_even = 1; 35static const unsigned subreg_odd = 2; 36 37namespace { 38 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's 39 /// instead of register numbers for the leaves of the matched tree. 40 struct SystemZRRIAddressMode { 41 enum { 42 RegBase, 43 FrameIndexBase 44 } BaseType; 45 46 struct { // This is really a union, discriminated by BaseType! 47 SDValue Reg; 48 int FrameIndex; 49 } Base; 50 51 SDValue IndexReg; 52 int64_t Disp; 53 bool isRI; 54 55 SystemZRRIAddressMode(bool RI = false) 56 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) { 57 } 58 59 void dump() { 60 cerr << "SystemZRRIAddressMode " << this << '\n'; 61 if (BaseType == RegBase) { 62 cerr << "Base.Reg "; 63 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump(); 64 else cerr << "nul"; 65 cerr << '\n'; 66 } else { 67 cerr << " Base.FrameIndex " << Base.FrameIndex << '\n'; 68 } 69 if (!isRI) { 70 cerr << "IndexReg "; 71 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump(); 72 else cerr << "nul"; 73 } 74 cerr << " Disp " << Disp << '\n'; 75 } 76 }; 77} 78 79/// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine 80/// instructions for SelectionDAG operations. 81/// 82namespace { 83 class SystemZDAGToDAGISel : public SelectionDAGISel { 84 SystemZTargetLowering &Lowering; 85 const SystemZSubtarget &Subtarget; 86 87 void getAddressOperandsRI(const SystemZRRIAddressMode &AM, 88 SDValue &Base, SDValue &Disp); 89 void getAddressOperands(const SystemZRRIAddressMode &AM, 90 SDValue &Base, SDValue &Disp, 91 SDValue &Index); 92 93 public: 94 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 95 : SelectionDAGISel(TM, OptLevel), 96 Lowering(*TM.getTargetLowering()), 97 Subtarget(*TM.getSubtargetImpl()) { } 98 99 virtual void InstructionSelect(); 100 101 virtual const char *getPassName() const { 102 return "SystemZ DAG->DAG Pattern Instruction Selection"; 103 } 104 105 /// getI16Imm - Return a target constant with the specified value, of type 106 /// i16. 107 inline SDValue getI16Imm(uint64_t Imm) { 108 return CurDAG->getTargetConstant(Imm, MVT::i16); 109 } 110 111 /// getI32Imm - Return a target constant with the specified value, of type 112 /// i32. 113 inline SDValue getI32Imm(uint64_t Imm) { 114 return CurDAG->getTargetConstant(Imm, MVT::i32); 115 } 116 117 // Include the pieces autogenerated from the target description. 118 #include "SystemZGenDAGISel.inc" 119 120 private: 121 bool SelectAddrRI12Only(SDValue Op, SDValue& Addr, 122 SDValue &Base, SDValue &Disp); 123 bool SelectAddrRI12(SDValue Op, SDValue& Addr, 124 SDValue &Base, SDValue &Disp, 125 bool is12BitOnly = false); 126 bool SelectAddrRI(SDValue Op, SDValue& Addr, 127 SDValue &Base, SDValue &Disp); 128 bool SelectAddrRRI12(SDValue Op, SDValue Addr, 129 SDValue &Base, SDValue &Disp, SDValue &Index); 130 bool SelectAddrRRI20(SDValue Op, SDValue Addr, 131 SDValue &Base, SDValue &Disp, SDValue &Index); 132 bool SelectLAAddr(SDValue Op, SDValue Addr, 133 SDValue &Base, SDValue &Disp, SDValue &Index); 134 135 SDNode *Select(SDValue Op); 136 137 bool TryFoldLoad(SDValue P, SDValue N, 138 SDValue &Base, SDValue &Disp, SDValue &Index); 139 140 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, 141 bool is12Bit, unsigned Depth = 0); 142 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM); 143 bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM, 144 bool is12Bit); 145 146 #ifndef NDEBUG 147 unsigned Indent; 148 #endif 149 }; 150} // end anonymous namespace 151 152/// createSystemZISelDag - This pass converts a legalized DAG into a 153/// SystemZ-specific DAG, ready for instruction scheduling. 154/// 155FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 156 CodeGenOpt::Level OptLevel) { 157 return new SystemZDAGToDAGISel(TM, OptLevel); 158} 159 160/// isImmSExt20 - This method tests to see if the node is either a 32-bit 161/// or 64-bit immediate, and if the value can be accurately represented as a 162/// sign extension from a 20-bit value. If so, this returns true and the 163/// immediate. 164static bool isImmSExt20(int64_t Val, int64_t &Imm) { 165 if (Val >= -524288 && Val <= 524287) { 166 Imm = Val; 167 return true; 168 } 169 return false; 170} 171 172/// isImmZExt12 - This method tests to see if the node is either a 32-bit 173/// or 64-bit immediate, and if the value can be accurately represented as a 174/// zero extension from a 12-bit value. If so, this returns true and the 175/// immediate. 176static bool isImmZExt12(int64_t Val, int64_t &Imm) { 177 if (Val >= 0 && Val <= 0xFFF) { 178 Imm = Val; 179 return true; 180 } 181 return false; 182} 183 184/// MatchAddress - Add the specified node to the specified addressing mode, 185/// returning true if it cannot be done. This just pattern matches for the 186/// addressing mode. 187bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM, 188 bool is12Bit, unsigned Depth) { 189 DebugLoc dl = N.getDebugLoc(); 190 DOUT << "MatchAddress: "; DEBUG(AM.dump()); 191 // Limit recursion. 192 if (Depth > 5) 193 return MatchAddressBase(N, AM); 194 195 // FIXME: We can perform better here. If we have something like 196 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of 197 // imm into addressing mode. 198 switch (N.getOpcode()) { 199 default: break; 200 case ISD::Constant: { 201 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 202 int64_t Imm; 203 bool Match = (is12Bit ? 204 isImmZExt12(AM.Disp + Val, Imm) : 205 isImmSExt20(AM.Disp + Val, Imm)); 206 if (Match) { 207 AM.Disp = Imm; 208 return false; 209 } 210 break; 211 } 212 213 case ISD::FrameIndex: 214 if (AM.BaseType == SystemZRRIAddressMode::RegBase && 215 AM.Base.Reg.getNode() == 0) { 216 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase; 217 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 218 return false; 219 } 220 break; 221 222 case ISD::SUB: { 223 // Given A-B, if A can be completely folded into the address and 224 // the index field with the index field unused, use -B as the index. 225 // This is a win if a has multiple parts that can be folded into 226 // the address. Also, this saves a mov if the base register has 227 // other uses, since it avoids a two-address sub instruction, however 228 // it costs an additional mov if the index register has other uses. 229 230 // Test if the LHS of the sub can be folded. 231 SystemZRRIAddressMode Backup = AM; 232 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) { 233 AM = Backup; 234 break; 235 } 236 // Test if the index field is free for use. 237 if (AM.IndexReg.getNode() && !AM.isRI) { 238 AM = Backup; 239 break; 240 } 241 242 // If the base is a register with multiple uses, this transformation may 243 // save a mov. Otherwise it's probably better not to do it. 244 if (AM.BaseType == SystemZRRIAddressMode::RegBase && 245 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) { 246 AM = Backup; 247 break; 248 } 249 250 // Ok, the transformation is legal and appears profitable. Go for it. 251 SDValue RHS = N.getNode()->getOperand(1); 252 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 253 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 254 AM.IndexReg = Neg; 255 256 // Insert the new nodes into the topological ordering. 257 if (Zero.getNode()->getNodeId() == -1 || 258 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) { 259 CurDAG->RepositionNode(N.getNode(), Zero.getNode()); 260 Zero.getNode()->setNodeId(N.getNode()->getNodeId()); 261 } 262 if (Neg.getNode()->getNodeId() == -1 || 263 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) { 264 CurDAG->RepositionNode(N.getNode(), Neg.getNode()); 265 Neg.getNode()->setNodeId(N.getNode()->getNodeId()); 266 } 267 return false; 268 } 269 270 case ISD::ADD: { 271 SystemZRRIAddressMode Backup = AM; 272 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) && 273 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1)) 274 return false; 275 AM = Backup; 276 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) && 277 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) 278 return false; 279 AM = Backup; 280 281 // If we couldn't fold both operands into the address at the same time, 282 // see if we can just put each operand into a register and fold at least 283 // the add. 284 if (!AM.isRI && 285 AM.BaseType == SystemZRRIAddressMode::RegBase && 286 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) { 287 AM.Base.Reg = N.getNode()->getOperand(0); 288 AM.IndexReg = N.getNode()->getOperand(1); 289 return false; 290 } 291 break; 292 } 293 294 case ISD::OR: 295 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 296 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 297 SystemZRRIAddressMode Backup = AM; 298 int64_t Offset = CN->getSExtValue(); 299 int64_t Imm; 300 bool MatchOffset = (is12Bit ? 301 isImmZExt12(AM.Disp + Offset, Imm) : 302 isImmSExt20(AM.Disp + Offset, Imm)); 303 // The resultant disp must fit in 12 or 20-bits. 304 if (MatchOffset && 305 // LHS should be an addr mode. 306 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) && 307 // Check to see if the LHS & C is zero. 308 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { 309 AM.Disp = Imm; 310 return false; 311 } 312 AM = Backup; 313 } 314 break; 315 } 316 317 return MatchAddressBase(N, AM); 318} 319 320/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 321/// specified addressing mode without any further recursion. 322bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N, 323 SystemZRRIAddressMode &AM) { 324 // Is the base register already occupied? 325 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) { 326 // If so, check to see if the index register is set. 327 if (AM.IndexReg.getNode() == 0 && !AM.isRI) { 328 AM.IndexReg = N; 329 return false; 330 } 331 332 // Otherwise, we cannot select it. 333 return true; 334 } 335 336 // Default, generate it as a register. 337 AM.BaseType = SystemZRRIAddressMode::RegBase; 338 AM.Base.Reg = N; 339 return false; 340} 341 342void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM, 343 SDValue &Base, SDValue &Disp) { 344 if (AM.BaseType == SystemZRRIAddressMode::RegBase) 345 Base = AM.Base.Reg; 346 else 347 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()); 348 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64); 349} 350 351void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, 352 SDValue &Base, SDValue &Disp, 353 SDValue &Index) { 354 getAddressOperandsRI(AM, Base, Disp); 355 Index = AM.IndexReg; 356} 357 358/// Returns true if the address can be represented by a base register plus 359/// an unsigned 12-bit displacement [r+imm]. 360bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr, 361 SDValue &Base, SDValue &Disp) { 362 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true); 363} 364 365bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr, 366 SDValue &Base, SDValue &Disp, 367 bool is12BitOnly) { 368 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true); 369 bool Done = false; 370 371 if (!Addr.hasOneUse()) { 372 unsigned Opcode = Addr.getOpcode(); 373 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 374 // If we are able to fold N into addressing mode, then we'll allow it even 375 // if N has multiple uses. In general, addressing computation is used as 376 // addresses by all of its uses. But watch out for CopyToReg uses, that 377 // means the address computation is liveout. It will be computed by a LA 378 // so we want to avoid computing the address twice. 379 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 380 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 381 if (UI->getOpcode() == ISD::CopyToReg) { 382 MatchAddressBase(Addr, AM12); 383 Done = true; 384 break; 385 } 386 } 387 } 388 } 389 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true)) 390 return false; 391 392 // Check, whether we can match stuff using 20-bit displacements 393 if (!Done && !is12BitOnly && 394 !MatchAddress(Addr, AM20, /* is12Bit */ false)) 395 if (AM12.Disp == 0 && AM20.Disp != 0) 396 return false; 397 398 DOUT << "MatchAddress (final): "; DEBUG(AM12.dump()); 399 400 MVT VT = Addr.getValueType(); 401 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) { 402 if (!AM12.Base.Reg.getNode()) 403 AM12.Base.Reg = CurDAG->getRegister(0, VT); 404 } 405 406 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!"); 407 408 getAddressOperandsRI(AM12, Base, Disp); 409 410 return true; 411} 412 413/// Returns true if the address can be represented by a base register plus 414/// a signed 20-bit displacement [r+imm]. 415bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr, 416 SDValue &Base, SDValue &Disp) { 417 SystemZRRIAddressMode AM(/*isRI*/true); 418 bool Done = false; 419 420 if (!Addr.hasOneUse()) { 421 unsigned Opcode = Addr.getOpcode(); 422 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 423 // If we are able to fold N into addressing mode, then we'll allow it even 424 // if N has multiple uses. In general, addressing computation is used as 425 // addresses by all of its uses. But watch out for CopyToReg uses, that 426 // means the address computation is liveout. It will be computed by a LA 427 // so we want to avoid computing the address twice. 428 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 429 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 430 if (UI->getOpcode() == ISD::CopyToReg) { 431 MatchAddressBase(Addr, AM); 432 Done = true; 433 break; 434 } 435 } 436 } 437 } 438 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false)) 439 return false; 440 441 DOUT << "MatchAddress (final): "; DEBUG(AM.dump()); 442 443 MVT VT = Addr.getValueType(); 444 if (AM.BaseType == SystemZRRIAddressMode::RegBase) { 445 if (!AM.Base.Reg.getNode()) 446 AM.Base.Reg = CurDAG->getRegister(0, VT); 447 } 448 449 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!"); 450 451 getAddressOperandsRI(AM, Base, Disp); 452 453 return true; 454} 455 456/// Returns true if the address can be represented by a base register plus 457/// index register plus an unsigned 12-bit displacement [base + idx + imm]. 458bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr, 459 SDValue &Base, SDValue &Disp, SDValue &Index) { 460 SystemZRRIAddressMode AM20, AM12; 461 bool Done = false; 462 463 if (!Addr.hasOneUse()) { 464 unsigned Opcode = Addr.getOpcode(); 465 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 466 // If we are able to fold N into addressing mode, then we'll allow it even 467 // if N has multiple uses. In general, addressing computation is used as 468 // addresses by all of its uses. But watch out for CopyToReg uses, that 469 // means the address computation is liveout. It will be computed by a LA 470 // so we want to avoid computing the address twice. 471 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 472 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 473 if (UI->getOpcode() == ISD::CopyToReg) { 474 MatchAddressBase(Addr, AM12); 475 Done = true; 476 break; 477 } 478 } 479 } 480 } 481 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true)) 482 return false; 483 484 // Check, whether we can match stuff using 20-bit displacements 485 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false)) 486 if (AM12.Disp == 0 && AM20.Disp != 0) 487 return false; 488 489 DOUT << "MatchAddress (final): "; DEBUG(AM12.dump()); 490 491 MVT VT = Addr.getValueType(); 492 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) { 493 if (!AM12.Base.Reg.getNode()) 494 AM12.Base.Reg = CurDAG->getRegister(0, VT); 495 } 496 497 if (!AM12.IndexReg.getNode()) 498 AM12.IndexReg = CurDAG->getRegister(0, VT); 499 500 getAddressOperands(AM12, Base, Disp, Index); 501 502 return true; 503} 504 505/// Returns true if the address can be represented by a base register plus 506/// index register plus a signed 20-bit displacement [base + idx + imm]. 507bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr, 508 SDValue &Base, SDValue &Disp, SDValue &Index) { 509 SystemZRRIAddressMode AM; 510 bool Done = false; 511 512 if (!Addr.hasOneUse()) { 513 unsigned Opcode = Addr.getOpcode(); 514 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) { 515 // If we are able to fold N into addressing mode, then we'll allow it even 516 // if N has multiple uses. In general, addressing computation is used as 517 // addresses by all of its uses. But watch out for CopyToReg uses, that 518 // means the address computation is liveout. It will be computed by a LA 519 // so we want to avoid computing the address twice. 520 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 521 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 522 if (UI->getOpcode() == ISD::CopyToReg) { 523 MatchAddressBase(Addr, AM); 524 Done = true; 525 break; 526 } 527 } 528 } 529 } 530 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false)) 531 return false; 532 533 DOUT << "MatchAddress (final): "; DEBUG(AM.dump()); 534 535 MVT VT = Addr.getValueType(); 536 if (AM.BaseType == SystemZRRIAddressMode::RegBase) { 537 if (!AM.Base.Reg.getNode()) 538 AM.Base.Reg = CurDAG->getRegister(0, VT); 539 } 540 541 if (!AM.IndexReg.getNode()) 542 AM.IndexReg = CurDAG->getRegister(0, VT); 543 544 getAddressOperands(AM, Base, Disp, Index); 545 546 return true; 547} 548 549/// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing 550/// mode it matches can be cost effectively emitted as an LA/LAY instruction. 551bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr, 552 SDValue &Base, SDValue &Disp, SDValue &Index) { 553 SystemZRRIAddressMode AM; 554 555 if (MatchAddress(Addr, AM, false)) 556 return false; 557 558 MVT VT = Addr.getValueType(); 559 unsigned Complexity = 0; 560 if (AM.BaseType == SystemZRRIAddressMode::RegBase) 561 if (AM.Base.Reg.getNode()) 562 Complexity = 1; 563 else 564 AM.Base.Reg = CurDAG->getRegister(0, VT); 565 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase) 566 Complexity = 4; 567 568 if (AM.IndexReg.getNode()) 569 Complexity += 1; 570 else 571 AM.IndexReg = CurDAG->getRegister(0, VT); 572 573 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode())) 574 Complexity += 1; 575 576 if (Complexity > 2) { 577 getAddressOperands(AM, Base, Disp, Index); 578 return true; 579 } 580 581 return false; 582} 583 584bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N, 585 SDValue &Base, SDValue &Disp, SDValue &Index) { 586 if (ISD::isNON_EXTLoad(N.getNode()) && 587 N.hasOneUse() && 588 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode())) 589 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index); 590 return false; 591} 592 593/// InstructionSelect - This callback is invoked by 594/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 595void SystemZDAGToDAGISel::InstructionSelect() { 596 DEBUG(BB->dump()); 597 598 // Codegen the basic block. 599#ifndef NDEBUG 600 DOUT << "===== Instruction selection begins:\n"; 601 Indent = 0; 602#endif 603 SelectRoot(*CurDAG); 604#ifndef NDEBUG 605 DOUT << "===== Instruction selection ends:\n"; 606#endif 607 608 CurDAG->RemoveDeadNodes(); 609} 610 611SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { 612 SDNode *Node = Op.getNode(); 613 MVT NVT = Node->getValueType(0); 614 DebugLoc dl = Op.getDebugLoc(); 615 unsigned Opcode = Node->getOpcode(); 616 617 // Dump information about the Node being selected 618 #ifndef NDEBUG 619 DOUT << std::string(Indent, ' ') << "Selecting: "; 620 DEBUG(Node->dump(CurDAG)); 621 DOUT << "\n"; 622 Indent += 2; 623 #endif 624 625 // If we have a custom node, we already have selected! 626 if (Node->isMachineOpcode()) { 627 #ifndef NDEBUG 628 DOUT << std::string(Indent-2, ' ') << "== "; 629 DEBUG(Node->dump(CurDAG)); 630 DOUT << "\n"; 631 Indent -= 2; 632 #endif 633 return NULL; // Already selected. 634 } 635 636 switch (Opcode) { 637 default: break; 638 case ISD::SDIVREM: { 639 unsigned Opc, MOpc, ClrOpc = 0; 640 SDValue N0 = Node->getOperand(0); 641 SDValue N1 = Node->getOperand(1); 642 643 MVT ResVT; 644 switch (NVT.getSimpleVT()) { 645 default: assert(0 && "Unsupported VT!"); 646 case MVT::i32: 647 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; 648 ClrOpc = SystemZ::MOV64Pr0_even; 649 ResVT = MVT::v2i32; 650 break; 651 case MVT::i64: 652 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m; 653 ResVT = MVT::v2i64; 654 break; 655 } 656 657 SDValue Tmp0, Tmp1, Tmp2; 658 bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2); 659 660 // Prepare the dividend 661 SDNode *Dividend = N0.getNode(); 662 663 // Insert prepared dividend into suitable 'subreg' 664 SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, 665 dl, ResVT); 666 Dividend = 667 CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, 668 SDValue(Tmp, 0), SDValue(Dividend, 0), 669 CurDAG->getTargetConstant(subreg_odd, MVT::i32)); 670 671 // Zero out even subreg, if needed 672 if (ClrOpc) 673 Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); 674 675 SDNode *Result; 676 SDValue DivVal = SDValue(Dividend, 0); 677 if (foldedLoad) { 678 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; 679 Result = CurDAG->getTargetNode(MOpc, dl, ResVT, Ops, array_lengthof(Ops)); 680 // Update the chain. 681 ReplaceUses(N1.getValue(1), SDValue(Result, 0)); 682 } else { 683 Result = CurDAG->getTargetNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1); 684 } 685 686 // Copy the division (odd subreg) result, if it is needed. 687 if (!Op.getValue(0).use_empty()) { 688 SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, 689 dl, NVT, 690 SDValue(Result, 0), 691 CurDAG->getTargetConstant(subreg_odd, 692 MVT::i32)); 693 ReplaceUses(Op.getValue(0), SDValue(Div, 0)); 694 #ifndef NDEBUG 695 DOUT << std::string(Indent-2, ' ') << "=> "; 696 DEBUG(Result->dump(CurDAG)); 697 DOUT << "\n"; 698 #endif 699 } 700 701 // Copy the remainder (even subreg) result, if it is needed. 702 if (!Op.getValue(1).use_empty()) { 703 SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, 704 dl, NVT, 705 SDValue(Result, 0), 706 CurDAG->getTargetConstant(subreg_even, 707 MVT::i32)); 708 ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); 709 #ifndef NDEBUG 710 DOUT << std::string(Indent-2, ' ') << "=> "; 711 DEBUG(Result->dump(CurDAG)); 712 DOUT << "\n"; 713 #endif 714 } 715 716#ifndef NDEBUG 717 Indent -= 2; 718#endif 719 720 return NULL; 721 } 722 case ISD::UDIVREM: { 723 unsigned Opc, MOpc, ClrOpc; 724 SDValue N0 = Node->getOperand(0); 725 SDValue N1 = Node->getOperand(1); 726 MVT ResVT; 727 728 switch (NVT.getSimpleVT()) { 729 default: assert(0 && "Unsupported VT!"); 730 case MVT::i32: 731 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; 732 ClrOpc = SystemZ::MOV64Pr0_even; 733 ResVT = MVT::v2i32; 734 break; 735 case MVT::i64: 736 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; 737 ClrOpc = SystemZ::MOV128r0_even; 738 ResVT = MVT::v2i64; 739 break; 740 } 741 742 SDValue Tmp0, Tmp1, Tmp2; 743 bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2); 744 745 // Prepare the dividend 746 SDNode *Dividend = N0.getNode(); 747 748 // Insert prepared dividend into suitable 'subreg' 749 SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, 750 dl, ResVT); 751 Dividend = 752 CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, 753 SDValue(Tmp, 0), SDValue(Dividend, 0), 754 CurDAG->getTargetConstant(subreg_odd, MVT::i32)); 755 756 // Zero out even subreg 757 Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); 758 759 SDValue DivVal = SDValue(Dividend, 0); 760 SDNode *Result; 761 if (foldedLoad) { 762 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; 763 Result = CurDAG->getTargetNode(MOpc, dl,ResVT, 764 Ops, array_lengthof(Ops)); 765 // Update the chain. 766 ReplaceUses(N1.getValue(1), SDValue(Result, 0)); 767 } else { 768 Result = CurDAG->getTargetNode(Opc, dl, ResVT, DivVal, N1); 769 } 770 771 // Copy the division (odd subreg) result, if it is needed. 772 if (!Op.getValue(0).use_empty()) { 773 SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, 774 dl, NVT, 775 SDValue(Result, 0), 776 CurDAG->getTargetConstant(subreg_odd, 777 MVT::i32)); 778 ReplaceUses(Op.getValue(0), SDValue(Div, 0)); 779 #ifndef NDEBUG 780 DOUT << std::string(Indent-2, ' ') << "=> "; 781 DEBUG(Result->dump(CurDAG)); 782 DOUT << "\n"; 783 #endif 784 } 785 786 // Copy the remainder (even subreg) result, if it is needed. 787 if (!Op.getValue(1).use_empty()) { 788 SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, 789 dl, NVT, 790 SDValue(Result, 0), 791 CurDAG->getTargetConstant(subreg_even, 792 MVT::i32)); 793 ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); 794 #ifndef NDEBUG 795 DOUT << std::string(Indent-2, ' ') << "=> "; 796 DEBUG(Result->dump(CurDAG)); 797 DOUT << "\n"; 798 #endif 799 } 800 801#ifndef NDEBUG 802 Indent -= 2; 803#endif 804 805 return NULL; 806 } 807 } 808 809 // Select the default instruction 810 SDNode *ResNode = SelectCode(Op); 811 812 #ifndef NDEBUG 813 DOUT << std::string(Indent-2, ' ') << "=> "; 814 if (ResNode == NULL || ResNode == Op.getNode()) 815 DEBUG(Op.getNode()->dump(CurDAG)); 816 else 817 DEBUG(ResNode->dump(CurDAG)); 818 DOUT << "\n"; 819 Indent -= 2; 820 #endif 821 822 return ResNode; 823} 824