SystemZISelDAGToDAG.cpp revision 9dffd71d0af3d78ee1f21865dd064fb43bc623be
1//===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SystemZ target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SystemZTargetMachine.h" 15#include "llvm/Analysis/AliasAnalysis.h" 16#include "llvm/CodeGen/SelectionDAGISel.h" 17#include "llvm/Support/Debug.h" 18#include "llvm/Support/raw_ostream.h" 19 20using namespace llvm; 21 22namespace { 23// Used to build addressing modes. 24struct SystemZAddressingMode { 25 // The shape of the address. 26 enum AddrForm { 27 // base+displacement 28 FormBD, 29 30 // base+displacement+index for load and store operands 31 FormBDXNormal, 32 33 // base+displacement+index for load address operands 34 FormBDXLA, 35 36 // base+displacement+index+ADJDYNALLOC 37 FormBDXDynAlloc 38 }; 39 AddrForm Form; 40 41 // The type of displacement. The enum names here correspond directly 42 // to the definitions in SystemZOperand.td. We could split them into 43 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it. 44 enum DispRange { 45 Disp12Only, 46 Disp12Pair, 47 Disp20Only, 48 Disp20Only128, 49 Disp20Pair 50 }; 51 DispRange DR; 52 53 // The parts of the address. The address is equivalent to: 54 // 55 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 56 SDValue Base; 57 int64_t Disp; 58 SDValue Index; 59 bool IncludesDynAlloc; 60 61 SystemZAddressingMode(AddrForm form, DispRange dr) 62 : Form(form), DR(dr), Base(), Disp(0), Index(), 63 IncludesDynAlloc(false) {} 64 65 // True if the address can have an index register. 66 bool hasIndexField() { return Form != FormBD; } 67 68 // True if the address can (and must) include ADJDYNALLOC. 69 bool isDynAlloc() { return Form == FormBDXDynAlloc; } 70 71 void dump() { 72 errs() << "SystemZAddressingMode " << this << '\n'; 73 74 errs() << " Base "; 75 if (Base.getNode() != 0) 76 Base.getNode()->dump(); 77 else 78 errs() << "null\n"; 79 80 if (hasIndexField()) { 81 errs() << " Index "; 82 if (Index.getNode() != 0) 83 Index.getNode()->dump(); 84 else 85 errs() << "null\n"; 86 } 87 88 errs() << " Disp " << Disp; 89 if (IncludesDynAlloc) 90 errs() << " + ADJDYNALLOC"; 91 errs() << '\n'; 92 } 93}; 94 95// Return a mask with Count low bits set. 96static uint64_t allOnes(unsigned int Count) { 97 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1; 98} 99 100// Represents operands 2 to 5 of a ROTATE AND ... SELECTED BITS operation. 101// The operands are: Input (R2), Start (I3), End (I4) and Rotate (I5). 102// The operand value is effectively (and (rotl Input Rotate) Mask) and 103// has BitSize bits. 104struct RxSBGOperands { 105 RxSBGOperands(SDValue N) 106 : BitSize(N.getValueType().getSizeInBits()), Mask(allOnes(BitSize)), 107 Input(N), Start(64 - BitSize), End(63), Rotate(0) {} 108 109 unsigned BitSize; 110 uint64_t Mask; 111 SDValue Input; 112 unsigned Start; 113 unsigned End; 114 unsigned Rotate; 115}; 116 117class SystemZDAGToDAGISel : public SelectionDAGISel { 118 const SystemZTargetLowering &Lowering; 119 const SystemZSubtarget &Subtarget; 120 121 // Used by SystemZOperands.td to create integer constants. 122 inline SDValue getImm(const SDNode *Node, uint64_t Imm) { 123 return CurDAG->getTargetConstant(Imm, Node->getValueType(0)); 124 } 125 126 // Try to fold more of the base or index of AM into AM, where IsBase 127 // selects between the base and index. 128 bool expandAddress(SystemZAddressingMode &AM, bool IsBase); 129 130 // Try to describe N in AM, returning true on success. 131 bool selectAddress(SDValue N, SystemZAddressingMode &AM); 132 133 // Extract individual target operands from matched address AM. 134 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 135 SDValue &Base, SDValue &Disp); 136 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 137 SDValue &Base, SDValue &Disp, SDValue &Index); 138 139 // Try to match Addr as a FormBD address with displacement type DR. 140 // Return true on success, storing the base and displacement in 141 // Base and Disp respectively. 142 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 143 SDValue &Base, SDValue &Disp); 144 145 // Try to match Addr as a FormBDX* address of form Form with 146 // displacement type DR. Return true on success, storing the base, 147 // displacement and index in Base, Disp and Index respectively. 148 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form, 149 SystemZAddressingMode::DispRange DR, SDValue Addr, 150 SDValue &Base, SDValue &Disp, SDValue &Index); 151 152 // PC-relative address matching routines used by SystemZOperands.td. 153 bool selectPCRelAddress(SDValue Addr, SDValue &Target) { 154 if (Addr.getOpcode() == SystemZISD::PCREL_WRAPPER) { 155 Target = Addr.getOperand(0); 156 return true; 157 } 158 return false; 159 } 160 161 // BD matching routines used by SystemZOperands.td. 162 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) { 163 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp); 164 } 165 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) { 166 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp); 167 } 168 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) { 169 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp); 170 } 171 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) { 172 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp); 173 } 174 175 // BDX matching routines used by SystemZOperands.td. 176 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 177 SDValue &Index) { 178 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 179 SystemZAddressingMode::Disp12Only, 180 Addr, Base, Disp, Index); 181 } 182 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 183 SDValue &Index) { 184 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 185 SystemZAddressingMode::Disp12Pair, 186 Addr, Base, Disp, Index); 187 } 188 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, 189 SDValue &Index) { 190 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc, 191 SystemZAddressingMode::Disp12Only, 192 Addr, Base, Disp, Index); 193 } 194 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, 195 SDValue &Index) { 196 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 197 SystemZAddressingMode::Disp20Only, 198 Addr, Base, Disp, Index); 199 } 200 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, 201 SDValue &Index) { 202 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 203 SystemZAddressingMode::Disp20Only128, 204 Addr, Base, Disp, Index); 205 } 206 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 207 SDValue &Index) { 208 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal, 209 SystemZAddressingMode::Disp20Pair, 210 Addr, Base, Disp, Index); 211 } 212 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 213 SDValue &Index) { 214 return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 215 SystemZAddressingMode::Disp12Pair, 216 Addr, Base, Disp, Index); 217 } 218 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, 219 SDValue &Index) { 220 return selectBDXAddr(SystemZAddressingMode::FormBDXLA, 221 SystemZAddressingMode::Disp20Pair, 222 Addr, Base, Disp, Index); 223 } 224 225 // Check whether (or Op (and X InsertMask)) is effectively an insertion 226 // of X into bits InsertMask of some Y != Op. Return true if so and 227 // set Op to that Y. 228 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask); 229 230 // Try to fold some of RxSBG.Input into other fields of RxSBG. 231 // Return true on success. 232 bool expandRxSBG(RxSBGOperands &RxSBG); 233 234 // Return an undefined i64 value. 235 SDValue getUNDEF64(SDLoc DL); 236 237 // Convert N to VT, if it isn't already. 238 SDValue convertTo(SDLoc DL, EVT VT, SDValue N); 239 240 // Try to implement AND or shift node N using RISBG with the zero flag set. 241 // Return the selected node on success, otherwise return null. 242 SDNode *tryRISBGZero(SDNode *N); 243 244 // Try to use RISBG or Opcode to implement OR or XOR node N. 245 // Return the selected node on success, otherwise return null. 246 SDNode *tryRxSBG(SDNode *N, unsigned Opcode); 247 248 // If Op0 is null, then Node is a constant that can be loaded using: 249 // 250 // (Opcode UpperVal LowerVal) 251 // 252 // If Op0 is nonnull, then Node can be implemented using: 253 // 254 // (Opcode (Opcode Op0 UpperVal) LowerVal) 255 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 256 uint64_t UpperVal, uint64_t LowerVal); 257 258 bool storeLoadCanUseMVC(SDNode *N) const; 259 260public: 261 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel) 262 : SelectionDAGISel(TM, OptLevel), 263 Lowering(*TM.getTargetLowering()), 264 Subtarget(*TM.getSubtargetImpl()) { } 265 266 // Override MachineFunctionPass. 267 virtual const char *getPassName() const LLVM_OVERRIDE { 268 return "SystemZ DAG->DAG Pattern Instruction Selection"; 269 } 270 271 // Override SelectionDAGISel. 272 virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE; 273 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 274 char ConstraintCode, 275 std::vector<SDValue> &OutOps) 276 LLVM_OVERRIDE; 277 278 // Include the pieces autogenerated from the target description. 279 #include "SystemZGenDAGISel.inc" 280}; 281} // end anonymous namespace 282 283FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, 284 CodeGenOpt::Level OptLevel) { 285 return new SystemZDAGToDAGISel(TM, OptLevel); 286} 287 288// Return true if Val should be selected as a displacement for an address 289// with range DR. Here we're interested in the range of both the instruction 290// described by DR and of any pairing instruction. 291static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 292 switch (DR) { 293 case SystemZAddressingMode::Disp12Only: 294 return isUInt<12>(Val); 295 296 case SystemZAddressingMode::Disp12Pair: 297 case SystemZAddressingMode::Disp20Only: 298 case SystemZAddressingMode::Disp20Pair: 299 return isInt<20>(Val); 300 301 case SystemZAddressingMode::Disp20Only128: 302 return isInt<20>(Val) && isInt<20>(Val + 8); 303 } 304 llvm_unreachable("Unhandled displacement range"); 305} 306 307// Change the base or index in AM to Value, where IsBase selects 308// between the base and index. 309static void changeComponent(SystemZAddressingMode &AM, bool IsBase, 310 SDValue Value) { 311 if (IsBase) 312 AM.Base = Value; 313 else 314 AM.Index = Value; 315} 316 317// The base or index of AM is equivalent to Value + ADJDYNALLOC, 318// where IsBase selects between the base and index. Try to fold the 319// ADJDYNALLOC into AM. 320static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, 321 SDValue Value) { 322 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) { 323 changeComponent(AM, IsBase, Value); 324 AM.IncludesDynAlloc = true; 325 return true; 326 } 327 return false; 328} 329 330// The base of AM is equivalent to Base + Index. Try to use Index as 331// the index register. 332static bool expandIndex(SystemZAddressingMode &AM, SDValue Base, 333 SDValue Index) { 334 if (AM.hasIndexField() && !AM.Index.getNode()) { 335 AM.Base = Base; 336 AM.Index = Index; 337 return true; 338 } 339 return false; 340} 341 342// The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 343// between the base and index. Try to fold Op1 into AM's displacement. 344static bool expandDisp(SystemZAddressingMode &AM, bool IsBase, 345 SDValue Op0, ConstantSDNode *Op1) { 346 // First try adjusting the displacement. 347 int64_t TestDisp = AM.Disp + Op1->getSExtValue(); 348 if (selectDisp(AM.DR, TestDisp)) { 349 changeComponent(AM, IsBase, Op0); 350 AM.Disp = TestDisp; 351 return true; 352 } 353 354 // We could consider forcing the displacement into a register and 355 // using it as an index, but it would need to be carefully tuned. 356 return false; 357} 358 359bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM, 360 bool IsBase) { 361 SDValue N = IsBase ? AM.Base : AM.Index; 362 unsigned Opcode = N.getOpcode(); 363 if (Opcode == ISD::TRUNCATE) { 364 N = N.getOperand(0); 365 Opcode = N.getOpcode(); 366 } 367 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { 368 SDValue Op0 = N.getOperand(0); 369 SDValue Op1 = N.getOperand(1); 370 371 unsigned Op0Code = Op0->getOpcode(); 372 unsigned Op1Code = Op1->getOpcode(); 373 374 if (Op0Code == SystemZISD::ADJDYNALLOC) 375 return expandAdjDynAlloc(AM, IsBase, Op1); 376 if (Op1Code == SystemZISD::ADJDYNALLOC) 377 return expandAdjDynAlloc(AM, IsBase, Op0); 378 379 if (Op0Code == ISD::Constant) 380 return expandDisp(AM, IsBase, Op1, cast<ConstantSDNode>(Op0)); 381 if (Op1Code == ISD::Constant) 382 return expandDisp(AM, IsBase, Op0, cast<ConstantSDNode>(Op1)); 383 384 if (IsBase && expandIndex(AM, Op0, Op1)) 385 return true; 386 } 387 return false; 388} 389 390// Return true if an instruction with displacement range DR should be 391// used for displacement value Val. selectDisp(DR, Val) must already hold. 392static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) { 393 assert(selectDisp(DR, Val) && "Invalid displacement"); 394 switch (DR) { 395 case SystemZAddressingMode::Disp12Only: 396 case SystemZAddressingMode::Disp20Only: 397 case SystemZAddressingMode::Disp20Only128: 398 return true; 399 400 case SystemZAddressingMode::Disp12Pair: 401 // Use the other instruction if the displacement is too large. 402 return isUInt<12>(Val); 403 404 case SystemZAddressingMode::Disp20Pair: 405 // Use the other instruction if the displacement is small enough. 406 return !isUInt<12>(Val); 407 } 408 llvm_unreachable("Unhandled displacement range"); 409} 410 411// Return true if Base + Disp + Index should be performed by LA(Y). 412static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) { 413 // Don't use LA(Y) for constants. 414 if (!Base) 415 return false; 416 417 // Always use LA(Y) for frame addresses, since we know that the destination 418 // register is almost always (perhaps always) going to be different from 419 // the frame register. 420 if (Base->getOpcode() == ISD::FrameIndex) 421 return true; 422 423 if (Disp) { 424 // Always use LA(Y) if there is a base, displacement and index. 425 if (Index) 426 return true; 427 428 // Always use LA if the displacement is small enough. It should always 429 // be no worse than AGHI (and better if it avoids a move). 430 if (isUInt<12>(Disp)) 431 return true; 432 433 // For similar reasons, always use LAY if the constant is too big for AGHI. 434 // LAY should be no worse than AGFI. 435 if (!isInt<16>(Disp)) 436 return true; 437 } else { 438 // Don't use LA for plain registers. 439 if (!Index) 440 return false; 441 442 // Don't use LA for plain addition if the index operand is only used 443 // once. It should be a natural two-operand addition in that case. 444 if (Index->hasOneUse()) 445 return false; 446 447 // Prefer addition if the second operation is sign-extended, in the 448 // hope of using AGF. 449 unsigned IndexOpcode = Index->getOpcode(); 450 if (IndexOpcode == ISD::SIGN_EXTEND || 451 IndexOpcode == ISD::SIGN_EXTEND_INREG) 452 return false; 453 } 454 455 // Don't use LA for two-operand addition if either operand is only 456 // used once. The addition instructions are better in that case. 457 if (Base->hasOneUse()) 458 return false; 459 460 return true; 461} 462 463// Return true if Addr is suitable for AM, updating AM if so. 464bool SystemZDAGToDAGISel::selectAddress(SDValue Addr, 465 SystemZAddressingMode &AM) { 466 // Start out assuming that the address will need to be loaded separately, 467 // then try to extend it as much as we can. 468 AM.Base = Addr; 469 470 // First try treating the address as a constant. 471 if (Addr.getOpcode() == ISD::Constant && 472 expandDisp(AM, true, SDValue(), cast<ConstantSDNode>(Addr))) 473 ; 474 else 475 // Otherwise try expanding each component. 476 while (expandAddress(AM, true) || 477 (AM.Index.getNode() && expandAddress(AM, false))) 478 continue; 479 480 // Reject cases where it isn't profitable to use LA(Y). 481 if (AM.Form == SystemZAddressingMode::FormBDXLA && 482 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) 483 return false; 484 485 // Reject cases where the other instruction in a pair should be used. 486 if (!isValidDisp(AM.DR, AM.Disp)) 487 return false; 488 489 // Make sure that ADJDYNALLOC is included where necessary. 490 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) 491 return false; 492 493 DEBUG(AM.dump()); 494 return true; 495} 496 497// Insert a node into the DAG at least before Pos. This will reposition 498// the node as needed, and will assign it a node ID that is <= Pos's ID. 499// Note that this does *not* preserve the uniqueness of node IDs! 500// The selection DAG must no longer depend on their uniqueness when this 501// function is used. 502static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { 503 if (N.getNode()->getNodeId() == -1 || 504 N.getNode()->getNodeId() > Pos->getNodeId()) { 505 DAG->RepositionNode(Pos, N.getNode()); 506 N.getNode()->setNodeId(Pos->getNodeId()); 507 } 508} 509 510void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 511 EVT VT, SDValue &Base, 512 SDValue &Disp) { 513 Base = AM.Base; 514 if (!Base.getNode()) 515 // Register 0 means "no base". This is mostly useful for shifts. 516 Base = CurDAG->getRegister(0, VT); 517 else if (Base.getOpcode() == ISD::FrameIndex) { 518 // Lower a FrameIndex to a TargetFrameIndex. 519 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); 520 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); 521 } else if (Base.getValueType() != VT) { 522 // Truncate values from i64 to i32, for shifts. 523 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && 524 "Unexpected truncation"); 525 SDLoc DL(Base); 526 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); 527 insertDAGNode(CurDAG, Base.getNode(), Trunc); 528 Base = Trunc; 529 } 530 531 // Lower the displacement to a TargetConstant. 532 Disp = CurDAG->getTargetConstant(AM.Disp, VT); 533} 534 535void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, 536 EVT VT, SDValue &Base, 537 SDValue &Disp, SDValue &Index) { 538 getAddressOperands(AM, VT, Base, Disp); 539 540 Index = AM.Index; 541 if (!Index.getNode()) 542 // Register 0 means "no index". 543 Index = CurDAG->getRegister(0, VT); 544} 545 546bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR, 547 SDValue Addr, SDValue &Base, 548 SDValue &Disp) { 549 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR); 550 if (!selectAddress(Addr, AM)) 551 return false; 552 553 getAddressOperands(AM, Addr.getValueType(), Base, Disp); 554 return true; 555} 556 557bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form, 558 SystemZAddressingMode::DispRange DR, 559 SDValue Addr, SDValue &Base, 560 SDValue &Disp, SDValue &Index) { 561 SystemZAddressingMode AM(Form, DR); 562 if (!selectAddress(Addr, AM)) 563 return false; 564 565 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index); 566 return true; 567} 568 569bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op, 570 uint64_t InsertMask) { 571 // We're only interested in cases where the insertion is into some operand 572 // of Op, rather than into Op itself. The only useful case is an AND. 573 if (Op.getOpcode() != ISD::AND) 574 return false; 575 576 // We need a constant mask. 577 ConstantSDNode *MaskNode = 578 dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode()); 579 if (!MaskNode) 580 return false; 581 582 // It's not an insertion of Op.getOperand(0) if the two masks overlap. 583 uint64_t AndMask = MaskNode->getZExtValue(); 584 if (InsertMask & AndMask) 585 return false; 586 587 // It's only an insertion if all bits are covered or are known to be zero. 588 // The inner check covers all cases but is more expensive. 589 uint64_t Used = allOnes(Op.getValueType().getSizeInBits()); 590 if (Used != (AndMask | InsertMask)) { 591 APInt KnownZero, KnownOne; 592 CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne); 593 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue())) 594 return false; 595 } 596 597 Op = Op.getOperand(0); 598 return true; 599} 600 601// Return true if Mask matches the regexp 0*1+0*, given that zero masks 602// have already been filtered out. Store the first set bit in LSB and 603// the number of set bits in Length if so. 604static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) { 605 unsigned First = findFirstSet(Mask); 606 uint64_t Top = (Mask >> First) + 1; 607 if ((Top & -Top) == Top) { 608 LSB = First; 609 Length = findFirstSet(Top); 610 return true; 611 } 612 return false; 613} 614 615// Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used. 616// Return true on success. 617static bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) { 618 if (RxSBG.Rotate != 0) 619 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); 620 Mask &= RxSBG.Mask; 621 622 // Reject trivial all-zero masks. 623 if (Mask == 0) 624 return false; 625 626 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of 627 // the msb and End specifies the index of the lsb. 628 unsigned LSB, Length; 629 if (isStringOfOnes(Mask, LSB, Length)) { 630 RxSBG.Mask = Mask; 631 RxSBG.Start = 63 - (LSB + Length - 1); 632 RxSBG.End = 63 - LSB; 633 return true; 634 } 635 636 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb 637 // of the low 1s and End specifies the lsb of the high 1s. 638 if (isStringOfOnes(Mask ^ allOnes(RxSBG.BitSize), LSB, Length)) { 639 assert(LSB > 0 && "Bottom bit must be set"); 640 assert(LSB + Length < RxSBG.BitSize && "Top bit must be set"); 641 RxSBG.Mask = Mask; 642 RxSBG.Start = 63 - (LSB - 1); 643 RxSBG.End = 63 - (LSB + Length); 644 return true; 645 } 646 647 return false; 648} 649 650// RxSBG.Input is a shift of Count bits in the direction given by IsLeft. 651// Return true if the result depends on the signs or zeros that are 652// shifted in. 653static bool shiftedInBitsMatter(RxSBGOperands &RxSBG, uint64_t Count, 654 bool IsLeft) { 655 // Work out which bits of the shift result are zeros or sign copies. 656 uint64_t ShiftedIn = allOnes(Count); 657 if (!IsLeft) 658 ShiftedIn <<= RxSBG.BitSize - Count; 659 660 // Rotate that mask in the same way as RxSBG.Input is rotated. 661 if (RxSBG.Rotate != 0) 662 ShiftedIn = ((ShiftedIn << RxSBG.Rotate) | 663 (ShiftedIn >> (64 - RxSBG.Rotate))); 664 665 // Fail if any of the zero or sign bits are used. 666 return (ShiftedIn & RxSBG.Mask) != 0; 667} 668 669bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) { 670 SDValue N = RxSBG.Input; 671 unsigned Opcode = N.getOpcode(); 672 switch (Opcode) { 673 case ISD::AND: { 674 ConstantSDNode *MaskNode = 675 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 676 if (!MaskNode) 677 return false; 678 679 SDValue Input = N.getOperand(0); 680 uint64_t Mask = MaskNode->getZExtValue(); 681 if (!refineRxSBGMask(RxSBG, Mask)) { 682 // If some bits of Input are already known zeros, those bits will have 683 // been removed from the mask. See if adding them back in makes the 684 // mask suitable. 685 APInt KnownZero, KnownOne; 686 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); 687 Mask |= KnownZero.getZExtValue(); 688 if (!refineRxSBGMask(RxSBG, Mask)) 689 return false; 690 } 691 RxSBG.Input = Input; 692 return true; 693 } 694 695 case ISD::ROTL: { 696 // Any 64-bit rotate left can be merged into the RxSBG. 697 if (RxSBG.BitSize != 64) 698 return false; 699 ConstantSDNode *CountNode 700 = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 701 if (!CountNode) 702 return false; 703 704 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63; 705 RxSBG.Input = N.getOperand(0); 706 return true; 707 } 708 709 case ISD::SHL: { 710 // Treat (shl X, count) as (and (rotl X, count), ~0<<count). 711 ConstantSDNode *CountNode = 712 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 713 if (!CountNode) 714 return false; 715 716 uint64_t Count = CountNode->getZExtValue(); 717 if (Count < 1 || 718 Count >= RxSBG.BitSize || 719 !refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count) << Count)) 720 return false; 721 722 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63; 723 RxSBG.Input = N.getOperand(0); 724 return true; 725 } 726 727 case ISD::SRL: 728 case ISD::SRA: { 729 ConstantSDNode *CountNode = 730 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode()); 731 if (!CountNode) 732 return false; 733 734 uint64_t Count = CountNode->getZExtValue(); 735 if (Count < 1 || Count >= RxSBG.BitSize) 736 return false; 737 738 if (Opcode == ISD::SRA) { 739 // Treat (sra X, count) as (rotl X, size-count) as long as the top 740 // Count bits from RxSBG.Input are ignored. 741 if (shiftedInBitsMatter(RxSBG, Count, false)) 742 return false; 743 } else { 744 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), 745 // which is similar to SLL above. 746 if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count))) 747 return false; 748 } 749 750 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63; 751 RxSBG.Input = N.getOperand(0); 752 return true; 753 } 754 default: 755 return false; 756 } 757} 758 759SDValue SystemZDAGToDAGISel::getUNDEF64(SDLoc DL) { 760 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64); 761 return SDValue(N, 0); 762} 763 764SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) { 765 if (N.getValueType() == MVT::i32 && VT == MVT::i64) { 766 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64); 767 SDNode *Insert = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, 768 DL, VT, getUNDEF64(DL), N, Index); 769 return SDValue(Insert, 0); 770 } 771 if (N.getValueType() == MVT::i64 && VT == MVT::i32) { 772 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64); 773 SDNode *Extract = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 774 DL, VT, N, Index); 775 return SDValue(Extract, 0); 776 } 777 assert(N.getValueType() == VT && "Unexpected value types"); 778 return N; 779} 780 781SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { 782 RxSBGOperands RISBG(SDValue(N, 0)); 783 unsigned Count = 0; 784 while (expandRxSBG(RISBG)) 785 Count += 1; 786 // Prefer to use normal shift instructions over RISBG, since they can handle 787 // all cases and are sometimes shorter. Prefer to use RISBG for ANDs though, 788 // since it is effectively a three-operand instruction in this case, 789 // and since it can handle some masks that AND IMMEDIATE can't. 790 if (Count < (N->getOpcode() == ISD::AND ? 1U : 2U)) 791 return 0; 792 793 // Prefer register extensions like LLC over RISBG. 794 if (RISBG.Rotate == 0 && 795 (RISBG.Start == 32 || RISBG.Start == 48 || RISBG.Start == 56) && 796 RISBG.End == 63) 797 return 0; 798 799 EVT VT = N->getValueType(0); 800 SDValue Ops[5] = { 801 getUNDEF64(SDLoc(N)), 802 convertTo(SDLoc(N), MVT::i64, RISBG.Input), 803 CurDAG->getTargetConstant(RISBG.Start, MVT::i32), 804 CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32), 805 CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32) 806 }; 807 N = CurDAG->getMachineNode(SystemZ::RISBG, SDLoc(N), MVT::i64, Ops); 808 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode(); 809} 810 811SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) { 812 // Try treating each operand of N as the second operand of the RxSBG 813 // and see which goes deepest. 814 RxSBGOperands RxSBG[] = { N->getOperand(0), N->getOperand(1) }; 815 unsigned Count[] = { 0, 0 }; 816 for (unsigned I = 0; I < 2; ++I) 817 while (expandRxSBG(RxSBG[I])) 818 Count[I] += 1; 819 820 // Do nothing if neither operand is suitable. 821 if (Count[0] == 0 && Count[1] == 0) 822 return 0; 823 824 // Pick the deepest second operand. 825 unsigned I = Count[0] > Count[1] ? 0 : 1; 826 SDValue Op0 = N->getOperand(I ^ 1); 827 828 // Prefer IC for character insertions from memory. 829 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0) 830 if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode())) 831 if (Load->getMemoryVT() == MVT::i8) 832 return 0; 833 834 // See whether we can avoid an AND in the first operand by converting 835 // ROSBG to RISBG. 836 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) 837 Opcode = SystemZ::RISBG; 838 839 EVT VT = N->getValueType(0); 840 SDValue Ops[5] = { 841 convertTo(SDLoc(N), MVT::i64, Op0), 842 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input), 843 CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32), 844 CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32), 845 CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32) 846 }; 847 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops); 848 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode(); 849} 850 851SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node, 852 SDValue Op0, uint64_t UpperVal, 853 uint64_t LowerVal) { 854 EVT VT = Node->getValueType(0); 855 SDLoc DL(Node); 856 SDValue Upper = CurDAG->getConstant(UpperVal, VT); 857 if (Op0.getNode()) 858 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); 859 Upper = SDValue(Select(Upper.getNode()), 0); 860 861 SDValue Lower = CurDAG->getConstant(LowerVal, VT); 862 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); 863 return Or.getNode(); 864} 865 866// N is a (store (load ...), ...) pattern. Return true if it can use MVC. 867bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const { 868 StoreSDNode *Store = cast<StoreSDNode>(N); 869 LoadSDNode *Load = cast<LoadSDNode>(Store->getValue().getNode()); 870 871 // MVC is logically a bytewise copy, so can't be used for volatile accesses. 872 if (Load->isVolatile() || Store->isVolatile()) 873 return false; 874 875 // Prefer not to use MVC if either address can use ... RELATIVE LONG 876 // instructions. 877 assert(Load->getMemoryVT() == Store->getMemoryVT() && 878 "Should already have checked that the types match"); 879 uint64_t Size = Load->getMemoryVT().getStoreSize(); 880 if (Size > 1 && Size <= 8) { 881 // Prefer LHRL, LRL and LGRL. 882 if (Load->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER) 883 return false; 884 // Prefer STHRL, STRL and STGRL. 885 if (Store->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER) 886 return false; 887 } 888 889 // There's no chance of overlap if the load is invariant. 890 if (Load->isInvariant()) 891 return true; 892 893 // If both operands are aligned, they must be equal or not overlap. 894 if (Load->getAlignment() >= Size && Store->getAlignment() >= Size) 895 return true; 896 897 // Otherwise we need to check whether there's an alias. 898 const Value *V1 = Load->getSrcValue(); 899 const Value *V2 = Store->getSrcValue(); 900 if (!V1 || !V2) 901 return false; 902 903 int64_t End1 = Load->getSrcValueOffset() + Size; 904 int64_t End2 = Store->getSrcValueOffset() + Size; 905 return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()), 906 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo())); 907} 908 909SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { 910 // Dump information about the Node being selected 911 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 912 913 // If we have a custom node, we already have selected! 914 if (Node->isMachineOpcode()) { 915 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 916 return 0; 917 } 918 919 unsigned Opcode = Node->getOpcode(); 920 SDNode *ResNode = 0; 921 switch (Opcode) { 922 case ISD::OR: 923 if (Node->getOperand(1).getOpcode() != ISD::Constant) 924 ResNode = tryRxSBG(Node, SystemZ::ROSBG); 925 goto or_xor; 926 927 case ISD::XOR: 928 if (Node->getOperand(1).getOpcode() != ISD::Constant) 929 ResNode = tryRxSBG(Node, SystemZ::RXSBG); 930 // Fall through. 931 or_xor: 932 // If this is a 64-bit operation in which both 32-bit halves are nonzero, 933 // split the operation into two. 934 if (!ResNode && Node->getValueType(0) == MVT::i64) 935 if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) { 936 uint64_t Val = Op1->getZExtValue(); 937 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) 938 Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0), 939 Val - uint32_t(Val), uint32_t(Val)); 940 } 941 break; 942 943 case ISD::AND: 944 case ISD::ROTL: 945 case ISD::SHL: 946 case ISD::SRL: 947 if (!ResNode) 948 ResNode = tryRISBGZero(Node); 949 break; 950 951 case ISD::Constant: 952 // If this is a 64-bit constant that is out of the range of LLILF, 953 // LLIHF and LGFI, split it into two 32-bit pieces. 954 if (Node->getValueType(0) == MVT::i64) { 955 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue(); 956 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) 957 Node = splitLargeImmediate(ISD::OR, Node, SDValue(), 958 Val - uint32_t(Val), uint32_t(Val)); 959 } 960 break; 961 962 case ISD::ATOMIC_LOAD_SUB: 963 // Try to convert subtractions of constants to additions. 964 if (ConstantSDNode *Op2 = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 965 uint64_t Value = -Op2->getZExtValue(); 966 EVT VT = Node->getValueType(0); 967 if (VT == MVT::i32 || isInt<32>(Value)) { 968 SDValue Ops[] = { Node->getOperand(0), Node->getOperand(1), 969 CurDAG->getConstant(int32_t(Value), VT) }; 970 Node = CurDAG->MorphNodeTo(Node, ISD::ATOMIC_LOAD_ADD, 971 Node->getVTList(), Ops, array_lengthof(Ops)); 972 } 973 } 974 break; 975 } 976 977 // Select the default instruction 978 if (!ResNode) 979 ResNode = SelectCode(Node); 980 981 DEBUG(errs() << "=> "; 982 if (ResNode == NULL || ResNode == Node) 983 Node->dump(CurDAG); 984 else 985 ResNode->dump(CurDAG); 986 errs() << "\n"; 987 ); 988 return ResNode; 989} 990 991bool SystemZDAGToDAGISel:: 992SelectInlineAsmMemoryOperand(const SDValue &Op, 993 char ConstraintCode, 994 std::vector<SDValue> &OutOps) { 995 assert(ConstraintCode == 'm' && "Unexpected constraint code"); 996 // Accept addresses with short displacements, which are compatible 997 // with Q, R, S and T. But keep the index operand for future expansion. 998 SDValue Base, Disp, Index; 999 if (!selectBDXAddr(SystemZAddressingMode::FormBD, 1000 SystemZAddressingMode::Disp12Only, 1001 Op, Base, Disp, Index)) 1002 return true; 1003 OutOps.push_back(Base); 1004 OutOps.push_back(Disp); 1005 OutOps.push_back(Index); 1006 return false; 1007} 1008