SystemZISelLowering.cpp revision 0e31d5cf80b6efb6f7a9ca7778503c575a8038e9 
1//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation  -----==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SystemZTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "systemz-lower"
15
16#include "SystemZISelLowering.h"
17#include "SystemZ.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZSubtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/ADT/VectorExtras.h"
37using namespace llvm;
38
39SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40  TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
41
42  RegInfo = TM.getRegisterInfo();
43
44  // Set up the register classes.
45  addRegisterClass(MVT::i32,  SystemZ::GR32RegisterClass);
46  addRegisterClass(MVT::i64,  SystemZ::GR64RegisterClass);
47  addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48  addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
49  addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
50
51  if (!UseSoftFloat) {
52    addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
53    addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
54  }
55
56  // Compute derived properties from the register classes
57  computeRegisterProperties();
58
59  // Set shifts properties
60  setShiftAmountFlavor(Extend);
61  setShiftAmountType(MVT::i64);
62
63  // Provide all sorts of operation actions
64  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
65  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
66  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
67
68  setStackPointerRegisterToSaveRestore(SystemZ::R15D);
69  setSchedulingPreference(SchedulingForLatency);
70
71  setOperationAction(ISD::RET,              MVT::Other, Custom);
72
73  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
74  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
75  setOperationAction(ISD::BR_CC,            MVT::i32, Custom);
76  setOperationAction(ISD::BR_CC,            MVT::i64, Custom);
77  setOperationAction(ISD::GlobalAddress,    MVT::i64, Custom);
78  setOperationAction(ISD::JumpTable,        MVT::i64, Custom);
79  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
80
81  setOperationAction(ISD::SDIV,             MVT::i32, Expand);
82  setOperationAction(ISD::UDIV,             MVT::i32, Expand);
83  setOperationAction(ISD::SDIV,             MVT::i64, Expand);
84  setOperationAction(ISD::UDIV,             MVT::i64, Expand);
85  setOperationAction(ISD::SREM,             MVT::i32, Expand);
86  setOperationAction(ISD::UREM,             MVT::i32, Expand);
87  setOperationAction(ISD::SREM,             MVT::i64, Expand);
88  setOperationAction(ISD::UREM,             MVT::i64, Expand);
89
90  // FIXME: Can we lower these 2 efficiently?
91  setOperationAction(ISD::SETCC,            MVT::i32, Expand);
92  setOperationAction(ISD::SETCC,            MVT::i64, Expand);
93  setOperationAction(ISD::SELECT,           MVT::i32, Expand);
94  setOperationAction(ISD::SELECT,           MVT::i64, Expand);
95  setOperationAction(ISD::SELECT_CC,        MVT::i32, Custom);
96  setOperationAction(ISD::SELECT_CC,        MVT::i64, Custom);
97
98  // Funny enough: we don't have 64-bit signed versions of these stuff, but have
99  // unsigned.
100  setOperationAction(ISD::MULHS,            MVT::i64, Expand);
101  setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Expand);
102}
103
104SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
105  switch (Op.getOpcode()) {
106  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
107  case ISD::RET:              return LowerRET(Op, DAG);
108  case ISD::CALL:             return LowerCALL(Op, DAG);
109  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
110  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
111  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
112  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
113  default:
114    assert(0 && "unimplemented operand");
115    return SDValue();
116  }
117}
118
119//===----------------------------------------------------------------------===//
120//                      Calling Convention Implementation
121//===----------------------------------------------------------------------===//
122
123#include "SystemZGenCallingConv.inc"
124
125SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
126                                                     SelectionDAG &DAG) {
127  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
128  switch (CC) {
129  default:
130    assert(0 && "Unsupported calling convention");
131  case CallingConv::C:
132  case CallingConv::Fast:
133    return LowerCCCArguments(Op, DAG);
134  }
135}
136
137SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
138  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
139  unsigned CallingConv = TheCall->getCallingConv();
140  switch (CallingConv) {
141  default:
142    assert(0 && "Unsupported calling convention");
143  case CallingConv::Fast:
144  case CallingConv::C:
145    return LowerCCCCallTo(Op, DAG, CallingConv);
146  }
147}
148
149/// LowerCCCArguments - transform physical registers into virtual registers and
150/// generate load operations for arguments places on the stack.
151// FIXME: struct return stuff
152// FIXME: varargs
153SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
154                                                 SelectionDAG &DAG) {
155  MachineFunction &MF = DAG.getMachineFunction();
156  MachineFrameInfo *MFI = MF.getFrameInfo();
157  MachineRegisterInfo &RegInfo = MF.getRegInfo();
158  SDValue Root = Op.getOperand(0);
159  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
160  unsigned CC = MF.getFunction()->getCallingConv();
161  DebugLoc dl = Op.getDebugLoc();
162
163  // Assign locations to all of the incoming arguments.
164  SmallVector<CCValAssign, 16> ArgLocs;
165  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
166  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
167
168  assert(!isVarArg && "Varargs not supported yet");
169
170  SmallVector<SDValue, 16> ArgValues;
171  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
172    CCValAssign &VA = ArgLocs[i];
173    if (VA.isRegLoc()) {
174      // Arguments passed in registers
175      MVT RegVT = VA.getLocVT();
176      TargetRegisterClass *RC;
177      switch (RegVT.getSimpleVT()) {
178      default:
179        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
180             << RegVT.getSimpleVT()
181             << "\n";
182        abort();
183       case MVT::i64:
184        RC = SystemZ::GR64RegisterClass;
185        break;
186       case MVT::f32:
187        RC = SystemZ::FP32RegisterClass;
188        break;
189       case MVT::f64:
190        RC = SystemZ::FP64RegisterClass;
191        break;
192      }
193
194      unsigned VReg = RegInfo.createVirtualRegister(RC);
195      RegInfo.addLiveIn(VA.getLocReg(), VReg);
196      SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
197
198      // If this is an 8/16/32-bit value, it is really passed promoted to 64
199      // bits. Insert an assert[sz]ext to capture this, then truncate to the
200      // right size.
201      if (VA.getLocInfo() == CCValAssign::SExt)
202        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
203                               DAG.getValueType(VA.getValVT()));
204      else if (VA.getLocInfo() == CCValAssign::ZExt)
205        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
206                               DAG.getValueType(VA.getValVT()));
207
208      if (VA.getLocInfo() != CCValAssign::Full)
209        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
210
211      ArgValues.push_back(ArgValue);
212    } else {
213      // Sanity check
214      assert(VA.isMemLoc());
215
216      // Create the nodes corresponding to a load from this parameter slot.
217      // Create the frame index object for this incoming parameter...
218      int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
219                                      VA.getLocMemOffset());
220
221      // Create the SelectionDAG nodes corresponding to a load
222      //from this parameter
223      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
224      ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN,
225                                      PseudoSourceValue::getFixedStack(FI), 0));
226    }
227  }
228
229  ArgValues.push_back(Root);
230
231  // Return the new list of results.
232  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
233                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
234}
235
236/// LowerCCCCallTo - functions arguments are copied from virtual regs to
237/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
238/// TODO: sret.
239SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
240                                              unsigned CC) {
241  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
242  SDValue Chain  = TheCall->getChain();
243  SDValue Callee = TheCall->getCallee();
244  bool isVarArg  = TheCall->isVarArg();
245  DebugLoc dl = Op.getDebugLoc();
246  MachineFunction &MF = DAG.getMachineFunction();
247
248  // Offset to first argument stack slot.
249  const unsigned FirstArgOffset = 160;
250
251  // Analyze operands of the call, assigning locations to each operand.
252  SmallVector<CCValAssign, 16> ArgLocs;
253  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
254
255  CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
256
257  // Get a count of how many bytes are to be pushed on the stack.
258  unsigned NumBytes = CCInfo.getNextStackOffset();
259
260  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
261                                                      getPointerTy(), true));
262
263  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
264  SmallVector<SDValue, 12> MemOpChains;
265  SDValue StackPtr;
266
267  // Walk the register/memloc assignments, inserting copies/loads.
268  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
269    CCValAssign &VA = ArgLocs[i];
270
271    // Arguments start after the 5 first operands of ISD::CALL
272    SDValue Arg = TheCall->getArg(i);
273
274    // Promote the value if needed.
275    switch (VA.getLocInfo()) {
276      default: assert(0 && "Unknown loc info!");
277      case CCValAssign::Full: break;
278      case CCValAssign::SExt:
279        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
280        break;
281      case CCValAssign::ZExt:
282        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
283        break;
284      case CCValAssign::AExt:
285        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
286        break;
287    }
288
289    // Arguments that can be passed on register must be kept at RegsToPass
290    // vector
291    if (VA.isRegLoc()) {
292      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
293    } else {
294      assert(VA.isMemLoc());
295
296      if (StackPtr.getNode() == 0)
297        StackPtr =
298          DAG.getCopyFromReg(Chain, dl,
299                             (RegInfo->hasFP(MF) ?
300                              SystemZ::R11D : SystemZ::R15D),
301                             getPointerTy());
302
303      unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
304      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
305                                   StackPtr,
306                                   DAG.getIntPtrConstant(Offset));
307
308      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
309                                         PseudoSourceValue::getStack(), Offset));
310    }
311  }
312
313  // Transform all store nodes into one single node because all store nodes are
314  // independent of each other.
315  if (!MemOpChains.empty())
316    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
317                        &MemOpChains[0], MemOpChains.size());
318
319  // Build a sequence of copy-to-reg nodes chained together with token chain and
320  // flag operands which copy the outgoing args into registers.  The InFlag in
321  // necessary since all emited instructions must be stuck together.
322  SDValue InFlag;
323  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
324    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
325                             RegsToPass[i].second, InFlag);
326    InFlag = Chain.getValue(1);
327  }
328
329  // If the callee is a GlobalAddress node (quite common, every direct call is)
330  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
331  // Likewise ExternalSymbol -> TargetExternalSymbol.
332  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
333    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
334  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
335    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
336
337  // Returns a chain & a flag for retval copy to use.
338  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
339  SmallVector<SDValue, 8> Ops;
340  Ops.push_back(Chain);
341  Ops.push_back(Callee);
342
343  // Add argument registers to the end of the list so that they are
344  // known live into the call.
345  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
346    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
347                                  RegsToPass[i].second.getValueType()));
348
349  if (InFlag.getNode())
350    Ops.push_back(InFlag);
351
352  Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
353  InFlag = Chain.getValue(1);
354
355  // Create the CALLSEQ_END node.
356  Chain = DAG.getCALLSEQ_END(Chain,
357                             DAG.getConstant(NumBytes, getPointerTy(), true),
358                             DAG.getConstant(0, getPointerTy(), true),
359                             InFlag);
360  InFlag = Chain.getValue(1);
361
362  // Handle result values, copying them out of physregs into vregs that we
363  // return.
364  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
365                 Op.getResNo());
366}
367
368/// LowerCallResult - Lower the result values of an ISD::CALL into the
369/// appropriate copies out of appropriate physical registers.  This assumes that
370/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
371/// being lowered. Returns a SDNode with the same number of values as the
372/// ISD::CALL.
373SDNode*
374SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
375                                       CallSDNode *TheCall,
376                                       unsigned CallingConv,
377                                       SelectionDAG &DAG) {
378  bool isVarArg = TheCall->isVarArg();
379  DebugLoc dl = TheCall->getDebugLoc();
380
381  // Assign locations to each value returned by this call.
382  SmallVector<CCValAssign, 16> RVLocs;
383  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
384
385  CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
386  SmallVector<SDValue, 8> ResultVals;
387
388  // Copy all of the result registers out of their specified physreg.
389  for (unsigned i = 0; i != RVLocs.size(); ++i) {
390    CCValAssign &VA = RVLocs[i];
391
392    Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
393                               VA.getLocVT(), InFlag).getValue(1);
394    SDValue RetValue = Chain.getValue(0);
395    InFlag = Chain.getValue(2);
396
397    // If this is an 8/16/32-bit value, it is really passed promoted to 64
398    // bits. Insert an assert[sz]ext to capture this, then truncate to the
399    // right size.
400    if (VA.getLocInfo() == CCValAssign::SExt)
401      RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
402                             DAG.getValueType(VA.getValVT()));
403    else if (VA.getLocInfo() == CCValAssign::ZExt)
404      RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
405                             DAG.getValueType(VA.getValVT()));
406
407    if (VA.getLocInfo() != CCValAssign::Full)
408      RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
409
410    ResultVals.push_back(RetValue);
411  }
412
413  ResultVals.push_back(Chain);
414
415  // Merge everything together with a MERGE_VALUES node.
416  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
417                     &ResultVals[0], ResultVals.size()).getNode();
418}
419
420
421SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
422  // CCValAssign - represent the assignment of the return value to a location
423  SmallVector<CCValAssign, 16> RVLocs;
424  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
425  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
426  DebugLoc dl = Op.getDebugLoc();
427
428  // CCState - Info about the registers and stack slot.
429  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
430
431  // Analize return values of ISD::RET
432  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
433
434  // If this is the first return lowered for this function, add the regs to the
435  // liveout set for the function.
436  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
437    for (unsigned i = 0; i != RVLocs.size(); ++i)
438      if (RVLocs[i].isRegLoc())
439        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
440  }
441
442  // The chain is always operand #0
443  SDValue Chain = Op.getOperand(0);
444  SDValue Flag;
445
446  // Copy the result values into the output registers.
447  for (unsigned i = 0; i != RVLocs.size(); ++i) {
448    CCValAssign &VA = RVLocs[i];
449    SDValue ResValue = Op.getOperand(i*2+1);
450    assert(VA.isRegLoc() && "Can only return in registers!");
451
452    // If this is an 8/16/32-bit value, it is really should be passed promoted
453    // to 64 bits.
454    if (VA.getLocInfo() == CCValAssign::SExt)
455      ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
456    else if (VA.getLocInfo() == CCValAssign::ZExt)
457      ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
458    else if (VA.getLocInfo() == CCValAssign::AExt)
459      ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
460
461    // ISD::RET => ret chain, (regnum1,val1), ...
462    // So i*2+1 index only the regnums
463    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
464
465    // Guarantee that all emitted copies are stuck together,
466    // avoiding something bad.
467    Flag = Chain.getValue(1);
468  }
469
470  if (Flag.getNode())
471    return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
472
473  // Return Void
474  return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
475}
476
477SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
478                                       ISD::CondCode CC, SDValue &SystemZCC,
479                                       SelectionDAG &DAG) {
480  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
481
482  // FIXME: Emit a test if RHS is zero
483
484  bool isUnsigned = false;
485  SystemZCC::CondCodes TCC;
486  switch (CC) {
487  default: assert(0 && "Invalid integer condition!");
488  case ISD::SETEQ:
489    TCC = SystemZCC::E;
490    break;
491  case ISD::SETNE:
492    TCC = SystemZCC::NE;
493    break;
494  case ISD::SETULE:
495    isUnsigned = true;   // FALLTHROUGH
496  case ISD::SETLE:
497    TCC = SystemZCC::LE;
498    break;
499  case ISD::SETUGE:
500    isUnsigned = true;   // FALLTHROUGH
501  case ISD::SETGE:
502    TCC = SystemZCC::HE;
503    break;
504  case ISD::SETUGT:
505    isUnsigned = true;
506  case ISD::SETGT:
507    TCC = SystemZCC::H; // FALLTHROUGH
508    break;
509  case ISD::SETULT:
510    isUnsigned = true;
511  case ISD::SETLT:      // FALLTHROUGH
512    TCC = SystemZCC::L;
513    break;
514  }
515
516  SystemZCC = DAG.getConstant(TCC, MVT::i32);
517
518  DebugLoc dl = LHS.getDebugLoc();
519  return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
520                     dl, MVT::Flag, LHS, RHS);
521}
522
523
524SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
525  SDValue Chain = Op.getOperand(0);
526  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
527  SDValue LHS   = Op.getOperand(2);
528  SDValue RHS   = Op.getOperand(3);
529  SDValue Dest  = Op.getOperand(4);
530  DebugLoc dl   = Op.getDebugLoc();
531
532  SDValue SystemZCC;
533  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
534  return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
535                     Chain, Dest, SystemZCC, Flag);
536}
537
538SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
539  SDValue LHS    = Op.getOperand(0);
540  SDValue RHS    = Op.getOperand(1);
541  SDValue TrueV  = Op.getOperand(2);
542  SDValue FalseV = Op.getOperand(3);
543  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
544  DebugLoc dl   = Op.getDebugLoc();
545
546  SDValue SystemZCC;
547  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
548
549  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
550  SmallVector<SDValue, 4> Ops;
551  Ops.push_back(TrueV);
552  Ops.push_back(FalseV);
553  Ops.push_back(SystemZCC);
554  Ops.push_back(Flag);
555
556  return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
557}
558
559SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
560                                                  SelectionDAG &DAG) {
561  DebugLoc dl = Op.getDebugLoc();
562  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
563  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
564
565  bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
566  bool ExtraLoadRequired =
567    Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
568
569  SDValue Result;
570  if (!IsPic && !ExtraLoadRequired) {
571    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
572    Offset = 0;
573  } else {
574    unsigned char OpFlags = 0;
575    if (ExtraLoadRequired)
576      OpFlags = SystemZII::MO_GOTENT;
577
578    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
579  }
580
581  Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
582                       getPointerTy(), Result);
583
584  if (ExtraLoadRequired)
585    Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
586                         PseudoSourceValue::getGOT(), 0);
587
588  // If there was a non-zero offset that we didn't fold, create an explicit
589  // addition for it.
590  if (Offset != 0)
591    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
592                         DAG.getConstant(Offset, getPointerTy()));
593
594  return Result;
595}
596
597
598SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
599                                              SelectionDAG &DAG) {
600  DebugLoc dl = Op.getDebugLoc();
601  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
602  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
603
604  return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
605}
606
607const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
608  switch (Opcode) {
609  case SystemZISD::RET_FLAG:           return "SystemZISD::RET_FLAG";
610  case SystemZISD::CALL:               return "SystemZISD::CALL";
611  case SystemZISD::BRCOND:             return "SystemZISD::BRCOND";
612  case SystemZISD::CMP:                return "SystemZISD::CMP";
613  case SystemZISD::UCMP:               return "SystemZISD::UCMP";
614  case SystemZISD::SELECT:             return "SystemZISD::SELECT";
615  case SystemZISD::PCRelativeWrapper:  return "SystemZISD::PCRelativeWrapper";
616  default: return NULL;
617  }
618}
619
620//===----------------------------------------------------------------------===//
621//  Other Lowering Code
622//===----------------------------------------------------------------------===//
623
624MachineBasicBlock*
625SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
626                                                   MachineBasicBlock *BB) const {
627  const SystemZInstrInfo &TII = *TM.getInstrInfo();
628  DebugLoc dl = MI->getDebugLoc();
629  assert((MI->getOpcode() == SystemZ::Select32 ||
630          MI->getOpcode() == SystemZ::Select64) &&
631         "Unexpected instr type to insert");
632
633  // To "insert" a SELECT instruction, we actually have to insert the diamond
634  // control-flow pattern.  The incoming instruction knows the destination vreg
635  // to set, the condition code register to branch on, the true/false values to
636  // select between, and a branch opcode to use.
637  const BasicBlock *LLVM_BB = BB->getBasicBlock();
638  MachineFunction::iterator I = BB;
639  ++I;
640
641  //  thisMBB:
642  //  ...
643  //   TrueVal = ...
644  //   cmpTY ccX, r1, r2
645  //   jCC copy1MBB
646  //   fallthrough --> copy0MBB
647  MachineBasicBlock *thisMBB = BB;
648  MachineFunction *F = BB->getParent();
649  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
650  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
651  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
652  BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
653  F->insert(I, copy0MBB);
654  F->insert(I, copy1MBB);
655  // Update machine-CFG edges by transferring all successors of the current
656  // block to the new block which will contain the Phi node for the select.
657  copy1MBB->transferSuccessors(BB);
658  // Next, add the true and fallthrough blocks as its successors.
659  BB->addSuccessor(copy0MBB);
660  BB->addSuccessor(copy1MBB);
661
662  //  copy0MBB:
663  //   %FalseValue = ...
664  //   # fallthrough to copy1MBB
665  BB = copy0MBB;
666
667  // Update machine-CFG edges
668  BB->addSuccessor(copy1MBB);
669
670  //  copy1MBB:
671  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
672  //  ...
673  BB = copy1MBB;
674  BuildMI(BB, dl, TII.get(SystemZ::PHI),
675          MI->getOperand(0).getReg())
676    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
677    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
678
679  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
680  return BB;
681}
682