SystemZISelLowering.cpp revision 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 
1//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation  -----==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SystemZTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "systemz-lower"
15
16#include "SystemZISelLowering.h"
17#include "SystemZ.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZSubtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/VectorExtras.h"
40using namespace llvm;
41
42SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
43  TargetLowering(tm, new TargetLoweringObjectFileELF()),
44  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
45
46  RegInfo = TM.getRegisterInfo();
47
48  // Set up the register classes.
49  addRegisterClass(MVT::i32,  SystemZ::GR32RegisterClass);
50  addRegisterClass(MVT::i64,  SystemZ::GR64RegisterClass);
51  addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
52  addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
53
54  if (!UseSoftFloat) {
55    addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
56    addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
57  }
58
59  // Compute derived properties from the register classes
60  computeRegisterProperties();
61
62  // Set shifts properties
63  setShiftAmountType(MVT::i64);
64
65  // Provide all sorts of operation actions
66  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
69
70  setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
71  setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
72  setLoadExtAction(ISD::EXTLOAD,  MVT::f32, Expand);
73
74  setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
75  setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
76  setLoadExtAction(ISD::EXTLOAD,  MVT::f64, Expand);
77
78  setStackPointerRegisterToSaveRestore(SystemZ::R15D);
79
80  // TODO: It may be better to default to latency-oriented scheduling, however
81  // LLVM's current latency-oriented scheduler can't handle physreg definitions
82  // such as SystemZ has with PSW, so set this to the register-pressure
83  // scheduler, because it can.
84  setSchedulingPreference(Sched::RegPressure);
85
86  setBooleanContents(ZeroOrOneBooleanContent);
87
88  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
89  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
90  setOperationAction(ISD::BR_CC,            MVT::i32, Custom);
91  setOperationAction(ISD::BR_CC,            MVT::i64, Custom);
92  setOperationAction(ISD::BR_CC,            MVT::f32, Custom);
93  setOperationAction(ISD::BR_CC,            MVT::f64, Custom);
94  setOperationAction(ISD::ConstantPool,     MVT::i32, Custom);
95  setOperationAction(ISD::ConstantPool,     MVT::i64, Custom);
96  setOperationAction(ISD::GlobalAddress,    MVT::i64, Custom);
97  setOperationAction(ISD::JumpTable,        MVT::i64, Custom);
98  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
99
100  setOperationAction(ISD::SDIV,             MVT::i32, Expand);
101  setOperationAction(ISD::UDIV,             MVT::i32, Expand);
102  setOperationAction(ISD::SDIV,             MVT::i64, Expand);
103  setOperationAction(ISD::UDIV,             MVT::i64, Expand);
104  setOperationAction(ISD::SREM,             MVT::i32, Expand);
105  setOperationAction(ISD::UREM,             MVT::i32, Expand);
106  setOperationAction(ISD::SREM,             MVT::i64, Expand);
107  setOperationAction(ISD::UREM,             MVT::i64, Expand);
108
109  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
110
111  setOperationAction(ISD::CTPOP,            MVT::i32, Expand);
112  setOperationAction(ISD::CTPOP,            MVT::i64, Expand);
113  setOperationAction(ISD::CTTZ,             MVT::i32, Expand);
114  setOperationAction(ISD::CTTZ,             MVT::i64, Expand);
115  setOperationAction(ISD::CTLZ,             MVT::i32, Promote);
116  setOperationAction(ISD::CTLZ,             MVT::i64, Legal);
117
118  // FIXME: Can we lower these 2 efficiently?
119  setOperationAction(ISD::SETCC,            MVT::i32, Expand);
120  setOperationAction(ISD::SETCC,            MVT::i64, Expand);
121  setOperationAction(ISD::SETCC,            MVT::f32, Expand);
122  setOperationAction(ISD::SETCC,            MVT::f64, Expand);
123  setOperationAction(ISD::SELECT,           MVT::i32, Expand);
124  setOperationAction(ISD::SELECT,           MVT::i64, Expand);
125  setOperationAction(ISD::SELECT,           MVT::f32, Expand);
126  setOperationAction(ISD::SELECT,           MVT::f64, Expand);
127  setOperationAction(ISD::SELECT_CC,        MVT::i32, Custom);
128  setOperationAction(ISD::SELECT_CC,        MVT::i64, Custom);
129  setOperationAction(ISD::SELECT_CC,        MVT::f32, Custom);
130  setOperationAction(ISD::SELECT_CC,        MVT::f64, Custom);
131
132  setOperationAction(ISD::MULHS,            MVT::i64, Expand);
133  setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Expand);
134
135  // FIXME: Can we support these natively?
136  setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i64, Expand);
138  setOperationAction(ISD::SHL_PARTS,        MVT::i64, Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i64, Expand);
140
141  // Lower some FP stuff
142  setOperationAction(ISD::FSIN,             MVT::f32, Expand);
143  setOperationAction(ISD::FSIN,             MVT::f64, Expand);
144  setOperationAction(ISD::FCOS,             MVT::f32, Expand);
145  setOperationAction(ISD::FCOS,             MVT::f64, Expand);
146  setOperationAction(ISD::FREM,             MVT::f32, Expand);
147  setOperationAction(ISD::FREM,             MVT::f64, Expand);
148
149  // We have only 64-bit bitconverts
150  setOperationAction(ISD::BIT_CONVERT,      MVT::f32, Expand);
151  setOperationAction(ISD::BIT_CONVERT,      MVT::i32, Expand);
152
153  setOperationAction(ISD::UINT_TO_FP,       MVT::i32, Expand);
154  setOperationAction(ISD::UINT_TO_FP,       MVT::i64, Expand);
155  setOperationAction(ISD::FP_TO_UINT,       MVT::i32, Expand);
156  setOperationAction(ISD::FP_TO_UINT,       MVT::i64, Expand);
157
158  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
159}
160
161SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
162                                              SelectionDAG &DAG) const {
163  switch (Op.getOpcode()) {
164  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
165  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
166  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
167  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
168  case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
169  default:
170    llvm_unreachable("Should not custom lower this!");
171    return SDValue();
172  }
173}
174
175bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
176  if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64))
177    return false;
178
179  // +0.0  lzer
180  // +0.0f lzdr
181  // -0.0  lzer + lner
182  // -0.0f lzdr + lndr
183  return Imm.isZero() || Imm.isNegZero();
184}
185
186//===----------------------------------------------------------------------===//
187//                       SystemZ Inline Assembly Support
188//===----------------------------------------------------------------------===//
189
190/// getConstraintType - Given a constraint letter, return the type of
191/// constraint it is for this target.
192TargetLowering::ConstraintType
193SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
194  if (Constraint.size() == 1) {
195    switch (Constraint[0]) {
196    case 'r':
197      return C_RegisterClass;
198    default:
199      break;
200    }
201  }
202  return TargetLowering::getConstraintType(Constraint);
203}
204
205std::pair<unsigned, const TargetRegisterClass*>
206SystemZTargetLowering::
207getRegForInlineAsmConstraint(const std::string &Constraint,
208                             EVT VT) const {
209  if (Constraint.size() == 1) {
210    // GCC Constraint Letters
211    switch (Constraint[0]) {
212    default: break;
213    case 'r':   // GENERAL_REGS
214      if (VT == MVT::i32)
215        return std::make_pair(0U, SystemZ::GR32RegisterClass);
216      else if (VT == MVT::i128)
217        return std::make_pair(0U, SystemZ::GR128RegisterClass);
218
219      return std::make_pair(0U, SystemZ::GR64RegisterClass);
220    }
221  }
222
223  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
224}
225
226//===----------------------------------------------------------------------===//
227//                      Calling Convention Implementation
228//===----------------------------------------------------------------------===//
229
230#include "SystemZGenCallingConv.inc"
231
232SDValue
233SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
234                                            CallingConv::ID CallConv,
235                                            bool isVarArg,
236                                            const SmallVectorImpl<ISD::InputArg>
237                                              &Ins,
238                                            DebugLoc dl,
239                                            SelectionDAG &DAG,
240                                            SmallVectorImpl<SDValue> &InVals)
241                                              const {
242
243  switch (CallConv) {
244  default:
245    llvm_unreachable("Unsupported calling convention");
246  case CallingConv::C:
247  case CallingConv::Fast:
248    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
249  }
250}
251
252SDValue
253SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
254                                 CallingConv::ID CallConv, bool isVarArg,
255                                 bool &isTailCall,
256                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
257                                 const SmallVectorImpl<ISD::InputArg> &Ins,
258                                 DebugLoc dl, SelectionDAG &DAG,
259                                 SmallVectorImpl<SDValue> &InVals) const {
260  // SystemZ target does not yet support tail call optimization.
261  isTailCall = false;
262
263  switch (CallConv) {
264  default:
265    llvm_unreachable("Unsupported calling convention");
266  case CallingConv::Fast:
267  case CallingConv::C:
268    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
269                          Outs, Ins, dl, DAG, InVals);
270  }
271}
272
273/// LowerCCCArguments - transform physical registers into virtual registers and
274/// generate load operations for arguments places on the stack.
275// FIXME: struct return stuff
276// FIXME: varargs
277SDValue
278SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
279                                         CallingConv::ID CallConv,
280                                         bool isVarArg,
281                                         const SmallVectorImpl<ISD::InputArg>
282                                           &Ins,
283                                         DebugLoc dl,
284                                         SelectionDAG &DAG,
285                                         SmallVectorImpl<SDValue> &InVals)
286                                           const {
287
288  MachineFunction &MF = DAG.getMachineFunction();
289  MachineFrameInfo *MFI = MF.getFrameInfo();
290  MachineRegisterInfo &RegInfo = MF.getRegInfo();
291
292  // Assign locations to all of the incoming arguments.
293  SmallVector<CCValAssign, 16> ArgLocs;
294  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
295                 ArgLocs, *DAG.getContext());
296  CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
297
298  if (isVarArg)
299    report_fatal_error("Varargs not supported yet");
300
301  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
302    SDValue ArgValue;
303    CCValAssign &VA = ArgLocs[i];
304    EVT LocVT = VA.getLocVT();
305    if (VA.isRegLoc()) {
306      // Arguments passed in registers
307      TargetRegisterClass *RC;
308      switch (LocVT.getSimpleVT().SimpleTy) {
309      default:
310#ifndef NDEBUG
311        errs() << "LowerFormalArguments Unhandled argument type: "
312             << LocVT.getSimpleVT().SimpleTy
313             << "\n";
314#endif
315        llvm_unreachable(0);
316      case MVT::i64:
317        RC = SystemZ::GR64RegisterClass;
318        break;
319      case MVT::f32:
320        RC = SystemZ::FP32RegisterClass;
321        break;
322      case MVT::f64:
323        RC = SystemZ::FP64RegisterClass;
324        break;
325      }
326
327      unsigned VReg = RegInfo.createVirtualRegister(RC);
328      RegInfo.addLiveIn(VA.getLocReg(), VReg);
329      ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
330    } else {
331      // Sanity check
332      assert(VA.isMemLoc());
333
334      // Create the nodes corresponding to a load from this parameter slot.
335      // Create the frame index object for this incoming parameter...
336      int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
337                                      VA.getLocMemOffset(), true);
338
339      // Create the SelectionDAG nodes corresponding to a load
340      // from this parameter
341      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
342      ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
343                             PseudoSourceValue::getFixedStack(FI), 0,
344                             false, false, 0);
345    }
346
347    // If this is an 8/16/32-bit value, it is really passed promoted to 64
348    // bits. Insert an assert[sz]ext to capture this, then truncate to the
349    // right size.
350    if (VA.getLocInfo() == CCValAssign::SExt)
351      ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
352                             DAG.getValueType(VA.getValVT()));
353    else if (VA.getLocInfo() == CCValAssign::ZExt)
354      ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
355                             DAG.getValueType(VA.getValVT()));
356
357    if (VA.getLocInfo() != CCValAssign::Full)
358      ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
359
360    InVals.push_back(ArgValue);
361  }
362
363  return Chain;
364}
365
366/// LowerCCCCallTo - functions arguments are copied from virtual regs to
367/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
368/// TODO: sret.
369SDValue
370SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
371                                      CallingConv::ID CallConv, bool isVarArg,
372                                      bool isTailCall,
373                                      const SmallVectorImpl<ISD::OutputArg>
374                                        &Outs,
375                                      const SmallVectorImpl<ISD::InputArg> &Ins,
376                                      DebugLoc dl, SelectionDAG &DAG,
377                                      SmallVectorImpl<SDValue> &InVals) const {
378
379  MachineFunction &MF = DAG.getMachineFunction();
380
381  // Offset to first argument stack slot.
382  const unsigned FirstArgOffset = 160;
383
384  // Analyze operands of the call, assigning locations to each operand.
385  SmallVector<CCValAssign, 16> ArgLocs;
386  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
387                 ArgLocs, *DAG.getContext());
388
389  CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
390
391  // Get a count of how many bytes are to be pushed on the stack.
392  unsigned NumBytes = CCInfo.getNextStackOffset();
393
394  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
395                                                      getPointerTy(), true));
396
397  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
398  SmallVector<SDValue, 12> MemOpChains;
399  SDValue StackPtr;
400
401  // Walk the register/memloc assignments, inserting copies/loads.
402  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
403    CCValAssign &VA = ArgLocs[i];
404
405    SDValue Arg = Outs[i].Val;
406
407    // Promote the value if needed.
408    switch (VA.getLocInfo()) {
409      default: assert(0 && "Unknown loc info!");
410      case CCValAssign::Full: break;
411      case CCValAssign::SExt:
412        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
413        break;
414      case CCValAssign::ZExt:
415        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
416        break;
417      case CCValAssign::AExt:
418        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
419        break;
420    }
421
422    // Arguments that can be passed on register must be kept at RegsToPass
423    // vector
424    if (VA.isRegLoc()) {
425      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
426    } else {
427      assert(VA.isMemLoc());
428
429      if (StackPtr.getNode() == 0)
430        StackPtr =
431          DAG.getCopyFromReg(Chain, dl,
432                             (RegInfo->hasFP(MF) ?
433                              SystemZ::R11D : SystemZ::R15D),
434                             getPointerTy());
435
436      unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
437      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
438                                   StackPtr,
439                                   DAG.getIntPtrConstant(Offset));
440
441      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
442                                         PseudoSourceValue::getStack(), Offset,
443                                         false, false, 0));
444    }
445  }
446
447  // Transform all store nodes into one single node because all store nodes are
448  // independent of each other.
449  if (!MemOpChains.empty())
450    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
451                        &MemOpChains[0], MemOpChains.size());
452
453  // Build a sequence of copy-to-reg nodes chained together with token chain and
454  // flag operands which copy the outgoing args into registers.  The InFlag in
455  // necessary since all emited instructions must be stuck together.
456  SDValue InFlag;
457  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
458    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
459                             RegsToPass[i].second, InFlag);
460    InFlag = Chain.getValue(1);
461  }
462
463  // If the callee is a GlobalAddress node (quite common, every direct call is)
464  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
465  // Likewise ExternalSymbol -> TargetExternalSymbol.
466  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
467    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
468  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
469    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
470
471  // Returns a chain & a flag for retval copy to use.
472  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
473  SmallVector<SDValue, 8> Ops;
474  Ops.push_back(Chain);
475  Ops.push_back(Callee);
476
477  // Add argument registers to the end of the list so that they are
478  // known live into the call.
479  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
480    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
481                                  RegsToPass[i].second.getValueType()));
482
483  if (InFlag.getNode())
484    Ops.push_back(InFlag);
485
486  Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
487  InFlag = Chain.getValue(1);
488
489  // Create the CALLSEQ_END node.
490  Chain = DAG.getCALLSEQ_END(Chain,
491                             DAG.getConstant(NumBytes, getPointerTy(), true),
492                             DAG.getConstant(0, getPointerTy(), true),
493                             InFlag);
494  InFlag = Chain.getValue(1);
495
496  // Handle result values, copying them out of physregs into vregs that we
497  // return.
498  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
499                         DAG, InVals);
500}
501
502/// LowerCallResult - Lower the result values of a call into the
503/// appropriate copies out of appropriate physical registers.
504///
505SDValue
506SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
507                                       CallingConv::ID CallConv, bool isVarArg,
508                                       const SmallVectorImpl<ISD::InputArg>
509                                         &Ins,
510                                       DebugLoc dl, SelectionDAG &DAG,
511                                       SmallVectorImpl<SDValue> &InVals) const {
512
513  // Assign locations to each value returned by this call.
514  SmallVector<CCValAssign, 16> RVLocs;
515  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
516                 *DAG.getContext());
517
518  CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
519
520  // Copy all of the result registers out of their specified physreg.
521  for (unsigned i = 0; i != RVLocs.size(); ++i) {
522    CCValAssign &VA = RVLocs[i];
523
524    Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
525                               VA.getLocVT(), InFlag).getValue(1);
526    SDValue RetValue = Chain.getValue(0);
527    InFlag = Chain.getValue(2);
528
529    // If this is an 8/16/32-bit value, it is really passed promoted to 64
530    // bits. Insert an assert[sz]ext to capture this, then truncate to the
531    // right size.
532    if (VA.getLocInfo() == CCValAssign::SExt)
533      RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
534                             DAG.getValueType(VA.getValVT()));
535    else if (VA.getLocInfo() == CCValAssign::ZExt)
536      RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
537                             DAG.getValueType(VA.getValVT()));
538
539    if (VA.getLocInfo() != CCValAssign::Full)
540      RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
541
542    InVals.push_back(RetValue);
543  }
544
545  return Chain;
546}
547
548
549SDValue
550SystemZTargetLowering::LowerReturn(SDValue Chain,
551                                   CallingConv::ID CallConv, bool isVarArg,
552                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
553                                   DebugLoc dl, SelectionDAG &DAG) const {
554
555  // CCValAssign - represent the assignment of the return value to a location
556  SmallVector<CCValAssign, 16> RVLocs;
557
558  // CCState - Info about the registers and stack slot.
559  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
560                 RVLocs, *DAG.getContext());
561
562  // Analize return values.
563  CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
564
565  // If this is the first return lowered for this function, add the regs to the
566  // liveout set for the function.
567  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
568    for (unsigned i = 0; i != RVLocs.size(); ++i)
569      if (RVLocs[i].isRegLoc())
570        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
571  }
572
573  SDValue Flag;
574
575  // Copy the result values into the output registers.
576  for (unsigned i = 0; i != RVLocs.size(); ++i) {
577    CCValAssign &VA = RVLocs[i];
578    SDValue ResValue = Outs[i].Val;
579    assert(VA.isRegLoc() && "Can only return in registers!");
580
581    // If this is an 8/16/32-bit value, it is really should be passed promoted
582    // to 64 bits.
583    if (VA.getLocInfo() == CCValAssign::SExt)
584      ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
585    else if (VA.getLocInfo() == CCValAssign::ZExt)
586      ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
587    else if (VA.getLocInfo() == CCValAssign::AExt)
588      ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
589
590    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
591
592    // Guarantee that all emitted copies are stuck together,
593    // avoiding something bad.
594    Flag = Chain.getValue(1);
595  }
596
597  if (Flag.getNode())
598    return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
599
600  // Return Void
601  return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
602}
603
604SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
605                                       ISD::CondCode CC, SDValue &SystemZCC,
606                                       SelectionDAG &DAG) const {
607  // FIXME: Emit a test if RHS is zero
608
609  bool isUnsigned = false;
610  SystemZCC::CondCodes TCC;
611  switch (CC) {
612  default:
613    llvm_unreachable("Invalid integer condition!");
614  case ISD::SETEQ:
615  case ISD::SETOEQ:
616    TCC = SystemZCC::E;
617    break;
618  case ISD::SETUEQ:
619    TCC = SystemZCC::NLH;
620    break;
621  case ISD::SETNE:
622  case ISD::SETONE:
623    TCC = SystemZCC::NE;
624    break;
625  case ISD::SETUNE:
626    TCC = SystemZCC::LH;
627    break;
628  case ISD::SETO:
629    TCC = SystemZCC::O;
630    break;
631  case ISD::SETUO:
632    TCC = SystemZCC::NO;
633    break;
634  case ISD::SETULE:
635    if (LHS.getValueType().isFloatingPoint()) {
636      TCC = SystemZCC::NH;
637      break;
638    }
639    isUnsigned = true;   // FALLTHROUGH
640  case ISD::SETLE:
641  case ISD::SETOLE:
642    TCC = SystemZCC::LE;
643    break;
644  case ISD::SETUGE:
645    if (LHS.getValueType().isFloatingPoint()) {
646      TCC = SystemZCC::NL;
647      break;
648    }
649    isUnsigned = true;   // FALLTHROUGH
650  case ISD::SETGE:
651  case ISD::SETOGE:
652    TCC = SystemZCC::HE;
653    break;
654  case ISD::SETUGT:
655    if (LHS.getValueType().isFloatingPoint()) {
656      TCC = SystemZCC::NLE;
657      break;
658    }
659    isUnsigned = true;  // FALLTHROUGH
660  case ISD::SETGT:
661  case ISD::SETOGT:
662    TCC = SystemZCC::H;
663    break;
664  case ISD::SETULT:
665    if (LHS.getValueType().isFloatingPoint()) {
666      TCC = SystemZCC::NHE;
667      break;
668    }
669    isUnsigned = true;  // FALLTHROUGH
670  case ISD::SETLT:
671  case ISD::SETOLT:
672    TCC = SystemZCC::L;
673    break;
674  }
675
676  SystemZCC = DAG.getConstant(TCC, MVT::i32);
677
678  DebugLoc dl = LHS.getDebugLoc();
679  return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
680                     dl, MVT::i64, LHS, RHS);
681}
682
683
684SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
685  SDValue Chain = Op.getOperand(0);
686  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
687  SDValue LHS   = Op.getOperand(2);
688  SDValue RHS   = Op.getOperand(3);
689  SDValue Dest  = Op.getOperand(4);
690  DebugLoc dl   = Op.getDebugLoc();
691
692  SDValue SystemZCC;
693  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
694  return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
695                     Chain, Dest, SystemZCC, Flag);
696}
697
698SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op,
699                                              SelectionDAG &DAG) const {
700  SDValue LHS    = Op.getOperand(0);
701  SDValue RHS    = Op.getOperand(1);
702  SDValue TrueV  = Op.getOperand(2);
703  SDValue FalseV = Op.getOperand(3);
704  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
705  DebugLoc dl   = Op.getDebugLoc();
706
707  SDValue SystemZCC;
708  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
709
710  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
711  SmallVector<SDValue, 4> Ops;
712  Ops.push_back(TrueV);
713  Ops.push_back(FalseV);
714  Ops.push_back(SystemZCC);
715  Ops.push_back(Flag);
716
717  return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
718}
719
720SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
721                                                  SelectionDAG &DAG) const {
722  DebugLoc dl = Op.getDebugLoc();
723  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
724  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
725
726  bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
727  bool ExtraLoadRequired =
728    Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
729
730  SDValue Result;
731  if (!IsPic && !ExtraLoadRequired) {
732    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
733    Offset = 0;
734  } else {
735    unsigned char OpFlags = 0;
736    if (ExtraLoadRequired)
737      OpFlags = SystemZII::MO_GOTENT;
738
739    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
740  }
741
742  Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
743                       getPointerTy(), Result);
744
745  if (ExtraLoadRequired)
746    Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
747                         PseudoSourceValue::getGOT(), 0, false, false, 0);
748
749  // If there was a non-zero offset that we didn't fold, create an explicit
750  // addition for it.
751  if (Offset != 0)
752    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
753                         DAG.getConstant(Offset, getPointerTy()));
754
755  return Result;
756}
757
758// FIXME: PIC here
759SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
760                                              SelectionDAG &DAG) const {
761  DebugLoc dl = Op.getDebugLoc();
762  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
763  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
764
765  return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
766}
767
768
769// FIXME: PIC here
770// FIXME: This is just dirty hack. We need to lower cpool properly
771SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
772                                                 SelectionDAG &DAG) const {
773  DebugLoc dl = Op.getDebugLoc();
774  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
775
776  SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
777                                             CP->getAlignment(),
778                                             CP->getOffset());
779
780  return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
781}
782
783const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
784  switch (Opcode) {
785  case SystemZISD::RET_FLAG:           return "SystemZISD::RET_FLAG";
786  case SystemZISD::CALL:               return "SystemZISD::CALL";
787  case SystemZISD::BRCOND:             return "SystemZISD::BRCOND";
788  case SystemZISD::CMP:                return "SystemZISD::CMP";
789  case SystemZISD::UCMP:               return "SystemZISD::UCMP";
790  case SystemZISD::SELECT:             return "SystemZISD::SELECT";
791  case SystemZISD::PCRelativeWrapper:  return "SystemZISD::PCRelativeWrapper";
792  default: return NULL;
793  }
794}
795
796//===----------------------------------------------------------------------===//
797//  Other Lowering Code
798//===----------------------------------------------------------------------===//
799
800MachineBasicBlock*
801SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
802                                                   MachineBasicBlock *BB) const {
803  const SystemZInstrInfo &TII = *TM.getInstrInfo();
804  DebugLoc dl = MI->getDebugLoc();
805  assert((MI->getOpcode() == SystemZ::Select32  ||
806          MI->getOpcode() == SystemZ::SelectF32 ||
807          MI->getOpcode() == SystemZ::Select64  ||
808          MI->getOpcode() == SystemZ::SelectF64) &&
809         "Unexpected instr type to insert");
810
811  // To "insert" a SELECT instruction, we actually have to insert the diamond
812  // control-flow pattern.  The incoming instruction knows the destination vreg
813  // to set, the condition code register to branch on, the true/false values to
814  // select between, and a branch opcode to use.
815  const BasicBlock *LLVM_BB = BB->getBasicBlock();
816  MachineFunction::iterator I = BB;
817  ++I;
818
819  //  thisMBB:
820  //  ...
821  //   TrueVal = ...
822  //   cmpTY ccX, r1, r2
823  //   jCC copy1MBB
824  //   fallthrough --> copy0MBB
825  MachineBasicBlock *thisMBB = BB;
826  MachineFunction *F = BB->getParent();
827  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
828  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
829  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
830  BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
831  F->insert(I, copy0MBB);
832  F->insert(I, copy1MBB);
833  // Update machine-CFG edges by transferring all successors of the current
834  // block to the new block which will contain the Phi node for the select.
835  copy1MBB->transferSuccessors(BB);
836  // Next, add the true and fallthrough blocks as its successors.
837  BB->addSuccessor(copy0MBB);
838  BB->addSuccessor(copy1MBB);
839
840  //  copy0MBB:
841  //   %FalseValue = ...
842  //   # fallthrough to copy1MBB
843  BB = copy0MBB;
844
845  // Update machine-CFG edges
846  BB->addSuccessor(copy1MBB);
847
848  //  copy1MBB:
849  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
850  //  ...
851  BB = copy1MBB;
852  BuildMI(BB, dl, TII.get(SystemZ::PHI),
853          MI->getOperand(0).getReg())
854    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
855    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
856
857  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
858  return BB;
859}
860