SystemZISelLowering.cpp revision 2c97ae8826371dc5b4dc119d7576443ebd39b7b2 
1//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation  -----==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SystemZTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "systemz-lower"
15
16#include "SystemZISelLowering.h"
17#include "SystemZ.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZSubtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/ADT/VectorExtras.h"
37using namespace llvm;
38
39SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40  TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
41
42  RegInfo = TM.getRegisterInfo();
43
44  // Set up the register classes.
45  addRegisterClass(MVT::i32,  SystemZ::GR32RegisterClass);
46  addRegisterClass(MVT::i64,  SystemZ::GR64RegisterClass);
47  addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48  addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
49  addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
50
51  if (!UseSoftFloat) {
52    addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
53    addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
54  }
55
56  // Compute derived properties from the register classes
57  computeRegisterProperties();
58
59  // Set shifts properties
60  setShiftAmountFlavor(Extend);
61  setShiftAmountType(MVT::i64);
62
63  // Provide all sorts of operation actions
64  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
65  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
66  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
67
68  setStackPointerRegisterToSaveRestore(SystemZ::R15D);
69  setSchedulingPreference(SchedulingForLatency);
70
71  setOperationAction(ISD::RET,              MVT::Other, Custom);
72
73  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
74  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
75  setOperationAction(ISD::BR_CC,            MVT::i32, Custom);
76  setOperationAction(ISD::BR_CC,            MVT::i64, Custom);
77  setOperationAction(ISD::GlobalAddress,    MVT::i64, Custom);
78  setOperationAction(ISD::JumpTable,        MVT::i64, Custom);
79  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
80
81  setOperationAction(ISD::SDIV,             MVT::i32, Expand);
82  setOperationAction(ISD::UDIV,             MVT::i32, Expand);
83  setOperationAction(ISD::SDIV,             MVT::i64, Expand);
84  setOperationAction(ISD::UDIV,             MVT::i64, Expand);
85  setOperationAction(ISD::SREM,             MVT::i32, Expand);
86  setOperationAction(ISD::UREM,             MVT::i32, Expand);
87  setOperationAction(ISD::SREM,             MVT::i64, Expand);
88  setOperationAction(ISD::UREM,             MVT::i64, Expand);
89
90  // FIXME: Can we lower these 2 efficiently?
91  setOperationAction(ISD::SETCC,            MVT::i32, Expand);
92  setOperationAction(ISD::SETCC,            MVT::i64, Expand);
93  setOperationAction(ISD::SELECT,           MVT::i32, Expand);
94  setOperationAction(ISD::SELECT,           MVT::i64, Expand);
95  setOperationAction(ISD::SELECT_CC,        MVT::i32, Custom);
96  setOperationAction(ISD::SELECT_CC,        MVT::i64, Custom);
97
98  // Funny enough: we don't have 64-bit signed versions of these stuff, but have
99  // unsigned.
100  setOperationAction(ISD::MULHS,            MVT::i64, Expand);
101  setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Expand);
102}
103
104SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
105  switch (Op.getOpcode()) {
106  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
107  case ISD::RET:              return LowerRET(Op, DAG);
108  case ISD::CALL:             return LowerCALL(Op, DAG);
109  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
110  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
111  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
112  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
113  default:
114    assert(0 && "unimplemented operand");
115    return SDValue();
116  }
117}
118
119//===----------------------------------------------------------------------===//
120//                      Calling Convention Implementation
121//===----------------------------------------------------------------------===//
122
123#include "SystemZGenCallingConv.inc"
124
125SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
126                                                     SelectionDAG &DAG) {
127  unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
128  switch (CC) {
129  default:
130    assert(0 && "Unsupported calling convention");
131  case CallingConv::C:
132  case CallingConv::Fast:
133    return LowerCCCArguments(Op, DAG);
134  }
135}
136
137SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
138  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
139  unsigned CallingConv = TheCall->getCallingConv();
140  switch (CallingConv) {
141  default:
142    assert(0 && "Unsupported calling convention");
143  case CallingConv::Fast:
144  case CallingConv::C:
145    return LowerCCCCallTo(Op, DAG, CallingConv);
146  }
147}
148
149/// LowerCCCArguments - transform physical registers into virtual registers and
150/// generate load operations for arguments places on the stack.
151// FIXME: struct return stuff
152// FIXME: varargs
153SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
154                                                 SelectionDAG &DAG) {
155  MachineFunction &MF = DAG.getMachineFunction();
156  MachineFrameInfo *MFI = MF.getFrameInfo();
157  MachineRegisterInfo &RegInfo = MF.getRegInfo();
158  SDValue Root = Op.getOperand(0);
159  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
160  unsigned CC = MF.getFunction()->getCallingConv();
161  DebugLoc dl = Op.getDebugLoc();
162
163  // Assign locations to all of the incoming arguments.
164  SmallVector<CCValAssign, 16> ArgLocs;
165  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
166  CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
167
168  assert(!isVarArg && "Varargs not supported yet");
169
170  SmallVector<SDValue, 16> ArgValues;
171  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
172    CCValAssign &VA = ArgLocs[i];
173    if (VA.isRegLoc()) {
174      // Arguments passed in registers
175      MVT RegVT = VA.getLocVT();
176      switch (RegVT.getSimpleVT()) {
177      default:
178        cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
179             << RegVT.getSimpleVT()
180             << "\n";
181        abort();
182      case MVT::i64:
183        unsigned VReg =
184          RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
185        RegInfo.addLiveIn(VA.getLocReg(), VReg);
186        SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
187
188        // If this is an 8/16/32-bit value, it is really passed promoted to 64
189        // bits. Insert an assert[sz]ext to capture this, then truncate to the
190        // right size.
191        if (VA.getLocInfo() == CCValAssign::SExt)
192          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
193                                 DAG.getValueType(VA.getValVT()));
194        else if (VA.getLocInfo() == CCValAssign::ZExt)
195          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
196                                 DAG.getValueType(VA.getValVT()));
197
198        if (VA.getLocInfo() != CCValAssign::Full)
199          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
200
201        ArgValues.push_back(ArgValue);
202      }
203    } else {
204      // Sanity check
205      assert(VA.isMemLoc());
206
207      // Create the nodes corresponding to a load from this parameter slot.
208      // Create the frame index object for this incoming parameter...
209      int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
210                                      VA.getLocMemOffset());
211
212      // Create the SelectionDAG nodes corresponding to a load
213      //from this parameter
214      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
215      ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN,
216                                      PseudoSourceValue::getFixedStack(FI), 0));
217    }
218  }
219
220  ArgValues.push_back(Root);
221
222  // Return the new list of results.
223  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
224                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
225}
226
227/// LowerCCCCallTo - functions arguments are copied from virtual regs to
228/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
229/// TODO: sret.
230SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
231                                              unsigned CC) {
232  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
233  SDValue Chain  = TheCall->getChain();
234  SDValue Callee = TheCall->getCallee();
235  bool isVarArg  = TheCall->isVarArg();
236  DebugLoc dl = Op.getDebugLoc();
237  MachineFunction &MF = DAG.getMachineFunction();
238
239  // Offset to first argument stack slot.
240  const unsigned FirstArgOffset = 160;
241
242  // Analyze operands of the call, assigning locations to each operand.
243  SmallVector<CCValAssign, 16> ArgLocs;
244  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
245
246  CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
247
248  // Get a count of how many bytes are to be pushed on the stack.
249  unsigned NumBytes = CCInfo.getNextStackOffset();
250
251  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
252                                                      getPointerTy(), true));
253
254  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
255  SmallVector<SDValue, 12> MemOpChains;
256  SDValue StackPtr;
257
258  // Walk the register/memloc assignments, inserting copies/loads.
259  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
260    CCValAssign &VA = ArgLocs[i];
261
262    // Arguments start after the 5 first operands of ISD::CALL
263    SDValue Arg = TheCall->getArg(i);
264
265    // Promote the value if needed.
266    switch (VA.getLocInfo()) {
267      default: assert(0 && "Unknown loc info!");
268      case CCValAssign::Full: break;
269      case CCValAssign::SExt:
270        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
271        break;
272      case CCValAssign::ZExt:
273        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
274        break;
275      case CCValAssign::AExt:
276        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
277        break;
278    }
279
280    // Arguments that can be passed on register must be kept at RegsToPass
281    // vector
282    if (VA.isRegLoc()) {
283      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
284    } else {
285      assert(VA.isMemLoc());
286
287      if (StackPtr.getNode() == 0)
288        StackPtr =
289          DAG.getCopyFromReg(Chain, dl,
290                             (RegInfo->hasFP(MF) ?
291                              SystemZ::R11D : SystemZ::R15D),
292                             getPointerTy());
293
294      unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
295      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
296                                   StackPtr,
297                                   DAG.getIntPtrConstant(Offset));
298
299      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
300                                         PseudoSourceValue::getStack(), Offset));
301    }
302  }
303
304  // Transform all store nodes into one single node because all store nodes are
305  // independent of each other.
306  if (!MemOpChains.empty())
307    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
308                        &MemOpChains[0], MemOpChains.size());
309
310  // Build a sequence of copy-to-reg nodes chained together with token chain and
311  // flag operands which copy the outgoing args into registers.  The InFlag in
312  // necessary since all emited instructions must be stuck together.
313  SDValue InFlag;
314  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
315    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
316                             RegsToPass[i].second, InFlag);
317    InFlag = Chain.getValue(1);
318  }
319
320  // If the callee is a GlobalAddress node (quite common, every direct call is)
321  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
322  // Likewise ExternalSymbol -> TargetExternalSymbol.
323  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
324    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
325  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
326    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
327
328  // Returns a chain & a flag for retval copy to use.
329  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
330  SmallVector<SDValue, 8> Ops;
331  Ops.push_back(Chain);
332  Ops.push_back(Callee);
333
334  // Add argument registers to the end of the list so that they are
335  // known live into the call.
336  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
337    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
338                                  RegsToPass[i].second.getValueType()));
339
340  if (InFlag.getNode())
341    Ops.push_back(InFlag);
342
343  Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
344  InFlag = Chain.getValue(1);
345
346  // Create the CALLSEQ_END node.
347  Chain = DAG.getCALLSEQ_END(Chain,
348                             DAG.getConstant(NumBytes, getPointerTy(), true),
349                             DAG.getConstant(0, getPointerTy(), true),
350                             InFlag);
351  InFlag = Chain.getValue(1);
352
353  // Handle result values, copying them out of physregs into vregs that we
354  // return.
355  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
356                 Op.getResNo());
357}
358
359/// LowerCallResult - Lower the result values of an ISD::CALL into the
360/// appropriate copies out of appropriate physical registers.  This assumes that
361/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
362/// being lowered. Returns a SDNode with the same number of values as the
363/// ISD::CALL.
364SDNode*
365SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
366                                       CallSDNode *TheCall,
367                                       unsigned CallingConv,
368                                       SelectionDAG &DAG) {
369  bool isVarArg = TheCall->isVarArg();
370  DebugLoc dl = TheCall->getDebugLoc();
371
372  // Assign locations to each value returned by this call.
373  SmallVector<CCValAssign, 16> RVLocs;
374  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
375
376  CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
377  SmallVector<SDValue, 8> ResultVals;
378
379  // Copy all of the result registers out of their specified physreg.
380  for (unsigned i = 0; i != RVLocs.size(); ++i) {
381    CCValAssign &VA = RVLocs[i];
382
383    Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
384                               VA.getLocVT(), InFlag).getValue(1);
385    SDValue RetValue = Chain.getValue(0);
386    InFlag = Chain.getValue(2);
387
388    // If this is an 8/16/32-bit value, it is really passed promoted to 64
389    // bits. Insert an assert[sz]ext to capture this, then truncate to the
390    // right size.
391    if (VA.getLocInfo() == CCValAssign::SExt)
392      RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
393                             DAG.getValueType(VA.getValVT()));
394    else if (VA.getLocInfo() == CCValAssign::ZExt)
395      RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
396                             DAG.getValueType(VA.getValVT()));
397
398    if (VA.getLocInfo() != CCValAssign::Full)
399      RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
400
401    ResultVals.push_back(RetValue);
402  }
403
404  ResultVals.push_back(Chain);
405
406  // Merge everything together with a MERGE_VALUES node.
407  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
408                     &ResultVals[0], ResultVals.size()).getNode();
409}
410
411
412SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
413  // CCValAssign - represent the assignment of the return value to a location
414  SmallVector<CCValAssign, 16> RVLocs;
415  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
416  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
417  DebugLoc dl = Op.getDebugLoc();
418
419  // CCState - Info about the registers and stack slot.
420  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
421
422  // Analize return values of ISD::RET
423  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
424
425  // If this is the first return lowered for this function, add the regs to the
426  // liveout set for the function.
427  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
428    for (unsigned i = 0; i != RVLocs.size(); ++i)
429      if (RVLocs[i].isRegLoc())
430        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
431  }
432
433  // The chain is always operand #0
434  SDValue Chain = Op.getOperand(0);
435  SDValue Flag;
436
437  // Copy the result values into the output registers.
438  for (unsigned i = 0; i != RVLocs.size(); ++i) {
439    CCValAssign &VA = RVLocs[i];
440    SDValue ResValue = Op.getOperand(i*2+1);
441    assert(VA.isRegLoc() && "Can only return in registers!");
442
443    // If this is an 8/16/32-bit value, it is really should be passed promoted
444    // to 64 bits.
445    if (VA.getLocInfo() == CCValAssign::SExt)
446      ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
447    else if (VA.getLocInfo() == CCValAssign::ZExt)
448      ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
449    else if (VA.getLocInfo() == CCValAssign::AExt)
450      ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
451
452    // ISD::RET => ret chain, (regnum1,val1), ...
453    // So i*2+1 index only the regnums
454    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
455
456    // Guarantee that all emitted copies are stuck together,
457    // avoiding something bad.
458    Flag = Chain.getValue(1);
459  }
460
461  if (Flag.getNode())
462    return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
463
464  // Return Void
465  return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
466}
467
468SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
469                                       ISD::CondCode CC, SDValue &SystemZCC,
470                                       SelectionDAG &DAG) {
471  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
472
473  // FIXME: Emit a test if RHS is zero
474
475  bool isUnsigned = false;
476  SystemZCC::CondCodes TCC;
477  switch (CC) {
478  default: assert(0 && "Invalid integer condition!");
479  case ISD::SETEQ:
480    TCC = SystemZCC::E;
481    break;
482  case ISD::SETNE:
483    TCC = SystemZCC::NE;
484    break;
485  case ISD::SETULE:
486    isUnsigned = true;   // FALLTHROUGH
487  case ISD::SETLE:
488    TCC = SystemZCC::LE;
489    break;
490  case ISD::SETUGE:
491    isUnsigned = true;   // FALLTHROUGH
492  case ISD::SETGE:
493    TCC = SystemZCC::HE;
494    break;
495  case ISD::SETUGT:
496    isUnsigned = true;
497  case ISD::SETGT:
498    TCC = SystemZCC::H; // FALLTHROUGH
499    break;
500  case ISD::SETULT:
501    isUnsigned = true;
502  case ISD::SETLT:      // FALLTHROUGH
503    TCC = SystemZCC::L;
504    break;
505  }
506
507  SystemZCC = DAG.getConstant(TCC, MVT::i32);
508
509  DebugLoc dl = LHS.getDebugLoc();
510  return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
511                     dl, MVT::Flag, LHS, RHS);
512}
513
514
515SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
516  SDValue Chain = Op.getOperand(0);
517  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
518  SDValue LHS   = Op.getOperand(2);
519  SDValue RHS   = Op.getOperand(3);
520  SDValue Dest  = Op.getOperand(4);
521  DebugLoc dl   = Op.getDebugLoc();
522
523  SDValue SystemZCC;
524  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
525  return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
526                     Chain, Dest, SystemZCC, Flag);
527}
528
529SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
530  SDValue LHS    = Op.getOperand(0);
531  SDValue RHS    = Op.getOperand(1);
532  SDValue TrueV  = Op.getOperand(2);
533  SDValue FalseV = Op.getOperand(3);
534  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
535  DebugLoc dl   = Op.getDebugLoc();
536
537  SDValue SystemZCC;
538  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
539
540  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
541  SmallVector<SDValue, 4> Ops;
542  Ops.push_back(TrueV);
543  Ops.push_back(FalseV);
544  Ops.push_back(SystemZCC);
545  Ops.push_back(Flag);
546
547  return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
548}
549
550SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
551                                                  SelectionDAG &DAG) {
552  DebugLoc dl = Op.getDebugLoc();
553  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
554  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
555
556  bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
557  bool ExtraLoadRequired =
558    Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
559
560  SDValue Result;
561  if (!IsPic && !ExtraLoadRequired) {
562    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
563    Offset = 0;
564  } else {
565    unsigned char OpFlags = 0;
566    if (ExtraLoadRequired)
567      OpFlags = SystemZII::MO_GOTENT;
568
569    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
570  }
571
572  Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
573                       getPointerTy(), Result);
574
575  if (ExtraLoadRequired)
576    Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
577                         PseudoSourceValue::getGOT(), 0);
578
579  // If there was a non-zero offset that we didn't fold, create an explicit
580  // addition for it.
581  if (Offset != 0)
582    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
583                         DAG.getConstant(Offset, getPointerTy()));
584
585  return Result;
586}
587
588
589SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
590                                              SelectionDAG &DAG) {
591  DebugLoc dl = Op.getDebugLoc();
592  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
593  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
594
595  return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
596}
597
598const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
599  switch (Opcode) {
600  case SystemZISD::RET_FLAG:           return "SystemZISD::RET_FLAG";
601  case SystemZISD::CALL:               return "SystemZISD::CALL";
602  case SystemZISD::BRCOND:             return "SystemZISD::BRCOND";
603  case SystemZISD::CMP:                return "SystemZISD::CMP";
604  case SystemZISD::UCMP:               return "SystemZISD::UCMP";
605  case SystemZISD::SELECT:             return "SystemZISD::SELECT";
606  case SystemZISD::PCRelativeWrapper:  return "SystemZISD::PCRelativeWrapper";
607  default: return NULL;
608  }
609}
610
611//===----------------------------------------------------------------------===//
612//  Other Lowering Code
613//===----------------------------------------------------------------------===//
614
615MachineBasicBlock*
616SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
617                                                   MachineBasicBlock *BB) const {
618  const SystemZInstrInfo &TII = *TM.getInstrInfo();
619  DebugLoc dl = MI->getDebugLoc();
620  assert((MI->getOpcode() == SystemZ::Select32 ||
621          MI->getOpcode() == SystemZ::Select64) &&
622         "Unexpected instr type to insert");
623
624  // To "insert" a SELECT instruction, we actually have to insert the diamond
625  // control-flow pattern.  The incoming instruction knows the destination vreg
626  // to set, the condition code register to branch on, the true/false values to
627  // select between, and a branch opcode to use.
628  const BasicBlock *LLVM_BB = BB->getBasicBlock();
629  MachineFunction::iterator I = BB;
630  ++I;
631
632  //  thisMBB:
633  //  ...
634  //   TrueVal = ...
635  //   cmpTY ccX, r1, r2
636  //   jCC copy1MBB
637  //   fallthrough --> copy0MBB
638  MachineBasicBlock *thisMBB = BB;
639  MachineFunction *F = BB->getParent();
640  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
641  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
642  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
643  BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
644  F->insert(I, copy0MBB);
645  F->insert(I, copy1MBB);
646  // Update machine-CFG edges by transferring all successors of the current
647  // block to the new block which will contain the Phi node for the select.
648  copy1MBB->transferSuccessors(BB);
649  // Next, add the true and fallthrough blocks as its successors.
650  BB->addSuccessor(copy0MBB);
651  BB->addSuccessor(copy1MBB);
652
653  //  copy0MBB:
654  //   %FalseValue = ...
655  //   # fallthrough to copy1MBB
656  BB = copy0MBB;
657
658  // Update machine-CFG edges
659  BB->addSuccessor(copy1MBB);
660
661  //  copy1MBB:
662  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
663  //  ...
664  BB = copy1MBB;
665  BuildMI(BB, dl, TII.get(SystemZ::PHI),
666          MI->getOperand(0).getReg())
667    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
668    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
669
670  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
671  return BB;
672}
673