SystemZISelLowering.cpp revision 46510a73e977273ec67747eb34cbdb43f815e451 
1//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation  -----==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SystemZTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "systemz-lower"
15
16#include "SystemZISelLowering.h"
17#include "SystemZ.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZSubtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Target/TargetOptions.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/VectorExtras.h"
40using namespace llvm;
41
42SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
43  TargetLowering(tm, new TargetLoweringObjectFileELF()),
44  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
45
46  RegInfo = TM.getRegisterInfo();
47
48  // Set up the register classes.
49  addRegisterClass(MVT::i32,  SystemZ::GR32RegisterClass);
50  addRegisterClass(MVT::i64,  SystemZ::GR64RegisterClass);
51  addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
52  addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
53
54  if (!UseSoftFloat) {
55    addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
56    addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
57  }
58
59  // Compute derived properties from the register classes
60  computeRegisterProperties();
61
62  // Set shifts properties
63  setShiftAmountType(MVT::i64);
64
65  // Provide all sorts of operation actions
66  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
69
70  setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
71  setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
72  setLoadExtAction(ISD::EXTLOAD,  MVT::f32, Expand);
73
74  setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
75  setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
76  setLoadExtAction(ISD::EXTLOAD,  MVT::f64, Expand);
77
78  setStackPointerRegisterToSaveRestore(SystemZ::R15D);
79
80  // TODO: It may be better to default to latency-oriented scheduling, however
81  // LLVM's current latency-oriented scheduler can't handle physreg definitions
82  // such as SystemZ has with PSW, so set this to the register-pressure
83  // scheduler, because it can.
84  setSchedulingPreference(SchedulingForRegPressure);
85
86  setBooleanContents(ZeroOrOneBooleanContent);
87
88  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
89  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
90  setOperationAction(ISD::BR_CC,            MVT::i32, Custom);
91  setOperationAction(ISD::BR_CC,            MVT::i64, Custom);
92  setOperationAction(ISD::BR_CC,            MVT::f32, Custom);
93  setOperationAction(ISD::BR_CC,            MVT::f64, Custom);
94  setOperationAction(ISD::ConstantPool,     MVT::i32, Custom);
95  setOperationAction(ISD::ConstantPool,     MVT::i64, Custom);
96  setOperationAction(ISD::GlobalAddress,    MVT::i64, Custom);
97  setOperationAction(ISD::JumpTable,        MVT::i64, Custom);
98  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
99
100  setOperationAction(ISD::SDIV,             MVT::i32, Expand);
101  setOperationAction(ISD::UDIV,             MVT::i32, Expand);
102  setOperationAction(ISD::SDIV,             MVT::i64, Expand);
103  setOperationAction(ISD::UDIV,             MVT::i64, Expand);
104  setOperationAction(ISD::SREM,             MVT::i32, Expand);
105  setOperationAction(ISD::UREM,             MVT::i32, Expand);
106  setOperationAction(ISD::SREM,             MVT::i64, Expand);
107  setOperationAction(ISD::UREM,             MVT::i64, Expand);
108
109  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
110
111  setOperationAction(ISD::CTPOP,            MVT::i32, Expand);
112  setOperationAction(ISD::CTPOP,            MVT::i64, Expand);
113  setOperationAction(ISD::CTTZ,             MVT::i32, Expand);
114  setOperationAction(ISD::CTTZ,             MVT::i64, Expand);
115  setOperationAction(ISD::CTLZ,             MVT::i32, Promote);
116  setOperationAction(ISD::CTLZ,             MVT::i64, Legal);
117
118  // FIXME: Can we lower these 2 efficiently?
119  setOperationAction(ISD::SETCC,            MVT::i32, Expand);
120  setOperationAction(ISD::SETCC,            MVT::i64, Expand);
121  setOperationAction(ISD::SETCC,            MVT::f32, Expand);
122  setOperationAction(ISD::SETCC,            MVT::f64, Expand);
123  setOperationAction(ISD::SELECT,           MVT::i32, Expand);
124  setOperationAction(ISD::SELECT,           MVT::i64, Expand);
125  setOperationAction(ISD::SELECT,           MVT::f32, Expand);
126  setOperationAction(ISD::SELECT,           MVT::f64, Expand);
127  setOperationAction(ISD::SELECT_CC,        MVT::i32, Custom);
128  setOperationAction(ISD::SELECT_CC,        MVT::i64, Custom);
129  setOperationAction(ISD::SELECT_CC,        MVT::f32, Custom);
130  setOperationAction(ISD::SELECT_CC,        MVT::f64, Custom);
131
132  setOperationAction(ISD::MULHS,            MVT::i64, Expand);
133  setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Expand);
134
135  // FIXME: Can we support these natively?
136  setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i64, Expand);
138  setOperationAction(ISD::SHL_PARTS,        MVT::i64, Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i64, Expand);
140
141  // Lower some FP stuff
142  setOperationAction(ISD::FSIN,             MVT::f32, Expand);
143  setOperationAction(ISD::FSIN,             MVT::f64, Expand);
144  setOperationAction(ISD::FCOS,             MVT::f32, Expand);
145  setOperationAction(ISD::FCOS,             MVT::f64, Expand);
146  setOperationAction(ISD::FREM,             MVT::f32, Expand);
147  setOperationAction(ISD::FREM,             MVT::f64, Expand);
148
149  // We have only 64-bit bitconverts
150  setOperationAction(ISD::BIT_CONVERT,      MVT::f32, Expand);
151  setOperationAction(ISD::BIT_CONVERT,      MVT::i32, Expand);
152
153  setOperationAction(ISD::UINT_TO_FP,       MVT::i32, Expand);
154  setOperationAction(ISD::UINT_TO_FP,       MVT::i64, Expand);
155  setOperationAction(ISD::FP_TO_UINT,       MVT::i32, Expand);
156  setOperationAction(ISD::FP_TO_UINT,       MVT::i64, Expand);
157
158  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
159}
160
161SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
162  switch (Op.getOpcode()) {
163  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
164  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
165  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
166  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
167  case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
168  default:
169    llvm_unreachable("Should not custom lower this!");
170    return SDValue();
171  }
172}
173
174bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
175  if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64))
176    return false;
177
178  // +0.0  lzer
179  // +0.0f lzdr
180  // -0.0  lzer + lner
181  // -0.0f lzdr + lndr
182  return Imm.isZero() || Imm.isNegZero();
183}
184
185//===----------------------------------------------------------------------===//
186//                       SystemZ Inline Assembly Support
187//===----------------------------------------------------------------------===//
188
189/// getConstraintType - Given a constraint letter, return the type of
190/// constraint it is for this target.
191TargetLowering::ConstraintType
192SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
193  if (Constraint.size() == 1) {
194    switch (Constraint[0]) {
195    case 'r':
196      return C_RegisterClass;
197    default:
198      break;
199    }
200  }
201  return TargetLowering::getConstraintType(Constraint);
202}
203
204std::pair<unsigned, const TargetRegisterClass*>
205SystemZTargetLowering::
206getRegForInlineAsmConstraint(const std::string &Constraint,
207                             EVT VT) const {
208  if (Constraint.size() == 1) {
209    // GCC Constraint Letters
210    switch (Constraint[0]) {
211    default: break;
212    case 'r':   // GENERAL_REGS
213      if (VT == MVT::i32)
214        return std::make_pair(0U, SystemZ::GR32RegisterClass);
215      else if (VT == MVT::i128)
216        return std::make_pair(0U, SystemZ::GR128RegisterClass);
217
218      return std::make_pair(0U, SystemZ::GR64RegisterClass);
219    }
220  }
221
222  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
223}
224
225//===----------------------------------------------------------------------===//
226//                      Calling Convention Implementation
227//===----------------------------------------------------------------------===//
228
229#include "SystemZGenCallingConv.inc"
230
231SDValue
232SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
233                                            CallingConv::ID CallConv,
234                                            bool isVarArg,
235                                            const SmallVectorImpl<ISD::InputArg>
236                                              &Ins,
237                                            DebugLoc dl,
238                                            SelectionDAG &DAG,
239                                            SmallVectorImpl<SDValue> &InVals) {
240
241  switch (CallConv) {
242  default:
243    llvm_unreachable("Unsupported calling convention");
244  case CallingConv::C:
245  case CallingConv::Fast:
246    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
247  }
248}
249
250SDValue
251SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
252                                 CallingConv::ID CallConv, bool isVarArg,
253                                 bool &isTailCall,
254                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
255                                 const SmallVectorImpl<ISD::InputArg> &Ins,
256                                 DebugLoc dl, SelectionDAG &DAG,
257                                 SmallVectorImpl<SDValue> &InVals) {
258  // SystemZ target does not yet support tail call optimization.
259  isTailCall = false;
260
261  switch (CallConv) {
262  default:
263    llvm_unreachable("Unsupported calling convention");
264  case CallingConv::Fast:
265  case CallingConv::C:
266    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
267                          Outs, Ins, dl, DAG, InVals);
268  }
269}
270
271/// LowerCCCArguments - transform physical registers into virtual registers and
272/// generate load operations for arguments places on the stack.
273// FIXME: struct return stuff
274// FIXME: varargs
275SDValue
276SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
277                                         CallingConv::ID CallConv,
278                                         bool isVarArg,
279                                         const SmallVectorImpl<ISD::InputArg>
280                                           &Ins,
281                                         DebugLoc dl,
282                                         SelectionDAG &DAG,
283                                         SmallVectorImpl<SDValue> &InVals) {
284
285  MachineFunction &MF = DAG.getMachineFunction();
286  MachineFrameInfo *MFI = MF.getFrameInfo();
287  MachineRegisterInfo &RegInfo = MF.getRegInfo();
288
289  // Assign locations to all of the incoming arguments.
290  SmallVector<CCValAssign, 16> ArgLocs;
291  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
292                 ArgLocs, *DAG.getContext());
293  CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
294
295  if (isVarArg)
296    report_fatal_error("Varargs not supported yet");
297
298  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
299    SDValue ArgValue;
300    CCValAssign &VA = ArgLocs[i];
301    EVT LocVT = VA.getLocVT();
302    if (VA.isRegLoc()) {
303      // Arguments passed in registers
304      TargetRegisterClass *RC;
305      switch (LocVT.getSimpleVT().SimpleTy) {
306      default:
307#ifndef NDEBUG
308        errs() << "LowerFormalArguments Unhandled argument type: "
309             << LocVT.getSimpleVT().SimpleTy
310             << "\n";
311#endif
312        llvm_unreachable(0);
313      case MVT::i64:
314        RC = SystemZ::GR64RegisterClass;
315        break;
316      case MVT::f32:
317        RC = SystemZ::FP32RegisterClass;
318        break;
319      case MVT::f64:
320        RC = SystemZ::FP64RegisterClass;
321        break;
322      }
323
324      unsigned VReg = RegInfo.createVirtualRegister(RC);
325      RegInfo.addLiveIn(VA.getLocReg(), VReg);
326      ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
327    } else {
328      // Sanity check
329      assert(VA.isMemLoc());
330
331      // Create the nodes corresponding to a load from this parameter slot.
332      // Create the frame index object for this incoming parameter...
333      int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
334                                      VA.getLocMemOffset(), true, false);
335
336      // Create the SelectionDAG nodes corresponding to a load
337      // from this parameter
338      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
339      ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
340                             PseudoSourceValue::getFixedStack(FI), 0,
341                             false, false, 0);
342    }
343
344    // If this is an 8/16/32-bit value, it is really passed promoted to 64
345    // bits. Insert an assert[sz]ext to capture this, then truncate to the
346    // right size.
347    if (VA.getLocInfo() == CCValAssign::SExt)
348      ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
349                             DAG.getValueType(VA.getValVT()));
350    else if (VA.getLocInfo() == CCValAssign::ZExt)
351      ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
352                             DAG.getValueType(VA.getValVT()));
353
354    if (VA.getLocInfo() != CCValAssign::Full)
355      ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
356
357    InVals.push_back(ArgValue);
358  }
359
360  return Chain;
361}
362
363/// LowerCCCCallTo - functions arguments are copied from virtual regs to
364/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
365/// TODO: sret.
366SDValue
367SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
368                                      CallingConv::ID CallConv, bool isVarArg,
369                                      bool isTailCall,
370                                      const SmallVectorImpl<ISD::OutputArg>
371                                        &Outs,
372                                      const SmallVectorImpl<ISD::InputArg> &Ins,
373                                      DebugLoc dl, SelectionDAG &DAG,
374                                      SmallVectorImpl<SDValue> &InVals) {
375
376  MachineFunction &MF = DAG.getMachineFunction();
377
378  // Offset to first argument stack slot.
379  const unsigned FirstArgOffset = 160;
380
381  // Analyze operands of the call, assigning locations to each operand.
382  SmallVector<CCValAssign, 16> ArgLocs;
383  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
384                 ArgLocs, *DAG.getContext());
385
386  CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
387
388  // Get a count of how many bytes are to be pushed on the stack.
389  unsigned NumBytes = CCInfo.getNextStackOffset();
390
391  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
392                                                      getPointerTy(), true));
393
394  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
395  SmallVector<SDValue, 12> MemOpChains;
396  SDValue StackPtr;
397
398  // Walk the register/memloc assignments, inserting copies/loads.
399  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
400    CCValAssign &VA = ArgLocs[i];
401
402    SDValue Arg = Outs[i].Val;
403
404    // Promote the value if needed.
405    switch (VA.getLocInfo()) {
406      default: assert(0 && "Unknown loc info!");
407      case CCValAssign::Full: break;
408      case CCValAssign::SExt:
409        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
410        break;
411      case CCValAssign::ZExt:
412        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
413        break;
414      case CCValAssign::AExt:
415        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
416        break;
417    }
418
419    // Arguments that can be passed on register must be kept at RegsToPass
420    // vector
421    if (VA.isRegLoc()) {
422      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
423    } else {
424      assert(VA.isMemLoc());
425
426      if (StackPtr.getNode() == 0)
427        StackPtr =
428          DAG.getCopyFromReg(Chain, dl,
429                             (RegInfo->hasFP(MF) ?
430                              SystemZ::R11D : SystemZ::R15D),
431                             getPointerTy());
432
433      unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
434      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
435                                   StackPtr,
436                                   DAG.getIntPtrConstant(Offset));
437
438      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
439                                         PseudoSourceValue::getStack(), Offset,
440                                         false, false, 0));
441    }
442  }
443
444  // Transform all store nodes into one single node because all store nodes are
445  // independent of each other.
446  if (!MemOpChains.empty())
447    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
448                        &MemOpChains[0], MemOpChains.size());
449
450  // Build a sequence of copy-to-reg nodes chained together with token chain and
451  // flag operands which copy the outgoing args into registers.  The InFlag in
452  // necessary since all emited instructions must be stuck together.
453  SDValue InFlag;
454  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
455    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
456                             RegsToPass[i].second, InFlag);
457    InFlag = Chain.getValue(1);
458  }
459
460  // If the callee is a GlobalAddress node (quite common, every direct call is)
461  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
462  // Likewise ExternalSymbol -> TargetExternalSymbol.
463  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
464    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
465  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
466    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
467
468  // Returns a chain & a flag for retval copy to use.
469  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
470  SmallVector<SDValue, 8> Ops;
471  Ops.push_back(Chain);
472  Ops.push_back(Callee);
473
474  // Add argument registers to the end of the list so that they are
475  // known live into the call.
476  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
477    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
478                                  RegsToPass[i].second.getValueType()));
479
480  if (InFlag.getNode())
481    Ops.push_back(InFlag);
482
483  Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
484  InFlag = Chain.getValue(1);
485
486  // Create the CALLSEQ_END node.
487  Chain = DAG.getCALLSEQ_END(Chain,
488                             DAG.getConstant(NumBytes, getPointerTy(), true),
489                             DAG.getConstant(0, getPointerTy(), true),
490                             InFlag);
491  InFlag = Chain.getValue(1);
492
493  // Handle result values, copying them out of physregs into vregs that we
494  // return.
495  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
496                         DAG, InVals);
497}
498
499/// LowerCallResult - Lower the result values of a call into the
500/// appropriate copies out of appropriate physical registers.
501///
502SDValue
503SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
504                                       CallingConv::ID CallConv, bool isVarArg,
505                                       const SmallVectorImpl<ISD::InputArg>
506                                         &Ins,
507                                       DebugLoc dl, SelectionDAG &DAG,
508                                       SmallVectorImpl<SDValue> &InVals) {
509
510  // Assign locations to each value returned by this call.
511  SmallVector<CCValAssign, 16> RVLocs;
512  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
513                 *DAG.getContext());
514
515  CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
516
517  // Copy all of the result registers out of their specified physreg.
518  for (unsigned i = 0; i != RVLocs.size(); ++i) {
519    CCValAssign &VA = RVLocs[i];
520
521    Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
522                               VA.getLocVT(), InFlag).getValue(1);
523    SDValue RetValue = Chain.getValue(0);
524    InFlag = Chain.getValue(2);
525
526    // If this is an 8/16/32-bit value, it is really passed promoted to 64
527    // bits. Insert an assert[sz]ext to capture this, then truncate to the
528    // right size.
529    if (VA.getLocInfo() == CCValAssign::SExt)
530      RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
531                             DAG.getValueType(VA.getValVT()));
532    else if (VA.getLocInfo() == CCValAssign::ZExt)
533      RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
534                             DAG.getValueType(VA.getValVT()));
535
536    if (VA.getLocInfo() != CCValAssign::Full)
537      RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
538
539    InVals.push_back(RetValue);
540  }
541
542  return Chain;
543}
544
545
546SDValue
547SystemZTargetLowering::LowerReturn(SDValue Chain,
548                                   CallingConv::ID CallConv, bool isVarArg,
549                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
550                                   DebugLoc dl, SelectionDAG &DAG) {
551
552  // CCValAssign - represent the assignment of the return value to a location
553  SmallVector<CCValAssign, 16> RVLocs;
554
555  // CCState - Info about the registers and stack slot.
556  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
557                 RVLocs, *DAG.getContext());
558
559  // Analize return values.
560  CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
561
562  // If this is the first return lowered for this function, add the regs to the
563  // liveout set for the function.
564  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
565    for (unsigned i = 0; i != RVLocs.size(); ++i)
566      if (RVLocs[i].isRegLoc())
567        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
568  }
569
570  SDValue Flag;
571
572  // Copy the result values into the output registers.
573  for (unsigned i = 0; i != RVLocs.size(); ++i) {
574    CCValAssign &VA = RVLocs[i];
575    SDValue ResValue = Outs[i].Val;
576    assert(VA.isRegLoc() && "Can only return in registers!");
577
578    // If this is an 8/16/32-bit value, it is really should be passed promoted
579    // to 64 bits.
580    if (VA.getLocInfo() == CCValAssign::SExt)
581      ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
582    else if (VA.getLocInfo() == CCValAssign::ZExt)
583      ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
584    else if (VA.getLocInfo() == CCValAssign::AExt)
585      ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
586
587    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
588
589    // Guarantee that all emitted copies are stuck together,
590    // avoiding something bad.
591    Flag = Chain.getValue(1);
592  }
593
594  if (Flag.getNode())
595    return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
596
597  // Return Void
598  return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
599}
600
601SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
602                                       ISD::CondCode CC, SDValue &SystemZCC,
603                                       SelectionDAG &DAG) {
604  // FIXME: Emit a test if RHS is zero
605
606  bool isUnsigned = false;
607  SystemZCC::CondCodes TCC;
608  switch (CC) {
609  default:
610    llvm_unreachable("Invalid integer condition!");
611  case ISD::SETEQ:
612  case ISD::SETOEQ:
613    TCC = SystemZCC::E;
614    break;
615  case ISD::SETUEQ:
616    TCC = SystemZCC::NLH;
617    break;
618  case ISD::SETNE:
619  case ISD::SETONE:
620    TCC = SystemZCC::NE;
621    break;
622  case ISD::SETUNE:
623    TCC = SystemZCC::LH;
624    break;
625  case ISD::SETO:
626    TCC = SystemZCC::O;
627    break;
628  case ISD::SETUO:
629    TCC = SystemZCC::NO;
630    break;
631  case ISD::SETULE:
632    if (LHS.getValueType().isFloatingPoint()) {
633      TCC = SystemZCC::NH;
634      break;
635    }
636    isUnsigned = true;   // FALLTHROUGH
637  case ISD::SETLE:
638  case ISD::SETOLE:
639    TCC = SystemZCC::LE;
640    break;
641  case ISD::SETUGE:
642    if (LHS.getValueType().isFloatingPoint()) {
643      TCC = SystemZCC::NL;
644      break;
645    }
646    isUnsigned = true;   // FALLTHROUGH
647  case ISD::SETGE:
648  case ISD::SETOGE:
649    TCC = SystemZCC::HE;
650    break;
651  case ISD::SETUGT:
652    if (LHS.getValueType().isFloatingPoint()) {
653      TCC = SystemZCC::NLE;
654      break;
655    }
656    isUnsigned = true;  // FALLTHROUGH
657  case ISD::SETGT:
658  case ISD::SETOGT:
659    TCC = SystemZCC::H;
660    break;
661  case ISD::SETULT:
662    if (LHS.getValueType().isFloatingPoint()) {
663      TCC = SystemZCC::NHE;
664      break;
665    }
666    isUnsigned = true;  // FALLTHROUGH
667  case ISD::SETLT:
668  case ISD::SETOLT:
669    TCC = SystemZCC::L;
670    break;
671  }
672
673  SystemZCC = DAG.getConstant(TCC, MVT::i32);
674
675  DebugLoc dl = LHS.getDebugLoc();
676  return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
677                     dl, MVT::i64, LHS, RHS);
678}
679
680
681SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
682  SDValue Chain = Op.getOperand(0);
683  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
684  SDValue LHS   = Op.getOperand(2);
685  SDValue RHS   = Op.getOperand(3);
686  SDValue Dest  = Op.getOperand(4);
687  DebugLoc dl   = Op.getDebugLoc();
688
689  SDValue SystemZCC;
690  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
691  return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
692                     Chain, Dest, SystemZCC, Flag);
693}
694
695SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
696  SDValue LHS    = Op.getOperand(0);
697  SDValue RHS    = Op.getOperand(1);
698  SDValue TrueV  = Op.getOperand(2);
699  SDValue FalseV = Op.getOperand(3);
700  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
701  DebugLoc dl   = Op.getDebugLoc();
702
703  SDValue SystemZCC;
704  SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
705
706  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
707  SmallVector<SDValue, 4> Ops;
708  Ops.push_back(TrueV);
709  Ops.push_back(FalseV);
710  Ops.push_back(SystemZCC);
711  Ops.push_back(Flag);
712
713  return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
714}
715
716SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
717                                                  SelectionDAG &DAG) {
718  DebugLoc dl = Op.getDebugLoc();
719  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
720  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
721
722  bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
723  bool ExtraLoadRequired =
724    Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
725
726  SDValue Result;
727  if (!IsPic && !ExtraLoadRequired) {
728    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
729    Offset = 0;
730  } else {
731    unsigned char OpFlags = 0;
732    if (ExtraLoadRequired)
733      OpFlags = SystemZII::MO_GOTENT;
734
735    Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
736  }
737
738  Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
739                       getPointerTy(), Result);
740
741  if (ExtraLoadRequired)
742    Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
743                         PseudoSourceValue::getGOT(), 0, false, false, 0);
744
745  // If there was a non-zero offset that we didn't fold, create an explicit
746  // addition for it.
747  if (Offset != 0)
748    Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
749                         DAG.getConstant(Offset, getPointerTy()));
750
751  return Result;
752}
753
754// FIXME: PIC here
755SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
756                                              SelectionDAG &DAG) {
757  DebugLoc dl = Op.getDebugLoc();
758  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
759  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
760
761  return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
762}
763
764
765// FIXME: PIC here
766// FIXME: This is just dirty hack. We need to lower cpool properly
767SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
768                                                 SelectionDAG &DAG) {
769  DebugLoc dl = Op.getDebugLoc();
770  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
771
772  SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
773                                             CP->getAlignment(),
774                                             CP->getOffset());
775
776  return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
777}
778
779const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
780  switch (Opcode) {
781  case SystemZISD::RET_FLAG:           return "SystemZISD::RET_FLAG";
782  case SystemZISD::CALL:               return "SystemZISD::CALL";
783  case SystemZISD::BRCOND:             return "SystemZISD::BRCOND";
784  case SystemZISD::CMP:                return "SystemZISD::CMP";
785  case SystemZISD::UCMP:               return "SystemZISD::UCMP";
786  case SystemZISD::SELECT:             return "SystemZISD::SELECT";
787  case SystemZISD::PCRelativeWrapper:  return "SystemZISD::PCRelativeWrapper";
788  default: return NULL;
789  }
790}
791
792//===----------------------------------------------------------------------===//
793//  Other Lowering Code
794//===----------------------------------------------------------------------===//
795
796MachineBasicBlock*
797SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
798                                                   MachineBasicBlock *BB,
799                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
800  const SystemZInstrInfo &TII = *TM.getInstrInfo();
801  DebugLoc dl = MI->getDebugLoc();
802  assert((MI->getOpcode() == SystemZ::Select32  ||
803          MI->getOpcode() == SystemZ::SelectF32 ||
804          MI->getOpcode() == SystemZ::Select64  ||
805          MI->getOpcode() == SystemZ::SelectF64) &&
806         "Unexpected instr type to insert");
807
808  // To "insert" a SELECT instruction, we actually have to insert the diamond
809  // control-flow pattern.  The incoming instruction knows the destination vreg
810  // to set, the condition code register to branch on, the true/false values to
811  // select between, and a branch opcode to use.
812  const BasicBlock *LLVM_BB = BB->getBasicBlock();
813  MachineFunction::iterator I = BB;
814  ++I;
815
816  //  thisMBB:
817  //  ...
818  //   TrueVal = ...
819  //   cmpTY ccX, r1, r2
820  //   jCC copy1MBB
821  //   fallthrough --> copy0MBB
822  MachineBasicBlock *thisMBB = BB;
823  MachineFunction *F = BB->getParent();
824  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
825  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
826  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
827  BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
828  F->insert(I, copy0MBB);
829  F->insert(I, copy1MBB);
830  // Inform sdisel of the edge changes.
831  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
832         SE = BB->succ_end(); SI != SE; ++SI)
833    EM->insert(std::make_pair(*SI, copy1MBB));
834  // Update machine-CFG edges by transferring all successors of the current
835  // block to the new block which will contain the Phi node for the select.
836  copy1MBB->transferSuccessors(BB);
837  // Next, add the true and fallthrough blocks as its successors.
838  BB->addSuccessor(copy0MBB);
839  BB->addSuccessor(copy1MBB);
840
841  //  copy0MBB:
842  //   %FalseValue = ...
843  //   # fallthrough to copy1MBB
844  BB = copy0MBB;
845
846  // Update machine-CFG edges
847  BB->addSuccessor(copy1MBB);
848
849  //  copy1MBB:
850  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
851  //  ...
852  BB = copy1MBB;
853  BuildMI(BB, dl, TII.get(SystemZ::PHI),
854          MI->getOperand(0).getReg())
855    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
856    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
857
858  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
859  return BB;
860}
861