SystemZInstrFormats.td revision 722e9e6d0a5b67d136be40bc015abc5b0b32f97b
1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Basic SystemZ instruction definition 12//===----------------------------------------------------------------------===// 13 14class InstSystemZ<int size, dag outs, dag ins, string asmstr, 15 list<dag> pattern> : Instruction { 16 let Namespace = "SystemZ"; 17 18 dag OutOperandList = outs; 19 dag InOperandList = ins; 20 let Size = size; 21 let Pattern = pattern; 22 let AsmString = asmstr; 23 24 // Used to identify a group of related instructions, such as ST and STY. 25 string Function = ""; 26 27 // "12" for an instruction that has a ...Y equivalent, "20" for that 28 // ...Y equivalent. 29 string PairType = "none"; 30 31 // True if this instruction is a simple D(X,B) load of a register 32 // (with no sign or zero extension). 33 bit SimpleBDXLoad = 0; 34 35 // True if this instruction is a simple D(X,B) store of a register 36 // (with no truncation). 37 bit SimpleBDXStore = 0; 38 39 // True if this instruction has a 20-bit displacement field. 40 bit Has20BitOffset = 0; 41 42 // True if addresses in this instruction have an index register. 43 bit HasIndex = 0; 44 45 // True if this is a 128-bit pseudo instruction that combines two 64-bit 46 // operations. 47 bit Is128Bit = 0; 48 49 let TSFlags{0} = SimpleBDXLoad; 50 let TSFlags{1} = SimpleBDXStore; 51 let TSFlags{2} = Has20BitOffset; 52 let TSFlags{3} = HasIndex; 53 let TSFlags{4} = Is128Bit; 54} 55 56//===----------------------------------------------------------------------===// 57// Mappings between instructions 58//===----------------------------------------------------------------------===// 59 60// Return the version of an instruction that has an unsigned 12-bit 61// displacement. 62def getDisp12Opcode : InstrMapping { 63 let FilterClass = "InstSystemZ"; 64 let RowFields = ["Function"]; 65 let ColFields = ["PairType"]; 66 let KeyCol = ["20"]; 67 let ValueCols = [["12"]]; 68} 69 70// Return the version of an instruction that has a signed 20-bit displacement. 71def getDisp20Opcode : InstrMapping { 72 let FilterClass = "InstSystemZ"; 73 let RowFields = ["Function"]; 74 let ColFields = ["PairType"]; 75 let KeyCol = ["12"]; 76 let ValueCols = [["20"]]; 77} 78 79//===----------------------------------------------------------------------===// 80// Instruction formats 81//===----------------------------------------------------------------------===// 82// 83// Formats are specified using operand field declarations of the form: 84// 85// bits<4> Rn : register input or output for operand n 86// bits<m> In : immediate value of width m for operand n 87// bits<4> BDn : address operand n, which has a base and a displacement 88// bits<m> XBDn : address operand n, which has an index, a base and a 89// displacement 90// bits<4> Xn : index register for address operand n 91// bits<4> Mn : mode value for operand n 92// 93// The operand numbers ("n" in the list above) follow the architecture manual. 94// Assembly operands sometimes have a different order; in particular, R3 often 95// is often written between operands 1 and 2. 96// 97//===----------------------------------------------------------------------===// 98 99class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 100 : InstSystemZ<4, outs, ins, asmstr, pattern> { 101 field bits<32> Inst; 102 field bits<32> SoftFail = 0; 103 104 bits<4> R1; 105 bits<16> I2; 106 107 let Inst{31-24} = op{11-4}; 108 let Inst{23-20} = R1; 109 let Inst{19-16} = op{3-0}; 110 let Inst{15-0} = I2; 111} 112 113class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 114 : InstSystemZ<6, outs, ins, asmstr, pattern> { 115 field bits<48> Inst; 116 field bits<48> SoftFail = 0; 117 118 bits<4> R1; 119 bits<4> R2; 120 bits<4> M3; 121 bits<16> RI4; 122 123 let Inst{47-40} = op{15-8}; 124 let Inst{39-36} = R1; 125 let Inst{35-32} = R2; 126 let Inst{31-16} = RI4; 127 let Inst{15-12} = M3; 128 let Inst{11-8} = 0; 129 let Inst{7-0} = op{7-0}; 130} 131 132class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 133 : InstSystemZ<6, outs, ins, asmstr, pattern> { 134 field bits<48> Inst; 135 field bits<48> SoftFail = 0; 136 137 bits<4> R1; 138 bits<8> I2; 139 bits<4> M3; 140 bits<16> RI4; 141 142 let Inst{47-40} = op{15-8}; 143 let Inst{39-36} = R1; 144 let Inst{35-32} = M3; 145 let Inst{31-16} = RI4; 146 let Inst{15-8} = I2; 147 let Inst{7-0} = op{7-0}; 148} 149 150class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 151 : InstSystemZ<6, outs, ins, asmstr, pattern> { 152 field bits<48> Inst; 153 field bits<48> SoftFail = 0; 154 155 bits<4> R1; 156 bits<4> R2; 157 bits<8> I3; 158 bits<8> I4; 159 bits<8> I5; 160 161 let Inst{47-40} = op{15-8}; 162 let Inst{39-36} = R1; 163 let Inst{35-32} = R2; 164 let Inst{31-24} = I3; 165 let Inst{23-16} = I4; 166 let Inst{15-8} = I5; 167 let Inst{7-0} = op{7-0}; 168} 169 170class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 171 : InstSystemZ<6, outs, ins, asmstr, pattern> { 172 field bits<48> Inst; 173 field bits<48> SoftFail = 0; 174 175 bits<4> R1; 176 bits<32> I2; 177 178 let Inst{47-40} = op{11-4}; 179 let Inst{39-36} = R1; 180 let Inst{35-32} = op{3-0}; 181 let Inst{31-0} = I2; 182} 183 184class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 185 : InstSystemZ<2, outs, ins, asmstr, pattern> { 186 field bits<16> Inst; 187 field bits<16> SoftFail = 0; 188 189 bits<4> R1; 190 bits<4> R2; 191 192 let Inst{15-8} = op; 193 let Inst{7-4} = R1; 194 let Inst{3-0} = R2; 195} 196 197class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 198 : InstSystemZ<4, outs, ins, asmstr, pattern> { 199 field bits<32> Inst; 200 field bits<32> SoftFail = 0; 201 202 bits<4> R1; 203 bits<4> R3; 204 bits<4> R2; 205 206 let Inst{31-16} = op; 207 let Inst{15-12} = R1; 208 let Inst{11-8} = 0; 209 let Inst{7-4} = R3; 210 let Inst{3-0} = R2; 211} 212 213class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 214 : InstSystemZ<4, outs, ins, asmstr, pattern> { 215 field bits<32> Inst; 216 field bits<32> SoftFail = 0; 217 218 bits<4> R1; 219 bits<4> R2; 220 221 let Inst{31-16} = op; 222 let Inst{15-8} = 0; 223 let Inst{7-4} = R1; 224 let Inst{3-0} = R2; 225} 226 227class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 228 : InstSystemZ<4, outs, ins, asmstr, pattern> { 229 field bits<32> Inst; 230 field bits<32> SoftFail = 0; 231 232 bits<4> R1; 233 bits<4> R2; 234 bits<4> R3; 235 236 let Inst{31-16} = op; 237 let Inst{15-12} = R3; 238 let Inst{11-8} = 0; 239 let Inst{7-4} = R1; 240 let Inst{3-0} = R2; 241} 242 243class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 244 : InstSystemZ<4, outs, ins, asmstr, pattern> { 245 field bits<32> Inst; 246 field bits<32> SoftFail = 0; 247 248 bits<4> R1; 249 bits<20> XBD2; 250 251 let Inst{31-24} = op; 252 let Inst{23-20} = R1; 253 let Inst{19-0} = XBD2; 254 255 let HasIndex = 1; 256} 257 258class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 259 : InstSystemZ<6, outs, ins, asmstr, pattern> { 260 field bits<48> Inst; 261 field bits<48> SoftFail = 0; 262 263 bits<4> R1; 264 bits<20> XBD2; 265 266 let Inst{47-40} = op{15-8}; 267 let Inst{39-36} = R1; 268 let Inst{35-16} = XBD2; 269 let Inst{15-8} = 0; 270 let Inst{7-0} = op{7-0}; 271 272 let HasIndex = 1; 273} 274 275class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 276 : InstSystemZ<6, outs, ins, asmstr, pattern> { 277 field bits<48> Inst; 278 field bits<48> SoftFail = 0; 279 280 bits<4> R1; 281 bits<4> R3; 282 bits<20> XBD2; 283 284 let Inst{47-40} = op{15-8}; 285 let Inst{39-36} = R3; 286 let Inst{35-16} = XBD2; 287 let Inst{15-12} = R1; 288 let Inst{11-8} = 0; 289 let Inst{7-0} = op{7-0}; 290 291 let HasIndex = 1; 292} 293 294class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 295 : InstSystemZ<6, outs, ins, asmstr, pattern> { 296 field bits<48> Inst; 297 field bits<48> SoftFail = 0; 298 299 bits<4> R1; 300 bits<28> XBD2; 301 302 let Inst{47-40} = op{15-8}; 303 let Inst{39-36} = R1; 304 let Inst{35-8} = XBD2; 305 let Inst{7-0} = op{7-0}; 306 307 let Has20BitOffset = 1; 308 let HasIndex = 1; 309} 310 311class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 312 : InstSystemZ<4, outs, ins, asmstr, pattern> { 313 field bits<32> Inst; 314 field bits<32> SoftFail = 0; 315 316 bits<4> R1; 317 bits<4> R3; 318 bits<16> BD2; 319 320 let Inst{31-24} = op; 321 let Inst{23-20} = R1; 322 let Inst{19-16} = R3; 323 let Inst{15-0} = BD2; 324} 325 326class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 327 : InstSystemZ<6, outs, ins, asmstr, pattern> { 328 field bits<48> Inst; 329 field bits<48> SoftFail = 0; 330 331 bits<4> R1; 332 bits<4> R3; 333 bits<24> BD2; 334 335 let Inst{47-40} = op{15-8}; 336 let Inst{39-36} = R1; 337 let Inst{35-32} = R3; 338 let Inst{31-8} = BD2; 339 let Inst{7-0} = op{7-0}; 340 341 let Has20BitOffset = 1; 342} 343 344class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 345 : InstSystemZ<4, outs, ins, asmstr, pattern> { 346 field bits<32> Inst; 347 field bits<32> SoftFail = 0; 348 349 bits<16> BD1; 350 bits<8> I2; 351 352 let Inst{31-24} = op; 353 let Inst{23-16} = I2; 354 let Inst{15-0} = BD1; 355} 356 357class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 358 : InstSystemZ<6, outs, ins, asmstr, pattern> { 359 field bits<48> Inst; 360 field bits<48> SoftFail = 0; 361 362 bits<16> BD1; 363 bits<16> I2; 364 365 let Inst{47-32} = op; 366 let Inst{31-16} = BD1; 367 let Inst{15-0} = I2; 368} 369 370class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 371 : InstSystemZ<6, outs, ins, asmstr, pattern> { 372 field bits<48> Inst; 373 field bits<48> SoftFail = 0; 374 375 bits<24> BD1; 376 bits<8> I2; 377 378 let Inst{47-40} = op{15-8}; 379 let Inst{39-32} = I2; 380 let Inst{31-8} = BD1; 381 let Inst{7-0} = op{7-0}; 382 383 let Has20BitOffset = 1; 384} 385 386//===----------------------------------------------------------------------===// 387// Instruction definitions with semantics 388//===----------------------------------------------------------------------===// 389// 390// These classes have the form <Category><Format>, where <Format> is one 391// of the formats defined above and where <Category> describes the inputs 392// and outputs. <Category> can be one of: 393// 394// Inherent: 395// One register output operand and no input operands. 396// 397// Store: 398// One register or immediate input operand and one address input operand. 399// The instruction stores the first operand to the address. 400// 401// This category is used for both pure and truncating stores. 402// 403// LoadMultiple: 404// One address input operand and two explicit output operands. 405// The instruction loads a range of registers from the address, 406// with the explicit operands giving the first and last register 407// to load. Other loaded registers are added as implicit definitions. 408// 409// StoreMultiple: 410// Two explicit input register operands and an address operand. 411// The instruction stores a range of registers to the address, 412// with the explicit operands giving the first and last register 413// to store. Other stored registers are added as implicit uses. 414// 415// Unary: 416// One register output operand and one input operand. The input 417// operand may be a register, immediate or memory. 418// 419// Binary: 420// One register output operand and two input operands. The first 421// input operand is always a register and he second may be a register, 422// immediate or memory. 423// 424// Shift: 425// One register output operand and two input operands. The first 426// input operand is a register and the second has the same form as 427// an address (although it isn't actually used to address memory). 428// 429// Compare: 430// Two input operands. The first operand is always a register, 431// the second may be a register, immediate or memory. 432// 433// Ternary: 434// One register output operand and three register input operands. 435// 436// CmpSwap: 437// One output operand and three input operands. The first two 438// operands are registers and the third is an address. The instruction 439// both reads from and writes to the address. 440// 441// RotateSelect: 442// One output operand and five input operands. The first two operands 443// are registers and the other three are immediates. 444// 445// The format determines which input operands are tied to output operands, 446// and also determines the shape of any address operand. 447// 448// Multiclasses of the form <Category><Format>Pair define two instructions, 449// one with <Category><Format> and one with <Category><Format>Y. The name 450// of the first instruction has no suffix, the name of the second has 451// an extra "y". 452// 453//===----------------------------------------------------------------------===// 454 455class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 456 dag src> 457 : InstRRE<opcode, (outs cls:$R1), (ins), 458 mnemonic#"\t$R1", 459 [(set cls:$R1, src)]> { 460 let R2 = 0; 461} 462 463class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 464 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2), 465 mnemonic#"\t$R1, $R3, $BD2", []> { 466 let mayLoad = 1; 467} 468 469class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 470 RegisterOperand cls> 471 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 472 mnemonic#"\t$R1, $I2", 473 [(operator cls:$R1, pcrel32:$I2)]> { 474 let mayStore = 1; 475 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 476 // However, BDXs have two extra operands and are therefore 6 units more 477 // complex. 478 let AddedComplexity = 7; 479} 480 481class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 482 RegisterOperand cls, AddressingMode mode = bdxaddr12only> 483 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 484 mnemonic#"\t$R1, $XBD2", 485 [(operator cls:$R1, mode:$XBD2)]> { 486 let mayStore = 1; 487} 488 489class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 490 RegisterOperand cls, AddressingMode mode = bdxaddr20only> 491 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 492 mnemonic#"\t$R1, $XBD2", 493 [(operator cls:$R1, mode:$XBD2)]> { 494 let mayStore = 1; 495} 496 497multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 498 SDPatternOperator operator, RegisterOperand cls> { 499 let Function = mnemonic ## #cls in { 500 let PairType = "12" in 501 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>; 502 let PairType = "20" in 503 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>; 504 } 505} 506 507class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 508 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2), 509 mnemonic#"\t$R1, $R3, $BD2", []> { 510 let mayStore = 1; 511} 512 513class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 514 Immediate imm, AddressingMode mode = bdaddr12only> 515 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 516 mnemonic#"\t$BD1, $I2", 517 [(operator imm:$I2, mode:$BD1)]> { 518 let mayStore = 1; 519} 520 521class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 522 Immediate imm, AddressingMode mode = bdaddr20only> 523 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 524 mnemonic#"\t$BD1, $I2", 525 [(operator imm:$I2, mode:$BD1)]> { 526 let mayStore = 1; 527} 528 529class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 530 Immediate imm> 531 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 532 mnemonic#"\t$BD1, $I2", 533 [(operator imm:$I2, bdaddr12only:$BD1)]> { 534 let mayStore = 1; 535} 536 537multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 538 SDPatternOperator operator, Immediate imm> { 539 let Function = mnemonic in { 540 let PairType = "12" in 541 def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 542 let PairType = "20" in 543 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 544 } 545} 546 547class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 548 RegisterOperand cls1, RegisterOperand cls2> 549 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 550 mnemonic#"\t$R1, $R2", 551 [(set cls1:$R1, (operator cls2:$R2))]>; 552 553class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 554 RegisterOperand cls1, RegisterOperand cls2> 555 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 556 mnemonic#"\t$R1, $R2", 557 [(set cls1:$R1, (operator cls2:$R2))]>; 558 559class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 560 RegisterOperand cls2> 561 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2), 562 mnemonic#"\t$R1, $R3, $R2", []>; 563 564class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 565 RegisterOperand cls, Immediate imm> 566 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2), 567 mnemonic#"\t$R1, $I2", 568 [(set cls:$R1, (operator imm:$I2))]>; 569 570class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 571 RegisterOperand cls, Immediate imm> 572 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2), 573 mnemonic#"\t$R1, $I2", 574 [(set cls:$R1, (operator imm:$I2))]>; 575 576class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 577 RegisterOperand cls> 578 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2), 579 mnemonic#"\t$R1, $I2", 580 [(set cls:$R1, (operator pcrel32:$I2))]> { 581 let mayLoad = 1; 582 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 583 // However, BDXs have two extra operands and are therefore 6 units more 584 // complex. 585 let AddedComplexity = 7; 586} 587 588class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 589 RegisterOperand cls, AddressingMode mode = bdxaddr12only> 590 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2), 591 mnemonic#"\t$R1, $XBD2", 592 [(set cls:$R1, (operator mode:$XBD2))]> { 593 let mayLoad = 1; 594} 595 596class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 597 RegisterOperand cls> 598 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2), 599 mnemonic#"\t$R1, $XBD2", 600 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 601 let mayLoad = 1; 602} 603 604class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 605 RegisterOperand cls, AddressingMode mode = bdxaddr20only> 606 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2), 607 mnemonic#"\t$R1, $XBD2", 608 [(set cls:$R1, (operator mode:$XBD2))]> { 609 let mayLoad = 1; 610} 611 612multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 613 SDPatternOperator operator, RegisterOperand cls> { 614 let Function = mnemonic ## #cls in { 615 let PairType = "12" in 616 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>; 617 let PairType = "20" in 618 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>; 619 } 620} 621 622class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 623 RegisterOperand cls1, RegisterOperand cls2> 624 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 625 mnemonic#"\t$R1, $R2", 626 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 627 let Constraints = "$R1 = $R1src"; 628 let DisableEncoding = "$R1src"; 629} 630 631class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 632 RegisterOperand cls1, RegisterOperand cls2> 633 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 634 mnemonic#"\t$R1, $R2", 635 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 636 let Constraints = "$R1 = $R1src"; 637 let DisableEncoding = "$R1src"; 638} 639 640class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 641 RegisterOperand cls1, RegisterOperand cls2> 642 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2), 643 mnemonic#"\t$R1, $R3, $R2", 644 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]>; 645 646class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 647 RegisterOperand cls, Immediate imm> 648 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 649 mnemonic#"\t$R1, $I2", 650 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 651 let Constraints = "$R1 = $R1src"; 652 let DisableEncoding = "$R1src"; 653} 654 655class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 656 RegisterOperand cls, Immediate imm> 657 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 658 mnemonic#"\t$R1, $I2", 659 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 660 let Constraints = "$R1 = $R1src"; 661 let DisableEncoding = "$R1src"; 662} 663 664class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 665 RegisterOperand cls, SDPatternOperator load, 666 AddressingMode mode = bdxaddr12only> 667 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 668 mnemonic#"\t$R1, $XBD2", 669 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 670 let Constraints = "$R1 = $R1src"; 671 let DisableEncoding = "$R1src"; 672 let mayLoad = 1; 673} 674 675class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 676 RegisterOperand cls, SDPatternOperator load> 677 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2), 678 mnemonic#"\t$R1, $XBD2", 679 [(set cls:$R1, (operator cls:$R1src, 680 (load bdxaddr12only:$XBD2)))]> { 681 let Constraints = "$R1 = $R1src"; 682 let DisableEncoding = "$R1src"; 683 let mayLoad = 1; 684} 685 686class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 687 RegisterOperand cls, SDPatternOperator load, 688 AddressingMode mode = bdxaddr20only> 689 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 690 mnemonic#"\t$R1, $XBD2", 691 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 692 let Constraints = "$R1 = $R1src"; 693 let DisableEncoding = "$R1src"; 694 let mayLoad = 1; 695} 696 697multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 698 SDPatternOperator operator, RegisterOperand cls, 699 SDPatternOperator load> { 700 let Function = mnemonic ## #cls in { 701 let PairType = "12" in 702 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bdxaddr12pair>; 703 let PairType = "20" in 704 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, 705 bdxaddr20pair>; 706 } 707} 708 709class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 710 Operand imm, AddressingMode mode = bdaddr12only> 711 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 712 mnemonic#"\t$BD1, $I2", 713 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 714 let mayLoad = 1; 715 let mayStore = 1; 716} 717 718class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 719 Operand imm, AddressingMode mode = bdaddr20only> 720 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 721 mnemonic#"\t$BD1, $I2", 722 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 723 let mayLoad = 1; 724 let mayStore = 1; 725} 726 727multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 728 bits<16> siyOpcode, SDPatternOperator operator, 729 Operand imm> { 730 let Function = mnemonic ## #cls in { 731 let PairType = "12" in 732 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 733 let PairType = "20" in 734 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 735 } 736} 737 738class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 739 RegisterOperand cls, AddressingMode mode> 740 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2), 741 mnemonic#"\t$R1, $BD2", 742 [(set cls:$R1, (operator cls:$R1src, mode:$BD2))]> { 743 let R3 = 0; 744 let Constraints = "$R1 = $R1src"; 745 let DisableEncoding = "$R1src"; 746} 747 748class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 749 RegisterOperand cls, AddressingMode mode> 750 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2), 751 mnemonic#"\t$R1, $R3, $BD2", 752 [(set cls:$R1, (operator cls:$R3, mode:$BD2))]>; 753 754class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 755 RegisterOperand cls1, RegisterOperand cls2> 756 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 757 mnemonic#"\t$R1, $R2", 758 [(operator cls1:$R1, cls2:$R2)]>; 759 760class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 761 RegisterOperand cls1, RegisterOperand cls2> 762 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 763 mnemonic#"\t$R1, $R2", 764 [(operator cls1:$R1, cls2:$R2)]>; 765 766class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 767 RegisterOperand cls, Immediate imm> 768 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2), 769 mnemonic#"\t$R1, $I2", 770 [(operator cls:$R1, imm:$I2)]>; 771 772class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 773 RegisterOperand cls, Immediate imm> 774 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2), 775 mnemonic#"\t$R1, $I2", 776 [(operator cls:$R1, imm:$I2)]>; 777 778class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 779 RegisterOperand cls, SDPatternOperator load> 780 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 781 mnemonic#"\t$R1, $I2", 782 [(operator cls:$R1, (load pcrel32:$I2))]> { 783 let mayLoad = 1; 784 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 785 // However, BDXs have two extra operands and are therefore 6 units more 786 // complex. 787 let AddedComplexity = 7; 788} 789 790class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 791 RegisterOperand cls, SDPatternOperator load, 792 AddressingMode mode = bdxaddr12only> 793 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 794 mnemonic#"\t$R1, $XBD2", 795 [(operator cls:$R1, (load mode:$XBD2))]> { 796 let mayLoad = 1; 797} 798 799class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 800 RegisterOperand cls, SDPatternOperator load> 801 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 802 mnemonic#"\t$R1, $XBD2", 803 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> { 804 let mayLoad = 1; 805} 806 807class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 808 RegisterOperand cls, SDPatternOperator load, 809 AddressingMode mode = bdxaddr20only> 810 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 811 mnemonic#"\t$R1, $XBD2", 812 [(operator cls:$R1, (load mode:$XBD2))]> { 813 let mayLoad = 1; 814} 815 816multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 817 SDPatternOperator operator, RegisterOperand cls, 818 SDPatternOperator load> { 819 let Function = mnemonic ## #cls in { 820 let PairType = "12" in 821 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 822 load, bdxaddr12pair>; 823 let PairType = "20" in 824 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 825 load, bdxaddr20pair>; 826 } 827} 828 829class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 830 SDPatternOperator load, Immediate imm, 831 AddressingMode mode = bdaddr12only> 832 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 833 mnemonic#"\t$BD1, $I2", 834 [(operator (load mode:$BD1), imm:$I2)]> { 835 let mayLoad = 1; 836} 837 838class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 839 SDPatternOperator load, Immediate imm> 840 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 841 mnemonic#"\t$BD1, $I2", 842 [(operator (load bdaddr12only:$BD1), imm:$I2)]> { 843 let mayLoad = 1; 844} 845 846class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 847 SDPatternOperator load, Immediate imm, 848 AddressingMode mode = bdaddr20only> 849 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 850 mnemonic#"\t$BD1, $I2", 851 [(operator (load mode:$BD1), imm:$I2)]> { 852 let mayLoad = 1; 853} 854 855multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 856 SDPatternOperator operator, SDPatternOperator load, 857 Immediate imm> { 858 let Function = mnemonic in { 859 let PairType = "12" in 860 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 861 let PairType = "20" in 862 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 863 bdaddr20pair>; 864 } 865} 866 867class TernaryRRD<string mnemonic, bits<16> opcode, 868 SDPatternOperator operator, RegisterOperand cls> 869 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2), 870 mnemonic#"\t$R1, $R3, $R2", 871 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> { 872 let Constraints = "$R1 = $R1src"; 873 let DisableEncoding = "$R1src"; 874} 875 876class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 877 RegisterOperand cls, SDPatternOperator load> 878 : InstRXF<opcode, (outs cls:$R1), 879 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2), 880 mnemonic#"\t$R1, $R3, $XBD2", 881 [(set cls:$R1, (operator cls:$R1src, cls:$R3, 882 (load bdxaddr12only:$XBD2)))]> { 883 let Constraints = "$R1 = $R1src"; 884 let DisableEncoding = "$R1src"; 885 let mayLoad = 1; 886} 887 888class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 889 RegisterOperand cls, AddressingMode mode = bdaddr12only> 890 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 891 mnemonic#"\t$R1, $R3, $BD2", 892 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 893 let Constraints = "$R1 = $R1src"; 894 let DisableEncoding = "$R1src"; 895 let mayLoad = 1; 896 let mayStore = 1; 897} 898 899class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 900 RegisterOperand cls, AddressingMode mode = bdaddr20only> 901 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 902 mnemonic#"\t$R1, $R3, $BD2", 903 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 904 let Constraints = "$R1 = $R1src"; 905 let DisableEncoding = "$R1src"; 906 let mayLoad = 1; 907 let mayStore = 1; 908} 909 910multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 911 SDPatternOperator operator, RegisterOperand cls> { 912 let Function = mnemonic ## #cls in { 913 let PairType = "12" in 914 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 915 let PairType = "20" in 916 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 917 } 918} 919 920class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 921 RegisterOperand cls2> 922 : InstRIEf<opcode, (outs cls1:$R1), 923 (ins cls1:$R1src, cls2:$R2, 924 uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5), 925 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> { 926 let Constraints = "$R1 = $R1src"; 927 let DisableEncoding = "$R1src"; 928} 929 930//===----------------------------------------------------------------------===// 931// Pseudo instructions 932//===----------------------------------------------------------------------===// 933// 934// Convenience instructions that get lowered to real instructions 935// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 936// or SystemZInstrInfo::expandPostRAPseudo(). 937// 938//===----------------------------------------------------------------------===// 939 940class Pseudo<dag outs, dag ins, list<dag> pattern> 941 : InstSystemZ<0, outs, ins, "", pattern> { 942 let isPseudo = 1; 943 let isCodeGenOnly = 1; 944} 945 946// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 947// the value of the PSW's 2-bit condition code field. 948class SelectWrapper<RegisterOperand cls> 949 : Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc), 950 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> { 951 let usesCustomInserter = 1; 952 // Although the instructions used by these nodes do not in themselves 953 // change CC, the insertion requires new blocks, and CC cannot be live 954 // across them. 955 let Defs = [CC]; 956 let Uses = [CC]; 957} 958 959// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 960multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 961 SDPatternOperator load, AddressingMode mode> { 962 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in { 963 def "" : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc), 964 [(store (z_select_ccmask cls:$new, (load mode:$addr), 965 imm:$cc), mode:$addr)]>; 966 def Inv : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc), 967 [(store (z_select_ccmask (load mode:$addr), cls:$new, 968 imm:$cc), mode:$addr)]>; 969 } 970} 971 972// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND 973// describe the second (non-memory) operand. 974class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls, 975 dag pat, DAGOperand operand> 976 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2), 977 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> { 978 let Defs = [CC]; 979 let Has20BitOffset = 1; 980 let mayLoad = 1; 981 let mayStore = 1; 982 let usesCustomInserter = 1; 983} 984 985// Specializations of AtomicLoadWBinary. 986class AtomicLoadBinaryReg32<SDPatternOperator operator> 987 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>; 988class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm> 989 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>; 990class AtomicLoadBinaryReg64<SDPatternOperator operator> 991 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>; 992class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm> 993 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>; 994 995// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 996// describe the second (non-memory) operand. 997class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 998 DAGOperand operand> 999 : Pseudo<(outs GR32:$dst), 1000 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 1001 ADDR32:$negbitshift, uimm32:$bitsize), 1002 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 1003 ADDR32:$negbitshift, uimm32:$bitsize))]> { 1004 let Defs = [CC]; 1005 let Has20BitOffset = 1; 1006 let mayLoad = 1; 1007 let mayStore = 1; 1008 let usesCustomInserter = 1; 1009} 1010 1011// Specializations of AtomicLoadWBinary. 1012class AtomicLoadWBinaryReg<SDPatternOperator operator> 1013 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 1014class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm> 1015 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 1016