SystemZInstrFormats.td revision d954716e7567282ff6f3d25b4f404bae006eed04
1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Basic SystemZ instruction definition 12//===----------------------------------------------------------------------===// 13 14class InstSystemZ<int size, dag outs, dag ins, string asmstr, 15 list<dag> pattern> : Instruction { 16 let Namespace = "SystemZ"; 17 18 dag OutOperandList = outs; 19 dag InOperandList = ins; 20 let Size = size; 21 let Pattern = pattern; 22 let AsmString = asmstr; 23 24 // Some instructions come in pairs, one having a 12-bit displacement 25 // and the other having a 20-bit displacement. Both instructions in 26 // the pair have the same DispKey and their DispSizes are "12" and "20" 27 // respectively. 28 string DispKey = ""; 29 string DispSize = "none"; 30 31 // Many register-based <INSN>R instructions have a memory-based <INSN> 32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is 33 // "reg" for <INSN>R and "mem" for <INSN>. 34 string OpKey = ""; 35 string OpType = "none"; 36 37 // Many distinct-operands instructions have older 2-operand equivalents. 38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs, 39 // with NumOpsValue being "2" or "3" as appropriate. 40 string NumOpsKey = ""; 41 string NumOpsValue = "none"; 42 43 // True if this instruction is a simple D(X,B) load of a register 44 // (with no sign or zero extension). 45 bit SimpleBDXLoad = 0; 46 47 // True if this instruction is a simple D(X,B) store of a register 48 // (with no truncation). 49 bit SimpleBDXStore = 0; 50 51 // True if this instruction has a 20-bit displacement field. 52 bit Has20BitOffset = 0; 53 54 // True if addresses in this instruction have an index register. 55 bit HasIndex = 0; 56 57 // True if this is a 128-bit pseudo instruction that combines two 64-bit 58 // operations. 59 bit Is128Bit = 0; 60 61 // The access size of all memory operands in bytes, or 0 if not known. 62 bits<5> AccessBytes = 0; 63 64 // If the instruction sets CC to a useful value, this gives the mask 65 // of all possible CC results. The mask has the same form as 66 // SystemZ::CCMASK_*. 67 bits<4> CCValues = 0; 68 69 // The subset of CCValues that have the same meaning as they would after 70 // a comparison of the first operand against zero. 71 bits<4> CompareZeroCCMask = 0; 72 73 // True if the instruction is conditional and if the CC mask operand 74 // comes first (as for BRC, etc.). 75 bit CCMaskFirst = 0; 76 77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.). 78 bit CCMaskLast = 0; 79 80 // True if the instruction is the "logical" rather than "arithmetic" form, 81 // in cases where a distinction exists. 82 bit IsLogical = 0; 83 84 let TSFlags{0} = SimpleBDXLoad; 85 let TSFlags{1} = SimpleBDXStore; 86 let TSFlags{2} = Has20BitOffset; 87 let TSFlags{3} = HasIndex; 88 let TSFlags{4} = Is128Bit; 89 let TSFlags{9-5} = AccessBytes; 90 let TSFlags{13-10} = CCValues; 91 let TSFlags{17-14} = CompareZeroCCMask; 92 let TSFlags{18} = CCMaskFirst; 93 let TSFlags{19} = CCMaskLast; 94 let TSFlags{20} = IsLogical; 95} 96 97//===----------------------------------------------------------------------===// 98// Mappings between instructions 99//===----------------------------------------------------------------------===// 100 101// Return the version of an instruction that has an unsigned 12-bit 102// displacement. 103def getDisp12Opcode : InstrMapping { 104 let FilterClass = "InstSystemZ"; 105 let RowFields = ["DispKey"]; 106 let ColFields = ["DispSize"]; 107 let KeyCol = ["20"]; 108 let ValueCols = [["12"]]; 109} 110 111// Return the version of an instruction that has a signed 20-bit displacement. 112def getDisp20Opcode : InstrMapping { 113 let FilterClass = "InstSystemZ"; 114 let RowFields = ["DispKey"]; 115 let ColFields = ["DispSize"]; 116 let KeyCol = ["12"]; 117 let ValueCols = [["20"]]; 118} 119 120// Return the memory form of a register instruction. 121def getMemOpcode : InstrMapping { 122 let FilterClass = "InstSystemZ"; 123 let RowFields = ["OpKey"]; 124 let ColFields = ["OpType"]; 125 let KeyCol = ["reg"]; 126 let ValueCols = [["mem"]]; 127} 128 129// Return the 3-operand form of a 2-operand instruction. 130def getThreeOperandOpcode : InstrMapping { 131 let FilterClass = "InstSystemZ"; 132 let RowFields = ["NumOpsKey"]; 133 let ColFields = ["NumOpsValue"]; 134 let KeyCol = ["2"]; 135 let ValueCols = [["3"]]; 136} 137 138//===----------------------------------------------------------------------===// 139// Instruction formats 140//===----------------------------------------------------------------------===// 141// 142// Formats are specified using operand field declarations of the form: 143// 144// bits<4> Rn : register input or output for operand n 145// bits<m> In : immediate value of width m for operand n 146// bits<4> BDn : address operand n, which has a base and a displacement 147// bits<m> XBDn : address operand n, which has an index, a base and a 148// displacement 149// bits<4> Xn : index register for address operand n 150// bits<4> Mn : mode value for operand n 151// 152// The operand numbers ("n" in the list above) follow the architecture manual. 153// Assembly operands sometimes have a different order; in particular, R3 often 154// is often written between operands 1 and 2. 155// 156//===----------------------------------------------------------------------===// 157 158class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 159 : InstSystemZ<4, outs, ins, asmstr, pattern> { 160 field bits<32> Inst; 161 field bits<32> SoftFail = 0; 162 163 bits<4> R1; 164 bits<16> I2; 165 166 let Inst{31-24} = op{11-4}; 167 let Inst{23-20} = R1; 168 let Inst{19-16} = op{3-0}; 169 let Inst{15-0} = I2; 170} 171 172class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 173 : InstSystemZ<6, outs, ins, asmstr, pattern> { 174 field bits<48> Inst; 175 field bits<48> SoftFail = 0; 176 177 bits<4> R1; 178 bits<4> R2; 179 bits<4> M3; 180 bits<16> RI4; 181 182 let Inst{47-40} = op{15-8}; 183 let Inst{39-36} = R1; 184 let Inst{35-32} = R2; 185 let Inst{31-16} = RI4; 186 let Inst{15-12} = M3; 187 let Inst{11-8} = 0; 188 let Inst{7-0} = op{7-0}; 189} 190 191class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 192 : InstSystemZ<6, outs, ins, asmstr, pattern> { 193 field bits<48> Inst; 194 field bits<48> SoftFail = 0; 195 196 bits<4> R1; 197 bits<8> I2; 198 bits<4> M3; 199 bits<16> RI4; 200 201 let Inst{47-40} = op{15-8}; 202 let Inst{39-36} = R1; 203 let Inst{35-32} = M3; 204 let Inst{31-16} = RI4; 205 let Inst{15-8} = I2; 206 let Inst{7-0} = op{7-0}; 207} 208 209class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 210 : InstSystemZ<6, outs, ins, asmstr, pattern> { 211 field bits<48> Inst; 212 field bits<48> SoftFail = 0; 213 214 bits<4> R1; 215 bits<4> R3; 216 bits<16> I2; 217 218 let Inst{47-40} = op{15-8}; 219 let Inst{39-36} = R1; 220 let Inst{35-32} = R3; 221 let Inst{31-16} = I2; 222 let Inst{15-8} = 0; 223 let Inst{7-0} = op{7-0}; 224} 225 226class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 227 : InstSystemZ<6, outs, ins, asmstr, pattern> { 228 field bits<48> Inst; 229 field bits<48> SoftFail = 0; 230 231 bits<4> R1; 232 bits<4> R2; 233 bits<8> I3; 234 bits<8> I4; 235 bits<8> I5; 236 237 let Inst{47-40} = op{15-8}; 238 let Inst{39-36} = R1; 239 let Inst{35-32} = R2; 240 let Inst{31-24} = I3; 241 let Inst{23-16} = I4; 242 let Inst{15-8} = I5; 243 let Inst{7-0} = op{7-0}; 244} 245 246class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 247 : InstSystemZ<6, outs, ins, asmstr, pattern> { 248 field bits<48> Inst; 249 field bits<48> SoftFail = 0; 250 251 bits<4> R1; 252 bits<32> I2; 253 254 let Inst{47-40} = op{11-4}; 255 let Inst{39-36} = R1; 256 let Inst{35-32} = op{3-0}; 257 let Inst{31-0} = I2; 258} 259 260class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 261 : InstSystemZ<2, outs, ins, asmstr, pattern> { 262 field bits<16> Inst; 263 field bits<16> SoftFail = 0; 264 265 bits<4> R1; 266 bits<4> R2; 267 268 let Inst{15-8} = op; 269 let Inst{7-4} = R1; 270 let Inst{3-0} = R2; 271} 272 273class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 274 : InstSystemZ<4, outs, ins, asmstr, pattern> { 275 field bits<32> Inst; 276 field bits<32> SoftFail = 0; 277 278 bits<4> R1; 279 bits<4> R3; 280 bits<4> R2; 281 282 let Inst{31-16} = op; 283 let Inst{15-12} = R1; 284 let Inst{11-8} = 0; 285 let Inst{7-4} = R3; 286 let Inst{3-0} = R2; 287} 288 289class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 290 : InstSystemZ<4, outs, ins, asmstr, pattern> { 291 field bits<32> Inst; 292 field bits<32> SoftFail = 0; 293 294 bits<4> R1; 295 bits<4> R2; 296 297 let Inst{31-16} = op; 298 let Inst{15-8} = 0; 299 let Inst{7-4} = R1; 300 let Inst{3-0} = R2; 301} 302 303class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 304 : InstSystemZ<4, outs, ins, asmstr, pattern> { 305 field bits<32> Inst; 306 field bits<32> SoftFail = 0; 307 308 bits<4> R1; 309 bits<4> R2; 310 bits<4> R3; 311 bits<4> R4; 312 313 let Inst{31-16} = op; 314 let Inst{15-12} = R3; 315 let Inst{11-8} = R4; 316 let Inst{7-4} = R1; 317 let Inst{3-0} = R2; 318} 319 320class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 321 : InstSystemZ<4, outs, ins, asmstr, pattern> { 322 field bits<32> Inst; 323 field bits<32> SoftFail = 0; 324 325 bits<4> R1; 326 bits<20> XBD2; 327 328 let Inst{31-24} = op; 329 let Inst{23-20} = R1; 330 let Inst{19-0} = XBD2; 331 332 let HasIndex = 1; 333} 334 335class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 336 : InstSystemZ<6, outs, ins, asmstr, pattern> { 337 field bits<48> Inst; 338 field bits<48> SoftFail = 0; 339 340 bits<4> R1; 341 bits<20> XBD2; 342 343 let Inst{47-40} = op{15-8}; 344 let Inst{39-36} = R1; 345 let Inst{35-16} = XBD2; 346 let Inst{15-8} = 0; 347 let Inst{7-0} = op{7-0}; 348 349 let HasIndex = 1; 350} 351 352class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 353 : InstSystemZ<6, outs, ins, asmstr, pattern> { 354 field bits<48> Inst; 355 field bits<48> SoftFail = 0; 356 357 bits<4> R1; 358 bits<4> R3; 359 bits<20> XBD2; 360 361 let Inst{47-40} = op{15-8}; 362 let Inst{39-36} = R3; 363 let Inst{35-16} = XBD2; 364 let Inst{15-12} = R1; 365 let Inst{11-8} = 0; 366 let Inst{7-0} = op{7-0}; 367 368 let HasIndex = 1; 369} 370 371class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 372 : InstSystemZ<6, outs, ins, asmstr, pattern> { 373 field bits<48> Inst; 374 field bits<48> SoftFail = 0; 375 376 bits<4> R1; 377 bits<28> XBD2; 378 379 let Inst{47-40} = op{15-8}; 380 let Inst{39-36} = R1; 381 let Inst{35-8} = XBD2; 382 let Inst{7-0} = op{7-0}; 383 384 let Has20BitOffset = 1; 385 let HasIndex = 1; 386} 387 388class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 389 : InstSystemZ<4, outs, ins, asmstr, pattern> { 390 field bits<32> Inst; 391 field bits<32> SoftFail = 0; 392 393 bits<4> R1; 394 bits<4> R3; 395 bits<16> BD2; 396 397 let Inst{31-24} = op; 398 let Inst{23-20} = R1; 399 let Inst{19-16} = R3; 400 let Inst{15-0} = BD2; 401} 402 403class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 404 : InstSystemZ<6, outs, ins, asmstr, pattern> { 405 field bits<48> Inst; 406 field bits<48> SoftFail = 0; 407 408 bits<4> R1; 409 bits<4> R3; 410 bits<24> BD2; 411 412 let Inst{47-40} = op{15-8}; 413 let Inst{39-36} = R1; 414 let Inst{35-32} = R3; 415 let Inst{31-8} = BD2; 416 let Inst{7-0} = op{7-0}; 417 418 let Has20BitOffset = 1; 419} 420 421class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 422 : InstSystemZ<4, outs, ins, asmstr, pattern> { 423 field bits<32> Inst; 424 field bits<32> SoftFail = 0; 425 426 bits<16> BD1; 427 bits<8> I2; 428 429 let Inst{31-24} = op; 430 let Inst{23-16} = I2; 431 let Inst{15-0} = BD1; 432} 433 434class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 435 : InstSystemZ<6, outs, ins, asmstr, pattern> { 436 field bits<48> Inst; 437 field bits<48> SoftFail = 0; 438 439 bits<16> BD1; 440 bits<16> I2; 441 442 let Inst{47-32} = op; 443 let Inst{31-16} = BD1; 444 let Inst{15-0} = I2; 445} 446 447class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 448 : InstSystemZ<6, outs, ins, asmstr, pattern> { 449 field bits<48> Inst; 450 field bits<48> SoftFail = 0; 451 452 bits<24> BD1; 453 bits<8> I2; 454 455 let Inst{47-40} = op{15-8}; 456 let Inst{39-32} = I2; 457 let Inst{31-8} = BD1; 458 let Inst{7-0} = op{7-0}; 459 460 let Has20BitOffset = 1; 461} 462 463class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 464 : InstSystemZ<6, outs, ins, asmstr, pattern> { 465 field bits<48> Inst; 466 field bits<48> SoftFail = 0; 467 468 bits<24> BDL1; 469 bits<16> BD2; 470 471 let Inst{47-40} = op; 472 let Inst{39-16} = BDL1; 473 let Inst{15-0} = BD2; 474} 475 476//===----------------------------------------------------------------------===// 477// Instruction definitions with semantics 478//===----------------------------------------------------------------------===// 479// 480// These classes have the form [Cond]<Category><Format>, where <Format> is one 481// of the formats defined above and where <Category> describes the inputs 482// and outputs. "Cond" is used if the instruction is conditional, 483// in which case the 4-bit condition-code mask is added as a final operand. 484// <Category> can be one of: 485// 486// Inherent: 487// One register output operand and no input operands. 488// 489// BranchUnary: 490// One register output operand, one register input operand and 491// one branch displacement. The instructions stores a modified 492// form of the source register in the destination register and 493// branches on the result. 494// 495// Store: 496// One register or immediate input operand and one address input operand. 497// The instruction stores the first operand to the address. 498// 499// This category is used for both pure and truncating stores. 500// 501// LoadMultiple: 502// One address input operand and two explicit output operands. 503// The instruction loads a range of registers from the address, 504// with the explicit operands giving the first and last register 505// to load. Other loaded registers are added as implicit definitions. 506// 507// StoreMultiple: 508// Two explicit input register operands and an address operand. 509// The instruction stores a range of registers to the address, 510// with the explicit operands giving the first and last register 511// to store. Other stored registers are added as implicit uses. 512// 513// Unary: 514// One register output operand and one input operand. The input 515// operand may be a register, immediate or memory. 516// 517// Binary: 518// One register output operand and two input operands. The first 519// input operand is always a register and he second may be a register, 520// immediate or memory. 521// 522// Shift: 523// One register output operand and two input operands. The first 524// input operand is a register and the second has the same form as 525// an address (although it isn't actually used to address memory). 526// 527// Compare: 528// Two input operands. The first operand is always a register, 529// the second may be a register, immediate or memory. 530// 531// Ternary: 532// One register output operand and three register input operands. 533// 534// CmpSwap: 535// One output operand and three input operands. The first two 536// operands are registers and the third is an address. The instruction 537// both reads from and writes to the address. 538// 539// RotateSelect: 540// One output operand and five input operands. The first two operands 541// are registers and the other three are immediates. 542// 543// The format determines which input operands are tied to output operands, 544// and also determines the shape of any address operand. 545// 546// Multiclasses of the form <Category><Format>Pair define two instructions, 547// one with <Category><Format> and one with <Category><Format>Y. The name 548// of the first instruction has no suffix, the name of the second has 549// an extra "y". 550// 551//===----------------------------------------------------------------------===// 552 553class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 554 dag src> 555 : InstRRE<opcode, (outs cls:$R1), (ins), 556 mnemonic#"\t$R1", 557 [(set cls:$R1, src)]> { 558 let R2 = 0; 559} 560 561class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> 562 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2), 563 mnemonic##"\t$R1, $I2", []> { 564 let isBranch = 1; 565 let isTerminator = 1; 566 let Constraints = "$R1 = $R1src"; 567 let DisableEncoding = "$R1src"; 568} 569 570class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 571 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2), 572 mnemonic#"\t$R1, $R3, $BD2", []> { 573 let mayLoad = 1; 574} 575 576class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 577 RegisterOperand cls> 578 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 579 mnemonic#"\t$R1, $I2", 580 [(operator cls:$R1, pcrel32:$I2)]> { 581 let mayStore = 1; 582 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 583 // However, BDXs have two extra operands and are therefore 6 units more 584 // complex. 585 let AddedComplexity = 7; 586} 587 588class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 589 RegisterOperand cls, bits<5> bytes, 590 AddressingMode mode = bdxaddr12only> 591 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 592 mnemonic#"\t$R1, $XBD2", 593 [(operator cls:$R1, mode:$XBD2)]> { 594 let OpKey = mnemonic ## cls; 595 let OpType = "mem"; 596 let mayStore = 1; 597 let AccessBytes = bytes; 598} 599 600class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 601 RegisterOperand cls, bits<5> bytes, 602 AddressingMode mode = bdxaddr20only> 603 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 604 mnemonic#"\t$R1, $XBD2", 605 [(operator cls:$R1, mode:$XBD2)]> { 606 let OpKey = mnemonic ## cls; 607 let OpType = "mem"; 608 let mayStore = 1; 609 let AccessBytes = bytes; 610} 611 612multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 613 SDPatternOperator operator, RegisterOperand cls, 614 bits<5> bytes> { 615 let DispKey = mnemonic ## #cls in { 616 let DispSize = "12" in 617 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 618 let DispSize = "20" in 619 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 620 bdxaddr20pair>; 621 } 622} 623 624class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 625 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2), 626 mnemonic#"\t$R1, $R3, $BD2", []> { 627 let mayStore = 1; 628} 629 630class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 631 Immediate imm, AddressingMode mode = bdaddr12only> 632 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 633 mnemonic#"\t$BD1, $I2", 634 [(operator imm:$I2, mode:$BD1)]> { 635 let mayStore = 1; 636} 637 638class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 639 Immediate imm, AddressingMode mode = bdaddr20only> 640 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 641 mnemonic#"\t$BD1, $I2", 642 [(operator imm:$I2, mode:$BD1)]> { 643 let mayStore = 1; 644} 645 646class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 647 Immediate imm> 648 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 649 mnemonic#"\t$BD1, $I2", 650 [(operator imm:$I2, bdaddr12only:$BD1)]> { 651 let mayStore = 1; 652} 653 654multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 655 SDPatternOperator operator, Immediate imm> { 656 let DispKey = mnemonic in { 657 let DispSize = "12" in 658 def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 659 let DispSize = "20" in 660 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 661 } 662} 663 664class CondStoreRSY<string mnemonic, bits<16> opcode, 665 RegisterOperand cls, bits<5> bytes, 666 AddressingMode mode = bdaddr20only> 667 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), 668 mnemonic#"$R3\t$R1, $BD2", []>, 669 Requires<[FeatureLoadStoreOnCond]> { 670 let mayStore = 1; 671 let AccessBytes = bytes; 672 let CCMaskLast = 1; 673} 674 675// Like CondStoreRSY, but used for the raw assembly form. The condition-code 676// mask is the third operand rather than being part of the mnemonic. 677class AsmCondStoreRSY<string mnemonic, bits<16> opcode, 678 RegisterOperand cls, bits<5> bytes, 679 AddressingMode mode = bdaddr20only> 680 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, uimm8zx4:$R3), 681 mnemonic#"\t$R1, $BD2, $R3", []>, 682 Requires<[FeatureLoadStoreOnCond]> { 683 let mayStore = 1; 684 let AccessBytes = bytes; 685} 686 687// Like CondStoreRSY, but with a fixed CC mask. 688class FixedCondStoreRSY<string mnemonic, bits<16> opcode, 689 RegisterOperand cls, bits<4> ccmask, bits<5> bytes, 690 AddressingMode mode = bdaddr20only> 691 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2), 692 mnemonic#"\t$R1, $BD2", []>, 693 Requires<[FeatureLoadStoreOnCond]> { 694 let mayStore = 1; 695 let AccessBytes = bytes; 696 let R3 = ccmask; 697} 698 699class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 700 RegisterOperand cls1, RegisterOperand cls2> 701 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 702 mnemonic#"r\t$R1, $R2", 703 [(set cls1:$R1, (operator cls2:$R2))]> { 704 let OpKey = mnemonic ## cls1; 705 let OpType = "reg"; 706} 707 708class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 709 RegisterOperand cls1, RegisterOperand cls2> 710 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 711 mnemonic#"r\t$R1, $R2", 712 [(set cls1:$R1, (operator cls2:$R2))]> { 713 let OpKey = mnemonic ## cls1; 714 let OpType = "reg"; 715} 716 717class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 718 RegisterOperand cls2> 719 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2), 720 mnemonic#"r\t$R1, $R3, $R2", []> { 721 let OpKey = mnemonic ## cls1; 722 let OpType = "reg"; 723 let R4 = 0; 724} 725 726class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1, 727 RegisterOperand cls2> 728 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2, uimm8zx4:$R4), 729 mnemonic#"\t$R1, $R3, $R2, $R4", []>; 730 731// These instructions are generated by if conversion. The old value of R1 732// is added as an implicit use. 733class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 734 RegisterOperand cls2> 735 : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3), 736 mnemonic#"r$R3\t$R1, $R2", []>, 737 Requires<[FeatureLoadStoreOnCond]> { 738 let CCMaskLast = 1; 739 let R4 = 0; 740} 741 742// Like CondUnaryRRF, but used for the raw assembly form. The condition-code 743// mask is the third operand rather than being part of the mnemonic. 744class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 745 RegisterOperand cls2> 746 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, uimm8zx4:$R3), 747 mnemonic#"r\t$R1, $R2, $R3", []>, 748 Requires<[FeatureLoadStoreOnCond]> { 749 let Constraints = "$R1 = $R1src"; 750 let DisableEncoding = "$R1src"; 751 let R4 = 0; 752} 753 754// Like CondUnaryRRF, but with a fixed CC mask. 755class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 756 RegisterOperand cls2, bits<4> ccmask> 757 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 758 mnemonic#"\t$R1, $R2", []>, 759 Requires<[FeatureLoadStoreOnCond]> { 760 let Constraints = "$R1 = $R1src"; 761 let DisableEncoding = "$R1src"; 762 let R3 = ccmask; 763 let R4 = 0; 764} 765 766class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 767 RegisterOperand cls, Immediate imm> 768 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2), 769 mnemonic#"\t$R1, $I2", 770 [(set cls:$R1, (operator imm:$I2))]>; 771 772class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 773 RegisterOperand cls, Immediate imm> 774 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2), 775 mnemonic#"\t$R1, $I2", 776 [(set cls:$R1, (operator imm:$I2))]>; 777 778class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 779 RegisterOperand cls> 780 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2), 781 mnemonic#"\t$R1, $I2", 782 [(set cls:$R1, (operator pcrel32:$I2))]> { 783 let mayLoad = 1; 784 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 785 // However, BDXs have two extra operands and are therefore 6 units more 786 // complex. 787 let AddedComplexity = 7; 788} 789 790class CondUnaryRSY<string mnemonic, bits<16> opcode, 791 SDPatternOperator operator, RegisterOperand cls, 792 bits<5> bytes, AddressingMode mode = bdaddr20only> 793 : InstRSY<opcode, (outs cls:$R1), 794 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3), 795 mnemonic#"$R3\t$R1, $BD2", 796 [(set cls:$R1, 797 (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src, 798 cond4:$valid, cond4:$R3))]>, 799 Requires<[FeatureLoadStoreOnCond]> { 800 let Constraints = "$R1 = $R1src"; 801 let DisableEncoding = "$R1src"; 802 let mayLoad = 1; 803 let AccessBytes = bytes; 804 let CCMaskLast = 1; 805} 806 807// Like CondUnaryRSY, but used for the raw assembly form. The condition-code 808// mask is the third operand rather than being part of the mnemonic. 809class AsmCondUnaryRSY<string mnemonic, bits<16> opcode, 810 RegisterOperand cls, bits<5> bytes, 811 AddressingMode mode = bdaddr20only> 812 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, uimm8zx4:$R3), 813 mnemonic#"\t$R1, $BD2, $R3", []>, 814 Requires<[FeatureLoadStoreOnCond]> { 815 let mayLoad = 1; 816 let AccessBytes = bytes; 817 let Constraints = "$R1 = $R1src"; 818 let DisableEncoding = "$R1src"; 819} 820 821// Like CondUnaryRSY, but with a fixed CC mask. 822class FixedCondUnaryRSY<string mnemonic, bits<16> opcode, 823 RegisterOperand cls, bits<4> ccmask, bits<5> bytes, 824 AddressingMode mode = bdaddr20only> 825 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2), 826 mnemonic#"\t$R1, $BD2", []>, 827 Requires<[FeatureLoadStoreOnCond]> { 828 let Constraints = "$R1 = $R1src"; 829 let DisableEncoding = "$R1src"; 830 let R3 = ccmask; 831 let mayLoad = 1; 832 let AccessBytes = bytes; 833} 834 835class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 836 RegisterOperand cls, bits<5> bytes, 837 AddressingMode mode = bdxaddr12only> 838 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2), 839 mnemonic#"\t$R1, $XBD2", 840 [(set cls:$R1, (operator mode:$XBD2))]> { 841 let OpKey = mnemonic ## cls; 842 let OpType = "mem"; 843 let mayLoad = 1; 844 let AccessBytes = bytes; 845} 846 847class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 848 RegisterOperand cls, bits<5> bytes> 849 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2), 850 mnemonic#"\t$R1, $XBD2", 851 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 852 let OpKey = mnemonic ## cls; 853 let OpType = "mem"; 854 let mayLoad = 1; 855 let AccessBytes = bytes; 856} 857 858class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 859 RegisterOperand cls, bits<5> bytes, 860 AddressingMode mode = bdxaddr20only> 861 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2), 862 mnemonic#"\t$R1, $XBD2", 863 [(set cls:$R1, (operator mode:$XBD2))]> { 864 let OpKey = mnemonic ## cls; 865 let OpType = "mem"; 866 let mayLoad = 1; 867 let AccessBytes = bytes; 868} 869 870multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 871 SDPatternOperator operator, RegisterOperand cls, 872 bits<5> bytes> { 873 let DispKey = mnemonic ## #cls in { 874 let DispSize = "12" in 875 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 876 let DispSize = "20" in 877 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 878 bdxaddr20pair>; 879 } 880} 881 882class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 883 RegisterOperand cls1, RegisterOperand cls2> 884 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 885 mnemonic#"r\t$R1, $R2", 886 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 887 let OpKey = mnemonic ## cls1; 888 let OpType = "reg"; 889 let Constraints = "$R1 = $R1src"; 890 let DisableEncoding = "$R1src"; 891} 892 893class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 894 RegisterOperand cls1, RegisterOperand cls2> 895 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 896 mnemonic#"r\t$R1, $R2", 897 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 898 let OpKey = mnemonic ## cls1; 899 let OpType = "reg"; 900 let Constraints = "$R1 = $R1src"; 901 let DisableEncoding = "$R1src"; 902} 903 904class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 905 RegisterOperand cls1, RegisterOperand cls2> 906 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2), 907 mnemonic#"r\t$R1, $R3, $R2", 908 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> { 909 let OpKey = mnemonic ## cls1; 910 let OpType = "reg"; 911 let R4 = 0; 912} 913 914class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator, 915 RegisterOperand cls1, RegisterOperand cls2> 916 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3), 917 mnemonic#"rk\t$R1, $R2, $R3", 918 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> { 919 let R4 = 0; 920} 921 922multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 923 SDPatternOperator operator, RegisterOperand cls1, 924 RegisterOperand cls2> { 925 let NumOpsKey = mnemonic in { 926 let NumOpsValue = "3" in 927 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>, 928 Requires<[FeatureDistinctOps]>; 929 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 930 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>; 931 } 932} 933 934multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2, 935 SDPatternOperator operator, RegisterOperand cls1, 936 RegisterOperand cls2> { 937 let NumOpsKey = mnemonic in { 938 let NumOpsValue = "3" in 939 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>, 940 Requires<[FeatureDistinctOps]>; 941 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 942 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>; 943 } 944} 945 946class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 947 RegisterOperand cls, Immediate imm> 948 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 949 mnemonic#"\t$R1, $I2", 950 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 951 let Constraints = "$R1 = $R1src"; 952 let DisableEncoding = "$R1src"; 953} 954 955class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 956 RegisterOperand cls, Immediate imm> 957 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), 958 mnemonic#"\t$R1, $R3, $I2", 959 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 960 961multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, 962 SDPatternOperator operator, RegisterOperand cls, 963 Immediate imm> { 964 let NumOpsKey = mnemonic in { 965 let NumOpsValue = "3" in 966 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>, 967 Requires<[FeatureDistinctOps]>; 968 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 969 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; 970 } 971} 972 973class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 974 RegisterOperand cls, Immediate imm> 975 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 976 mnemonic#"\t$R1, $I2", 977 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 978 let Constraints = "$R1 = $R1src"; 979 let DisableEncoding = "$R1src"; 980} 981 982class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 983 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 984 AddressingMode mode = bdxaddr12only> 985 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 986 mnemonic#"\t$R1, $XBD2", 987 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 988 let OpKey = mnemonic ## cls; 989 let OpType = "mem"; 990 let Constraints = "$R1 = $R1src"; 991 let DisableEncoding = "$R1src"; 992 let mayLoad = 1; 993 let AccessBytes = bytes; 994} 995 996class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 997 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 998 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2), 999 mnemonic#"\t$R1, $XBD2", 1000 [(set cls:$R1, (operator cls:$R1src, 1001 (load bdxaddr12only:$XBD2)))]> { 1002 let OpKey = mnemonic ## cls; 1003 let OpType = "mem"; 1004 let Constraints = "$R1 = $R1src"; 1005 let DisableEncoding = "$R1src"; 1006 let mayLoad = 1; 1007 let AccessBytes = bytes; 1008} 1009 1010class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1011 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1012 AddressingMode mode = bdxaddr20only> 1013 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 1014 mnemonic#"\t$R1, $XBD2", 1015 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 1016 let OpKey = mnemonic ## cls; 1017 let OpType = "mem"; 1018 let Constraints = "$R1 = $R1src"; 1019 let DisableEncoding = "$R1src"; 1020 let mayLoad = 1; 1021 let AccessBytes = bytes; 1022} 1023 1024multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1025 SDPatternOperator operator, RegisterOperand cls, 1026 SDPatternOperator load, bits<5> bytes> { 1027 let DispKey = mnemonic ## #cls in { 1028 let DispSize = "12" in 1029 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 1030 bdxaddr12pair>; 1031 let DispSize = "20" in 1032 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes, 1033 bdxaddr20pair>; 1034 } 1035} 1036 1037class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1038 Operand imm, AddressingMode mode = bdaddr12only> 1039 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 1040 mnemonic#"\t$BD1, $I2", 1041 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 1042 let mayLoad = 1; 1043 let mayStore = 1; 1044} 1045 1046class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1047 Operand imm, AddressingMode mode = bdaddr20only> 1048 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 1049 mnemonic#"\t$BD1, $I2", 1050 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 1051 let mayLoad = 1; 1052 let mayStore = 1; 1053} 1054 1055multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 1056 bits<16> siyOpcode, SDPatternOperator operator, 1057 Operand imm> { 1058 let DispKey = mnemonic ## #cls in { 1059 let DispSize = "12" in 1060 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 1061 let DispSize = "20" in 1062 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 1063 } 1064} 1065 1066class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1067 RegisterOperand cls> 1068 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2), 1069 mnemonic#"\t$R1, $BD2", 1070 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> { 1071 let R3 = 0; 1072 let Constraints = "$R1 = $R1src"; 1073 let DisableEncoding = "$R1src"; 1074} 1075 1076class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1077 RegisterOperand cls> 1078 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2), 1079 mnemonic#"\t$R1, $R3, $BD2", 1080 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>; 1081 1082multiclass ShiftRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 1083 SDPatternOperator operator, RegisterOperand cls> { 1084 let NumOpsKey = mnemonic in { 1085 let NumOpsValue = "3" in 1086 def K : ShiftRSY<mnemonic##"k", opcode2, null_frag, cls>, 1087 Requires<[FeatureDistinctOps]>; 1088 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1089 def "" : ShiftRS<mnemonic, opcode1, operator, cls>; 1090 } 1091} 1092 1093class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1094 RegisterOperand cls1, RegisterOperand cls2> 1095 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 1096 mnemonic#"r\t$R1, $R2", 1097 [(operator cls1:$R1, cls2:$R2)]> { 1098 let OpKey = mnemonic ## cls1; 1099 let OpType = "reg"; 1100 let isCompare = 1; 1101} 1102 1103class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1104 RegisterOperand cls1, RegisterOperand cls2> 1105 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 1106 mnemonic#"r\t$R1, $R2", 1107 [(operator cls1:$R1, cls2:$R2)]> { 1108 let OpKey = mnemonic ## cls1; 1109 let OpType = "reg"; 1110 let isCompare = 1; 1111} 1112 1113class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1114 RegisterOperand cls, Immediate imm> 1115 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2), 1116 mnemonic#"\t$R1, $I2", 1117 [(operator cls:$R1, imm:$I2)]> { 1118 let isCompare = 1; 1119} 1120 1121class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1122 RegisterOperand cls, Immediate imm> 1123 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2), 1124 mnemonic#"\t$R1, $I2", 1125 [(operator cls:$R1, imm:$I2)]> { 1126 let isCompare = 1; 1127} 1128 1129class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1130 RegisterOperand cls, SDPatternOperator load> 1131 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 1132 mnemonic#"\t$R1, $I2", 1133 [(operator cls:$R1, (load pcrel32:$I2))]> { 1134 let isCompare = 1; 1135 let mayLoad = 1; 1136 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 1137 // However, BDXs have two extra operands and are therefore 6 units more 1138 // complex. 1139 let AddedComplexity = 7; 1140} 1141 1142class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1143 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1144 AddressingMode mode = bdxaddr12only> 1145 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1146 mnemonic#"\t$R1, $XBD2", 1147 [(operator cls:$R1, (load mode:$XBD2))]> { 1148 let OpKey = mnemonic ## cls; 1149 let OpType = "mem"; 1150 let isCompare = 1; 1151 let mayLoad = 1; 1152 let AccessBytes = bytes; 1153} 1154 1155class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1156 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1157 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 1158 mnemonic#"\t$R1, $XBD2", 1159 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> { 1160 let OpKey = mnemonic ## cls; 1161 let OpType = "mem"; 1162 let isCompare = 1; 1163 let mayLoad = 1; 1164 let AccessBytes = bytes; 1165} 1166 1167class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1168 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1169 AddressingMode mode = bdxaddr20only> 1170 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1171 mnemonic#"\t$R1, $XBD2", 1172 [(operator cls:$R1, (load mode:$XBD2))]> { 1173 let OpKey = mnemonic ## cls; 1174 let OpType = "mem"; 1175 let isCompare = 1; 1176 let mayLoad = 1; 1177 let AccessBytes = bytes; 1178} 1179 1180multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1181 SDPatternOperator operator, RegisterOperand cls, 1182 SDPatternOperator load, bits<5> bytes> { 1183 let DispKey = mnemonic ## #cls in { 1184 let DispSize = "12" in 1185 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 1186 load, bytes, bdxaddr12pair>; 1187 let DispSize = "20" in 1188 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 1189 load, bytes, bdxaddr20pair>; 1190 } 1191} 1192 1193class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1194 SDPatternOperator load, Immediate imm, 1195 AddressingMode mode = bdaddr12only> 1196 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 1197 mnemonic#"\t$BD1, $I2", 1198 [(operator (load mode:$BD1), imm:$I2)]> { 1199 let isCompare = 1; 1200 let mayLoad = 1; 1201} 1202 1203class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1204 SDPatternOperator load, Immediate imm> 1205 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 1206 mnemonic#"\t$BD1, $I2", 1207 [(operator (load bdaddr12only:$BD1), imm:$I2)]> { 1208 let isCompare = 1; 1209 let mayLoad = 1; 1210} 1211 1212class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1213 SDPatternOperator load, Immediate imm, 1214 AddressingMode mode = bdaddr20only> 1215 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 1216 mnemonic#"\t$BD1, $I2", 1217 [(operator (load mode:$BD1), imm:$I2)]> { 1218 let isCompare = 1; 1219 let mayLoad = 1; 1220} 1221 1222multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 1223 SDPatternOperator operator, SDPatternOperator load, 1224 Immediate imm> { 1225 let DispKey = mnemonic in { 1226 let DispSize = "12" in 1227 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 1228 let DispSize = "20" in 1229 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 1230 bdaddr20pair>; 1231 } 1232} 1233 1234class TernaryRRD<string mnemonic, bits<16> opcode, 1235 SDPatternOperator operator, RegisterOperand cls> 1236 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2), 1237 mnemonic#"r\t$R1, $R3, $R2", 1238 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> { 1239 let OpKey = mnemonic ## cls; 1240 let OpType = "reg"; 1241 let Constraints = "$R1 = $R1src"; 1242 let DisableEncoding = "$R1src"; 1243} 1244 1245class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1246 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1247 : InstRXF<opcode, (outs cls:$R1), 1248 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2), 1249 mnemonic#"\t$R1, $R3, $XBD2", 1250 [(set cls:$R1, (operator cls:$R1src, cls:$R3, 1251 (load bdxaddr12only:$XBD2)))]> { 1252 let OpKey = mnemonic ## cls; 1253 let OpType = "mem"; 1254 let Constraints = "$R1 = $R1src"; 1255 let DisableEncoding = "$R1src"; 1256 let mayLoad = 1; 1257 let AccessBytes = bytes; 1258} 1259 1260class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1261 RegisterOperand cls, AddressingMode mode = bdaddr12only> 1262 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 1263 mnemonic#"\t$R1, $R3, $BD2", 1264 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 1265 let Constraints = "$R1 = $R1src"; 1266 let DisableEncoding = "$R1src"; 1267 let mayLoad = 1; 1268 let mayStore = 1; 1269} 1270 1271class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1272 RegisterOperand cls, AddressingMode mode = bdaddr20only> 1273 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 1274 mnemonic#"\t$R1, $R3, $BD2", 1275 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 1276 let Constraints = "$R1 = $R1src"; 1277 let DisableEncoding = "$R1src"; 1278 let mayLoad = 1; 1279 let mayStore = 1; 1280} 1281 1282multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 1283 SDPatternOperator operator, RegisterOperand cls> { 1284 let DispKey = mnemonic ## #cls in { 1285 let DispSize = "12" in 1286 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 1287 let DispSize = "20" in 1288 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 1289 } 1290} 1291 1292class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1293 RegisterOperand cls2> 1294 : InstRIEf<opcode, (outs cls1:$R1), 1295 (ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5), 1296 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> { 1297 let Constraints = "$R1 = $R1src"; 1298 let DisableEncoding = "$R1src"; 1299} 1300 1301// A floating-point load-and test operation. Create both a normal unary 1302// operation and one that acts as a comparison against zero. 1303multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode, 1304 RegisterOperand cls> { 1305 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>; 1306 let isCodeGenOnly = 1 in 1307 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>; 1308} 1309 1310//===----------------------------------------------------------------------===// 1311// Pseudo instructions 1312//===----------------------------------------------------------------------===// 1313// 1314// Convenience instructions that get lowered to real instructions 1315// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 1316// or SystemZInstrInfo::expandPostRAPseudo(). 1317// 1318//===----------------------------------------------------------------------===// 1319 1320class Pseudo<dag outs, dag ins, list<dag> pattern> 1321 : InstSystemZ<0, outs, ins, "", pattern> { 1322 let isPseudo = 1; 1323 let isCodeGenOnly = 1; 1324} 1325 1326// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 1327// the value of the PSW's 2-bit condition code field. 1328class SelectWrapper<RegisterOperand cls> 1329 : Pseudo<(outs cls:$dst), 1330 (ins cls:$src1, cls:$src2, uimm8zx4:$valid, uimm8zx4:$cc), 1331 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, 1332 uimm8zx4:$valid, uimm8zx4:$cc))]> { 1333 let usesCustomInserter = 1; 1334 // Although the instructions used by these nodes do not in themselves 1335 // change CC, the insertion requires new blocks, and CC cannot be live 1336 // across them. 1337 let Defs = [CC]; 1338 let Uses = [CC]; 1339} 1340 1341// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 1342multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 1343 SDPatternOperator load, AddressingMode mode> { 1344 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in { 1345 def "" : Pseudo<(outs), 1346 (ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc), 1347 [(store (z_select_ccmask cls:$new, (load mode:$addr), 1348 uimm8zx4:$valid, uimm8zx4:$cc), 1349 mode:$addr)]>; 1350 def Inv : Pseudo<(outs), 1351 (ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc), 1352 [(store (z_select_ccmask (load mode:$addr), cls:$new, 1353 uimm8zx4:$valid, uimm8zx4:$cc), 1354 mode:$addr)]>; 1355 } 1356} 1357 1358// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND 1359// describe the second (non-memory) operand. 1360class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls, 1361 dag pat, DAGOperand operand> 1362 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2), 1363 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> { 1364 let Defs = [CC]; 1365 let Has20BitOffset = 1; 1366 let mayLoad = 1; 1367 let mayStore = 1; 1368 let usesCustomInserter = 1; 1369} 1370 1371// Specializations of AtomicLoadWBinary. 1372class AtomicLoadBinaryReg32<SDPatternOperator operator> 1373 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>; 1374class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm> 1375 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>; 1376class AtomicLoadBinaryReg64<SDPatternOperator operator> 1377 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>; 1378class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm> 1379 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>; 1380 1381// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 1382// describe the second (non-memory) operand. 1383class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 1384 DAGOperand operand> 1385 : Pseudo<(outs GR32:$dst), 1386 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 1387 ADDR32:$negbitshift, uimm32:$bitsize), 1388 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 1389 ADDR32:$negbitshift, uimm32:$bitsize))]> { 1390 let Defs = [CC]; 1391 let Has20BitOffset = 1; 1392 let mayLoad = 1; 1393 let mayStore = 1; 1394 let usesCustomInserter = 1; 1395} 1396 1397// Specializations of AtomicLoadWBinary. 1398class AtomicLoadWBinaryReg<SDPatternOperator operator> 1399 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 1400class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm> 1401 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 1402 1403// Define an instruction that operates on two fixed-length blocks of memory. 1404// The real instruction uses a bdladdr12onlylen8 for the first operand and a 1405// bdaddr12only for the second, with the length of the second operand being 1406// implicitly the same as the first. This arrangement matches the underlying 1407// assembly syntax. However, for instruction selection it's easier to have 1408// two normal bdaddr12onlys and a separate length operand, so define a pseudo 1409// instruction for that too. 1410multiclass MemorySS<string mnemonic, bits<8> opcode, 1411 SDPatternOperator operator> { 1412 def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, 1413 bdaddr12only:$BD2), 1414 mnemonic##"\t$BDL1, $BD2", []>; 1415 let usesCustomInserter = 1 in 1416 def Wrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 1417 imm32len8:$length), 1418 [(operator bdaddr12only:$dest, bdaddr12only:$src, 1419 imm32len8:$length)]>; 1420} 1421 1422// Define an instruction that operates on two strings, both terminated 1423// by the character in R0. The instruction processes a CPU-determinated 1424// number of bytes at a time and sets CC to 3 if the instruction needs 1425// to be repeated. Also define a pseudo instruction that represents 1426// the full loop (the main instruction plus the branch on CC==3). 1427multiclass StringRRE<string mnemonic, bits<16> opcode, 1428 SDPatternOperator operator> { 1429 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2), 1430 (ins GR64:$R1src, GR64:$R2src), 1431 mnemonic#"\t$R1, $R2", []> { 1432 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 1433 let DisableEncoding = "$R1src, $R2src"; 1434 } 1435 let usesCustomInserter = 1 in 1436 def Loop : Pseudo<(outs GR64:$end), 1437 (ins GR64:$start1, GR64:$start2, GR32:$char), 1438 [(set GR64:$end, (operator GR64:$start1, GR64:$start2, 1439 GR32:$char))]>; 1440} 1441