SystemZInstrInfo.td revision 0ba60d96588e8491c0ae0367d152d1c274986793
1//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SystemZ instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// SystemZ Instruction Predicate Definitions. 16def IsZ10 : Predicate<"Subtarget.isZ10()">; 17 18include "SystemZInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Type Constraints. 22//===----------------------------------------------------------------------===// 23class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 24class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 25class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>; 26class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>; 27 28//===----------------------------------------------------------------------===// 29// Type Profiles. 30//===----------------------------------------------------------------------===// 31def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 32def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>; 33def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>; 34def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 35def SDT_BrCond : SDTypeProfile<0, 2, 36 [SDTCisVT<0, OtherVT>, 37 SDTCisI8<1>]>; 38def SDT_SelectCC : SDTypeProfile<1, 3, 39 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 40 SDTCisI8<3>]>; 41def SDT_Address : SDTypeProfile<1, 1, 42 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 43 44//===----------------------------------------------------------------------===// 45// SystemZ Specific Node Definitions. 46//===----------------------------------------------------------------------===// 47def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 48 [SDNPHasChain, SDNPOptInFlag]>; 49def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall, 50 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; 51def SystemZcallseq_start : 52 SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart, 53 [SDNPHasChain, SDNPOutFlag]>; 54def SystemZcallseq_end : 55 SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd, 56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 57def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>; 58def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>; 59def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, 60 [SDNPHasChain, SDNPInFlag]>; 61def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>; 62def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>; 63 64 65include "SystemZOperands.td" 66 67//===----------------------------------------------------------------------===// 68// Instruction list.. 69 70def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 71 "#ADJCALLSTACKDOWN", 72 [(SystemZcallseq_start timm:$amt)]>; 73def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 74 "#ADJCALLSTACKUP", 75 [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>; 76 77let usesCustomDAGSchedInserter = 1 in { 78 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc), 79 "# Select32 PSEUDO", 80 [(set GR32:$dst, 81 (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>; 82 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc), 83 "# Select64 PSEUDO", 84 [(set GR64:$dst, 85 (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>; 86} 87 88 89//===----------------------------------------------------------------------===// 90// Control Flow Instructions... 91// 92 93// FIXME: Provide proper encoding! 94let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { 95 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>; 96} 97 98let isBranch = 1, isTerminator = 1 in { 99 let isBarrier = 1 in { 100 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>; 101 102 let isIndirectBranch = 1 in 103 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>; 104 } 105 106 let Uses = [PSW] in { 107 def JE : Pseudo<(outs), (ins brtarget:$dst), 108 "je\t$dst", 109 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>; 110 def JNE : Pseudo<(outs), (ins brtarget:$dst), 111 "jne\t$dst", 112 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>; 113 def JH : Pseudo<(outs), (ins brtarget:$dst), 114 "jh\t$dst", 115 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>; 116 def JL : Pseudo<(outs), (ins brtarget:$dst), 117 "jl\t$dst", 118 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>; 119 def JHE : Pseudo<(outs), (ins brtarget:$dst), 120 "jhe\t$dst", 121 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>; 122 def JLE : Pseudo<(outs), (ins brtarget:$dst), 123 "jle\t$dst", 124 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>; 125 126 } // Uses = [PSW] 127} // isBranch = 1 128 129//===----------------------------------------------------------------------===// 130// Call Instructions... 131// 132 133let isCall = 1 in 134 // All calls clobber the non-callee saved registers. Uses for argument 135 // registers are added manually. 136 let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D] in { 137 def CALLi : Pseudo<(outs), (ins i64imm:$dst, variable_ops), 138 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>; 139 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops), 140 "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>; 141 } 142 143//===----------------------------------------------------------------------===// 144// Miscellaneous Instructions. 145// 146 147let isReMaterializable = 1 in 148// FIXME: Provide imm12 variant 149// FIXME: Address should be halfword aligned... 150def LA64r : Pseudo<(outs GR64:$dst), (ins laaddr:$src), 151 "lay\t{$dst, $src}", 152 [(set GR64:$dst, laaddr:$src)]>; 153def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 154 "larl\t{$dst, $src}", 155 [(set GR64:$dst, 156 (SystemZpcrelwrapper tglobaladdr:$src))]>; 157 158let neverHasSideEffects = 1 in 159def NOP : Pseudo<(outs), (ins), "# no-op", []>; 160 161//===----------------------------------------------------------------------===// 162// Move Instructions 163 164// FIXME: Provide proper encoding! 165let neverHasSideEffects = 1 in { 166def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src), 167 "lr\t{$dst, $src}", 168 []>; 169def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src), 170 "lgr\t{$dst, $src}", 171 []>; 172def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src), 173 "# MOV128 PSEUDO!\n" 174 "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n" 175 "\tlgr\t${dst:subreg_even}, ${src:subreg_even}", 176 []>; 177def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src), 178 "# MOV64P PSEUDO!\n" 179 "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n" 180 "\tlr\t${dst:subreg_even}, ${src:subreg_even}", 181 []>; 182} 183 184def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 185 "lgfr\t{$dst, $src}", 186 [(set GR64:$dst, (sext GR32:$src))]>; 187def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 188 "llgfr\t{$dst, $src}", 189 [(set GR64:$dst, (zext GR32:$src))]>; 190 191// FIXME: Provide proper encoding! 192let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 193def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src), 194 "lhi\t{$dst, $src}", 195 [(set GR32:$dst, immSExt16:$src)]>; 196def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src), 197 "lghi\t{$dst, $src}", 198 [(set GR64:$dst, immSExt16:$src)]>; 199 200def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 201 "llill\t{$dst, $src}", 202 [(set GR64:$dst, i64ll16:$src)]>; 203def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 204 "llilh\t{$dst, $src}", 205 [(set GR64:$dst, i64lh16:$src)]>; 206def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 207 "llihl\t{$dst, $src}", 208 [(set GR64:$dst, i64hl16:$src)]>; 209def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 210 "llihh\t{$dst, $src}", 211 [(set GR64:$dst, i64hh16:$src)]>; 212 213def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src), 214 "lgfi\t{$dst, $src}", 215 [(set GR64:$dst, immSExt32:$src)]>; 216def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 217 "llilf\t{$dst, $src}", 218 [(set GR64:$dst, i64lo32:$src)]>; 219def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src), 220 "llihf\t{$dst, $src}", 221 [(set GR64:$dst, i64hi32:$src)]>; 222} 223 224let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { 225def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src), 226 "l\t{$dst, $src}", 227 [(set GR32:$dst, (load rriaddr12:$src))]>; 228def MOV32rmy : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 229 "ly\t{$dst, $src}", 230 [(set GR32:$dst, (load rriaddr:$src))]>; 231def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 232 "lg\t{$dst, $src}", 233 [(set GR64:$dst, (load rriaddr:$src))]>; 234 235} 236 237def MOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src), 238 "st\t{$src, $dst}", 239 [(store GR32:$src, rriaddr12:$dst)]>; 240def MOV32mry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 241 "sty\t{$src, $dst}", 242 [(store GR32:$src, rriaddr:$dst)]>; 243def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 244 "stg\t{$src, $dst}", 245 [(store GR64:$src, rriaddr:$dst)]>; 246 247def MOV8mi : Pseudo<(outs), (ins riaddr12:$dst, i32i8imm:$src), 248 "mvi\t{$dst, $src}", 249 [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>; 250def MOV8miy : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src), 251 "mviy\t{$dst, $src}", 252 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>; 253 254def MOV16mi : Pseudo<(outs), (ins riaddr12:$dst, s16imm:$src), 255 "mvhhi\t{$dst, $src}", 256 [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>, 257 Requires<[IsZ10]>; 258def MOV32mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm:$src), 259 "mvhi\t{$dst, $src}", 260 [(store (i32 immSExt16:$src), riaddr12:$dst)]>, 261 Requires<[IsZ10]>; 262def MOV64mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm64:$src), 263 "mvghi\t{$dst, $src}", 264 [(store (i64 immSExt16:$src), riaddr12:$dst)]>, 265 Requires<[IsZ10]>; 266 267// sexts 268def MOVSX32rr8 : Pseudo<(outs GR32:$dst), (ins GR32:$src), 269 "lbr\t{$dst, $src}", 270 [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>; 271def MOVSX64rr8 : Pseudo<(outs GR64:$dst), (ins GR64:$src), 272 "lgbr\t{$dst, $src}", 273 [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>; 274def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src), 275 "lhr\t{$dst, $src}", 276 [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>; 277def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src), 278 "lghr\t{$dst, $src}", 279 [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>; 280 281// extloads 282def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 283 "lb\t{$dst, $src}", 284 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>; 285def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src), 286 "lh\t{$dst, $src}", 287 [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>; 288def MOVSX32rm16y : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 289 "lhy\t{$dst, $src}", 290 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>; 291def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 292 "lgb\t{$dst, $src}", 293 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>; 294def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 295 "lgh\t{$dst, $src}", 296 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>; 297def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 298 "lgf\t{$dst, $src}", 299 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>; 300 301def MOVZX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 302 "llc\t{$dst, $src}", 303 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>; 304def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src), 305 "llh\t{$dst, $src}", 306 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>; 307def MOVZX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 308 "llgc\t{$dst, $src}", 309 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>; 310def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 311 "llgh\t{$dst, $src}", 312 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>; 313def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src), 314 "llgf\t{$dst, $src}", 315 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>; 316 317// truncstores 318def MOV32m8r : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src), 319 "stc\t{$src, $dst}", 320 [(truncstorei8 GR32:$src, rriaddr12:$dst)]>; 321 322def MOV32m8ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 323 "stcy\t{$src, $dst}", 324 [(truncstorei8 GR32:$src, rriaddr:$dst)]>; 325 326def MOV32m16r : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src), 327 "sth\t{$src, $dst}", 328 [(truncstorei16 GR32:$src, rriaddr12:$dst)]>; 329 330def MOV32m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src), 331 "sthy\t{$src, $dst}", 332 [(truncstorei16 GR32:$src, rriaddr:$dst)]>; 333 334def MOV64m8r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src), 335 "stc\t{$src, $dst}", 336 [(truncstorei8 GR64:$src, rriaddr12:$dst)]>; 337 338def MOV64m8ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 339 "stcy\t{$src, $dst}", 340 [(truncstorei8 GR64:$src, rriaddr:$dst)]>; 341 342def MOV64m16r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src), 343 "sth\t{$src, $dst}", 344 [(truncstorei16 GR64:$src, rriaddr12:$dst)]>; 345 346def MOV64m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 347 "sthy\t{$src, $dst}", 348 [(truncstorei16 GR64:$src, rriaddr:$dst)]>; 349 350def MOV64m32r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src), 351 "st\t{$src, $dst}", 352 [(truncstorei32 GR64:$src, rriaddr12:$dst)]>; 353 354def MOV64m32ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src), 355 "sty\t{$src, $dst}", 356 [(truncstorei32 GR64:$src, rriaddr:$dst)]>; 357 358// multiple regs moves 359// FIXME: should we use multiple arg nodes? 360def MOV32mrm : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to), 361 "stmy\t{$from, $to, $dst}", 362 []>; 363def MOV64mrm : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to), 364 "stmg\t{$from, $to, $dst}", 365 []>; 366def MOV32rmm : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst), 367 "lmy\t{$from, $to, $dst}", 368 []>; 369def MOV64rmm : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst), 370 "lmg\t{$from, $to, $dst}", 371 []>; 372 373 374//===----------------------------------------------------------------------===// 375// Arithmetic Instructions 376 377let Defs = [PSW] in { 378def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src), 379 "lcr\t{$dst, $src}", 380 [(set GR32:$dst, (ineg GR32:$src)), 381 (implicit PSW)]>; 382def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src), 383 "lcgr\t{$dst, $src}", 384 [(set GR64:$dst, (ineg GR64:$src)), 385 (implicit PSW)]>; 386def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src), 387 "lcgfr\t{$dst, $src}", 388 [(set GR64:$dst, (ineg (sext GR32:$src))), 389 (implicit PSW)]>; 390} 391 392let isTwoAddress = 1 in { 393 394let Defs = [PSW] in { 395 396let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 397// FIXME: Provide proper encoding! 398def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 399 "ar\t{$dst, $src2}", 400 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), 401 (implicit PSW)]>; 402def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 403 "agr\t{$dst, $src2}", 404 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)), 405 (implicit PSW)]>; 406} 407 408// FIXME: Provide proper encoding! 409def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2), 410 "ahi\t{$dst, $src2}", 411 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)), 412 (implicit PSW)]>; 413def ADD32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 414 "afi\t{$dst, $src2}", 415 [(set GR32:$dst, (add GR32:$src1, imm:$src2)), 416 (implicit PSW)]>; 417def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2), 418 "aghi\t{$dst, $src2}", 419 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)), 420 (implicit PSW)]>; 421def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 422 "agfi\t{$dst, $src2}", 423 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)), 424 (implicit PSW)]>; 425 426let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y 427// FIXME: Provide proper encoding! 428def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 429 "nr\t{$dst, $src2}", 430 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; 431def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 432 "ngr\t{$dst, $src2}", 433 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; 434} 435 436// FIXME: Provide proper encoding! 437// FIXME: Compute masked bits properly! 438def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 439 "nill\t{$dst, $src2}", 440 [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>; 441def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 442 "nill\t{$dst, $src2}", 443 [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>; 444 445def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 446 "nilh\t{$dst, $src2}", 447 [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>; 448def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 449 "nilh\t{$dst, $src2}", 450 [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>; 451 452def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 453 "nihl\t{$dst, $src2}", 454 [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>; 455def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 456 "nihh\t{$dst, $src2}", 457 [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>; 458 459def AND32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 460 "nilf\t{$dst, $src2}", 461 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; 462def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 463 "nilf\t{$dst, $src2}", 464 [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>; 465def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 466 "nihf\t{$dst, $src2}", 467 [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>; 468 469let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y 470// FIXME: Provide proper encoding! 471def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 472 "or\t{$dst, $src2}", 473 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; 474def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 475 "ogr\t{$dst, $src2}", 476 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; 477} 478 479def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 480 "oill\t{$dst, $src2}", 481 [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>; 482def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 483 "oilh\t{$dst, $src2}", 484 [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>; 485def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 486 "oilf\t{$dst, $src2}", 487 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; 488 489def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 490 "oill\t{$dst, $src2}", 491 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; 492def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 493 "oilh\t{$dst, $src2}", 494 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>; 495def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 496 "oihl\t{$dst, $src2}", 497 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>; 498def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 499 "oihh\t{$dst, $src2}", 500 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; 501 502def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 503 "oilf\t{$dst, $src2}", 504 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>; 505def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), 506 "oihf\t{$dst, $src2}", 507 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>; 508 509// FIXME: Provide proper encoding! 510def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 511 "sr\t{$dst, $src2}", 512 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; 513def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 514 "sgr\t{$dst, $src2}", 515 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>; 516 517 518let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y 519// FIXME: Provide proper encoding! 520def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 521 "xr\t{$dst, $src2}", 522 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; 523def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 524 "xgr\t{$dst, $src2}", 525 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; 526} 527 528def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 529 "xilf\t{$dst, $src2}", 530 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; 531 532} // Defs = [PSW] 533 534let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y 535def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 536 "msr\t{$dst, $src2}", 537 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>; 538def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 539 "msgr\t{$dst, $src2}", 540 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>; 541 542def MUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 543 "mr\t{$dst, $src2}", 544 []>; 545def UMUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 546 "mlr\t{$dst, $src2}", 547 []>; 548def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 549 "mlgr\t{$dst, $src2}", 550 []>; 551} 552 553 554def MUL32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2), 555 "mhi\t{$dst, $src2}", 556 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>; 557def MUL64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2), 558 "mghi\t{$dst, $src2}", 559 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>; 560 561def MUL32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2), 562 "msfi\t{$dst, $src2}", 563 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>, 564 Requires<[IsZ10]>; 565def MUL64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2), 566 "msgfi\t{$dst, $src2}", 567 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>, 568 Requires<[IsZ10]>; 569 570def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2), 571 "ms\t{$dst, $src2}", 572 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>; 573def MUL32rmy : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2), 574 "msy\t{$dst, $src2}", 575 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>; 576def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), 577 "msg\t{$dst, $src2}", 578 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>; 579 580def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2), 581 "msgfr\t{$dst, $src2}", 582 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>; 583 584def SDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 585 "dr\t{$dst, $src2}", 586 []>; 587 588def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 589 "dsgr\t{$dst, $src2}", 590 []>; 591 592def UDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2), 593 "dlr\t{$dst, $src2}", 594 []>; 595 596def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2), 597 "dlgr\t{$dst, $src2}", 598 []>; 599 600} // isTwoAddress = 1 601 602//===----------------------------------------------------------------------===// 603// Shifts 604 605let isTwoAddress = 1 in 606def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 607 "srl\t{$src, $amt}", 608 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>; 609def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 610 "srlg\t{$dst, $src, $amt}", 611 [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 612def SRLA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 613 "srlg\t{$dst, $src, $amt}", 614 [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>; 615 616let isTwoAddress = 1 in 617def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 618 "sll\t{$src, $amt}", 619 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>; 620def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 621 "sllg\t{$dst, $src, $amt}", 622 [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 623def SHL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 624 "sllg\t{$dst, $src, $amt}", 625 [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>; 626 627let Defs = [PSW] in { 628let isTwoAddress = 1 in 629def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 630 "sra\t{$src, $amt}", 631 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)), 632 (implicit PSW)]>; 633def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 634 "srag\t{$dst, $src, $amt}", 635 [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))), 636 (implicit PSW)]>; 637def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 638 "srag\t{$dst, $src, $amt}", 639 [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))), 640 (implicit PSW)]>; 641} // Defs = [PSW] 642 643let isTwoAddress = 1 in 644def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), 645 "rll\t{$src, $amt}", 646 [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>; 647def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), 648 "rllg\t{$dst, $src, $amt}", 649 [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>; 650def ROTL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), 651 "rllg\t{$dst, $src, $amt}", 652 [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>; 653 654//===----------------------------------------------------------------------===// 655// Test instructions (like AND but do not produce any result 656 657// Integer comparisons 658let Defs = [PSW] in { 659def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2), 660 "cr\t$src1, $src2", 661 [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>; 662def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2), 663 "cgr\t$src1, $src2", 664 [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>; 665 666def CMP32ri : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2), 667 "cfi\t$src1, $src2", 668 [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>; 669def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2), 670 "cgfi\t$src1, $src2", 671 [(SystemZcmp GR64:$src1, i64immSExt32:$src2), 672 (implicit PSW)]>; 673 674def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2), 675 "c\t$src1, $src2", 676 [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)), 677 (implicit PSW)]>; 678def CMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2), 679 "cy\t$src1, $src2", 680 [(SystemZcmp GR32:$src1, (load rriaddr:$src2)), 681 (implicit PSW)]>; 682def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 683 "cg\t$src1, $src2", 684 [(SystemZcmp GR64:$src1, (load rriaddr:$src2)), 685 (implicit PSW)]>; 686 687def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2), 688 "clr\t$src1, $src2", 689 [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>; 690def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2), 691 "clgr\t$src1, $src2", 692 [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>; 693 694def UCMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2), 695 "clfi\t$src1, $src2", 696 [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>; 697def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2), 698 "clgfi\t$src1, $src2", 699 [(SystemZucmp GR64:$src1, i64immZExt32:$src2), 700 (implicit PSW)]>; 701 702def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2), 703 "cl\t$src1, $src2", 704 [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)), 705 (implicit PSW)]>; 706def UCMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2), 707 "cly\t$src1, $src2", 708 [(SystemZucmp GR32:$src1, (load rriaddr:$src2)), 709 (implicit PSW)]>; 710def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 711 "clg\t$src1, $src2", 712 [(SystemZucmp GR64:$src1, (load rriaddr:$src2)), 713 (implicit PSW)]>; 714 715def CMPSX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2), 716 "cgfr\t$src1, $src2", 717 [(SystemZucmp GR64:$src1, (sext GR32:$src2)), 718 (implicit PSW)]>; 719def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2), 720 "clgfr\t$src1, $src2", 721 [(SystemZucmp GR64:$src1, (zext GR32:$src2)), 722 (implicit PSW)]>; 723 724def CMPSX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 725 "cgf\t$src1, $src2", 726 [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)), 727 (implicit PSW)]>; 728def UCMPZX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2), 729 "clgf\t$src1, $src2", 730 [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)), 731 (implicit PSW)]>; 732 733// FIXME: Add other crazy ucmp forms 734 735} // Defs = [PSW] 736 737//===----------------------------------------------------------------------===// 738// Non-Instruction Patterns. 739//===----------------------------------------------------------------------===// 740 741// JumpTable 742def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>; 743 744// anyext 745def : Pat<(i64 (anyext GR32:$src)), 746 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 747 748// calls 749def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>; 750def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>; 751 752//===----------------------------------------------------------------------===// 753// Peepholes. 754//===----------------------------------------------------------------------===// 755 756// FIXME: use add/sub tricks with 32678/-32768 757 758// Arbitrary immediate support. Implement in terms of LLIHF/OILF. 759def : Pat<(i64 imm:$imm), 760 (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>; 761 762// trunc patterns 763def : Pat<(i32 (trunc GR64:$src)), 764 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 765 766// sext_inreg patterns 767def : Pat<(sext_inreg GR64:$src, i32), 768 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 769 770// extload patterns 771def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>; 772def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>; 773def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>; 774def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>; 775def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>; 776 777// muls 778def : Pat<(mulhs GR32:$src1, GR32:$src2), 779 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 780 GR32:$src1, subreg_odd), 781 GR32:$src2), 782 subreg_even)>; 783 784def : Pat<(mulhu GR32:$src1, GR32:$src2), 785 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 786 GR32:$src1, subreg_odd), 787 GR32:$src2), 788 subreg_even)>; 789def : Pat<(mulhu GR64:$src1, GR64:$src2), 790 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 791 GR64:$src1, subreg_odd), 792 GR64:$src2), 793 subreg_even)>; 794 795// divs 796// FIXME: Add memory versions 797def : Pat<(sdiv GR32:$src1, GR32:$src2), 798 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 799 GR32:$src1, subreg_odd), 800 GR32:$src2), 801 subreg_odd)>; 802def : Pat<(sdiv GR64:$src1, GR64:$src2), 803 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 804 GR64:$src1, subreg_odd), 805 GR64:$src2), 806 subreg_odd)>; 807def : Pat<(udiv GR32:$src1, GR32:$src2), 808 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 809 GR32:$src1, subreg_odd), 810 GR32:$src2), 811 subreg_odd)>; 812def : Pat<(udiv GR64:$src1, GR64:$src2), 813 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 814 GR64:$src1, subreg_odd), 815 GR64:$src2), 816 subreg_odd)>; 817 818// rems 819// FIXME: Add memory versions 820def : Pat<(srem GR32:$src1, GR32:$src2), 821 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 822 GR32:$src1, subreg_odd), 823 GR32:$src2), 824 subreg_even)>; 825def : Pat<(srem GR64:$src1, GR64:$src2), 826 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 827 GR64:$src1, subreg_odd), 828 GR64:$src2), 829 subreg_even)>; 830def : Pat<(urem GR32:$src1, GR32:$src2), 831 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 832 GR32:$src1, subreg_odd), 833 GR32:$src2), 834 subreg_even)>; 835def : Pat<(urem GR64:$src1, GR64:$src2), 836 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), 837 GR64:$src1, subreg_odd), 838 GR64:$src2), 839 subreg_even)>; 840 841def : Pat<(i32 imm:$src), 842 (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>; 843