SystemZInstrInfo.td revision 1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07
1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 15 [(callseq_start timm:$amt)]>; 16def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_end timm:$amt1, timm:$amt2)]>; 18 19let neverHasSideEffects = 1 in { 20 // Takes as input the value of the stack pointer after a dynamic allocation 21 // has been made. Sets the output to the address of the dynamically- 22 // allocated area itself, skipping the outgoing arguments. 23 // 24 // This expands to an LA or LAY instruction. We restrict the offset 25 // to the range of LA and keep the LAY range in reserve for when 26 // the size of the outgoing arguments is added. 27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 28 [(set GR64:$dst, dynalloc12only:$src)]>; 29} 30 31//===----------------------------------------------------------------------===// 32// Control flow instructions 33//===----------------------------------------------------------------------===// 34 35// A return instruction. R1 is the condition-code mask (all 1s) 36// and R2 is the target address, which is always stored in %r14. 37let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1, 38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in { 39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>; 40} 41 42// Unconditional branches. R1 is the condition-code mask (all 1s). 43let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 44 let isIndirectBranch = 1 in 45 def BR : InstRR<0x07, (outs), (ins ADDR64:$dst), 46 "br\t$dst", [(brind ADDR64:$dst)]>; 47 48 // An assembler extended mnemonic for BRC. Use a separate instruction for 49 // the asm parser, so that we don't relax Js to external symbols into JGs. 50 let isCodeGenOnly = 1 in 51 def J : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>; 52 let isAsmParserOnly = 1 in 53 def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>; 54 55 // An assembler extended mnemonic for BRCL. (The extension is "G" 56 // rather than "L" because "JL" is "Jump if Less".) 57 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$dst), 58 "jg\t$dst", [(br bb:$dst)]>; 59} 60 61// Conditional branches. It's easier for LLVM to handle these branches 62// in their raw BRC/BRCL form, with the 4-bit condition-code mask being 63// the first operand. It seems friendlier to use mnemonic forms like 64// JE and JLH when writing out the assembly though. 65multiclass CondBranches<Operand imm, string short, string long> { 66 let isBranch = 1, isTerminator = 1, Uses = [PSW] in { 67 def "" : InstRI<0xA74, (outs), (ins imm:$cond, brtarget16:$dst), short, []>; 68 def L : InstRIL<0xC04, (outs), (ins imm:$cond, brtarget32:$dst), long, []>; 69 } 70} 71let isCodeGenOnly = 1 in 72 defm BRC : CondBranches<cond4, "j$cond\t$dst", "jg$cond\t$dst">; 73let isAsmParserOnly = 1 in 74 defm AsmBRC : CondBranches<uimm8zx4, "brc\t$cond, $dst", "brcl\t$cond, $dst">; 75 76def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRCL cond4:$cond, bb:$dst)>; 77 78// Define AsmParser mnemonics for each condition code. 79multiclass CondExtendedMnemonic<bits<4> Cond, string name> { 80 let R1 = Cond in { 81 def "" : InstRI<0xA74, (outs), (ins brtarget16:$dst), 82 "j"##name##"\t$dst", []>; 83 def L : InstRIL<0xC04, (outs), (ins brtarget32:$dst), 84 "jg"##name##"\t$dst", []>; 85 } 86} 87let isAsmParserOnly = 1 in { 88 defm AsmJO : CondExtendedMnemonic<1, "o">; 89 defm AsmJH : CondExtendedMnemonic<2, "h">; 90 defm AsmJNLE : CondExtendedMnemonic<3, "nle">; 91 defm AsmJL : CondExtendedMnemonic<4, "l">; 92 defm AsmJNHE : CondExtendedMnemonic<5, "nhe">; 93 defm AsmJLH : CondExtendedMnemonic<6, "lh">; 94 defm AsmJNE : CondExtendedMnemonic<7, "ne">; 95 defm AsmJE : CondExtendedMnemonic<8, "e">; 96 defm AsmJNLH : CondExtendedMnemonic<9, "nlh">; 97 defm AsmJHE : CondExtendedMnemonic<10, "he">; 98 defm AsmJNL : CondExtendedMnemonic<11, "nl">; 99 defm AsmJLE : CondExtendedMnemonic<12, "le">; 100 defm AsmJNH : CondExtendedMnemonic<13, "nh">; 101 defm AsmJNO : CondExtendedMnemonic<14, "no">; 102} 103 104def Select32 : SelectWrapper<GR32>; 105def Select64 : SelectWrapper<GR64>; 106 107//===----------------------------------------------------------------------===// 108// Call instructions 109//===----------------------------------------------------------------------===// 110 111// The definitions here are for the call-clobbered registers. 112let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, 113 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D], 114 R1 = 14, isCodeGenOnly = 1 in { 115 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$dst, variable_ops), 116 "bras\t%r14, $dst", []>; 117 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$dst, variable_ops), 118 "brasl\t%r14, $dst", [(z_call pcrel32call:$dst)]>; 119 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$dst, variable_ops), 120 "basr\t%r14, $dst", [(z_call ADDR64:$dst)]>; 121} 122 123// Define the general form of the call instructions for the asm parser. 124// These instructions don't hard-code %r14 as the return address register. 125let isAsmParserOnly = 1 in { 126 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$save, brtarget16:$dst), 127 "bras\t$save, $dst", []>; 128 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$save, brtarget32:$dst), 129 "brasl\t$save, $dst", []>; 130 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$save, ADDR64:$dst), 131 "basr\t$save, $dst", []>; 132} 133 134//===----------------------------------------------------------------------===// 135// Move instructions 136//===----------------------------------------------------------------------===// 137 138// Register moves. 139let neverHasSideEffects = 1 in { 140 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 141 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 142} 143 144// Immediate moves. 145let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 146 // 16-bit sign-extended immediates. 147 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 148 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 149 150 // Other 16-bit immediates. 151 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 152 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 153 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 154 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 155 156 // 32-bit immediates. 157 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 158 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 159 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 160} 161 162// Register loads. 163let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 164 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>; 165 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 166 167 def LG : UnaryRXY<"lg", 0xE304, load, GR64>; 168 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 169 170 // These instructions are split after register allocation, so we don't 171 // want a custom inserter. 172 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 173 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 174 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 175 } 176} 177 178// Register stores. 179let SimpleBDXStore = 1 in { 180 let isCodeGenOnly = 1 in { 181 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>; 182 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 183 } 184 185 def STG : StoreRXY<"stg", 0xE324, store, GR64>; 186 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 187 188 // These instructions are split after register allocation, so we don't 189 // want a custom inserter. 190 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 191 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 192 [(store GR128:$src, bdxaddr20only128:$dst)]>; 193 } 194} 195 196// 8-bit immediate stores to 8-bit fields. 197defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 198 199// 16-bit immediate stores to 16-, 32- or 64-bit fields. 200def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 201def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 202def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 203 204//===----------------------------------------------------------------------===// 205// Sign extensions 206//===----------------------------------------------------------------------===// 207 208// 32-bit extensions from registers. 209let neverHasSideEffects = 1 in { 210 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 211 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 212} 213 214// 64-bit extensions from registers. 215let neverHasSideEffects = 1 in { 216 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 217 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 218 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 219} 220 221// Match 32-to-64-bit sign extensions in which the source is already 222// in a 64-bit register. 223def : Pat<(sext_inreg GR64:$src, i32), 224 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 225 226// 32-bit extensions from memory. 227def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>; 228defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>; 229def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>; 230 231// 64-bit extensions from memory. 232def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64>; 233def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>; 234def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>; 235def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>; 236def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>; 237 238// If the sign of a load-extend operation doesn't matter, use the signed ones. 239// There's not really much to choose between the sign and zero extensions, 240// but LH is more compact than LLH for small offsets. 241def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>; 242def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>; 243def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>; 244 245def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>; 246def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>; 247def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>; 248 249//===----------------------------------------------------------------------===// 250// Zero extensions 251//===----------------------------------------------------------------------===// 252 253// 32-bit extensions from registers. 254let neverHasSideEffects = 1 in { 255 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 256 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 257} 258 259// 64-bit extensions from registers. 260let neverHasSideEffects = 1 in { 261 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 262 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 263 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 264} 265 266// Match 32-to-64-bit zero extensions in which the source is already 267// in a 64-bit register. 268def : Pat<(and GR64:$src, 0xffffffff), 269 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 270 271// 32-bit extensions from memory. 272def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32>; 273def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>; 274def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>; 275 276// 64-bit extensions from memory. 277def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64>; 278def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>; 279def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>; 280def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>; 281def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>; 282 283//===----------------------------------------------------------------------===// 284// Truncations 285//===----------------------------------------------------------------------===// 286 287// Truncations of 64-bit registers to 32-bit registers. 288def : Pat<(i32 (trunc GR64:$src)), 289 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 290 291// Truncations of 32-bit registers to memory. 292let isCodeGenOnly = 1 in { 293 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32>; 294 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>; 295 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 296} 297 298// Truncations of 64-bit registers to memory. 299defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64>; 300defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>; 301def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>; 302defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>; 303def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>; 304 305//===----------------------------------------------------------------------===// 306// Multi-register moves 307//===----------------------------------------------------------------------===// 308 309// Multi-register loads. 310def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 311 312// Multi-register stores. 313def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 314 315//===----------------------------------------------------------------------===// 316// Byte swaps 317//===----------------------------------------------------------------------===// 318 319// Byte-swapping register moves. 320let neverHasSideEffects = 1 in { 321 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 322 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 323} 324 325// Byte-swapping loads. 326def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap>, GR32>; 327def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap>, GR64>; 328 329// Byte-swapping stores. 330def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap>, GR32>; 331def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap>, GR64>; 332 333//===----------------------------------------------------------------------===// 334// Load address instructions 335//===----------------------------------------------------------------------===// 336 337// Load BDX-style addresses. 338let neverHasSideEffects = 1, Function = "la" in { 339 let PairType = "12" in 340 def LA : InstRX<0x41, (outs GR64:$dst), (ins laaddr12pair:$src), 341 "la\t$dst, $src", 342 [(set GR64:$dst, laaddr12pair:$src)]>; 343 let PairType = "20" in 344 def LAY : InstRXY<0xE371, (outs GR64:$dst), (ins laaddr20pair:$src), 345 "lay\t$dst, $src", 346 [(set GR64:$dst, laaddr20pair:$src)]>; 347} 348 349// Load a PC-relative address. There's no version of this instruction 350// with a 16-bit offset, so there's no relaxation. 351let neverHasSideEffects = 1 in { 352 def LARL : InstRIL<0xC00, (outs GR64:$dst), (ins pcrel32:$src), 353 "larl\t$dst, $src", 354 [(set GR64:$dst, pcrel32:$src)]>; 355} 356 357//===----------------------------------------------------------------------===// 358// Negation 359//===----------------------------------------------------------------------===// 360 361let Defs = [PSW] in { 362 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 363 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 364 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 365} 366defm : SXU<ineg, LCGFR>; 367 368//===----------------------------------------------------------------------===// 369// Insertion 370//===----------------------------------------------------------------------===// 371 372let isCodeGenOnly = 1 in 373 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>; 374defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>; 375 376defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>; 377defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>; 378 379defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>; 380defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>; 381 382// Insertions of a 16-bit immediate, leaving other bits unaffected. 383// We don't have or_as_insert equivalents of these operations because 384// OI is available instead. 385let isCodeGenOnly = 1 in { 386 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 387 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 388} 389def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>; 390def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>; 391def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>; 392def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>; 393 394// ...likewise for 32-bit immediates. For GR32s this is a general 395// full-width move. (We use IILF rather than something like LLILF 396// for 32-bit moves because IILF leaves the upper 32 bits of the 397// GR64 unchanged.) 398let isCodeGenOnly = 1 in { 399 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 400} 401def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>; 402def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>; 403 404// An alternative model of inserthf, with the first operand being 405// a zero-extended value. 406def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 407 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit), 408 imm64hf32:$imm)>; 409 410//===----------------------------------------------------------------------===// 411// Addition 412//===----------------------------------------------------------------------===// 413 414// Plain addition. 415let Defs = [PSW] in { 416 // Addition of a register. 417 let isCommutable = 1 in { 418 def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>; 419 def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>; 420 } 421 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 422 423 // Addition of signed 16-bit immediates. 424 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>; 425 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>; 426 427 // Addition of signed 32-bit immediates. 428 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 429 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 430 431 // Addition of memory. 432 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>; 433 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load>; 434 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>; 435 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load>; 436 437 // Addition to memory. 438 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 439 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 440} 441defm : SXB<add, GR64, AGFR>; 442 443// Addition producing a carry. 444let Defs = [PSW] in { 445 // Addition of a register. 446 let isCommutable = 1 in { 447 def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>; 448 def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>; 449 } 450 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 451 452 // Addition of unsigned 32-bit immediates. 453 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 454 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 455 456 // Addition of memory. 457 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>; 458 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>; 459 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load>; 460} 461defm : ZXB<addc, GR64, ALGFR>; 462 463// Addition producing and using a carry. 464let Defs = [PSW], Uses = [PSW] in { 465 // Addition of a register. 466 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 467 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 468 469 // Addition of memory. 470 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load>; 471 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>; 472} 473 474//===----------------------------------------------------------------------===// 475// Subtraction 476//===----------------------------------------------------------------------===// 477 478// Plain substraction. Although immediate forms exist, we use the 479// add-immediate instruction instead. 480let Defs = [PSW] in { 481 // Subtraction of a register. 482 def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>; 483 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 484 def SGR : BinaryRRE<"sgr", 0xB909, sub, GR64, GR64>; 485 486 // Subtraction of memory. 487 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>; 488 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>; 489 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load>; 490} 491defm : SXB<sub, GR64, SGFR>; 492 493// Subtraction producing a carry. 494let Defs = [PSW] in { 495 // Subtraction of a register. 496 def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>; 497 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 498 def SLGR : BinaryRRE<"slgr", 0xB90B, subc, GR64, GR64>; 499 500 // Subtraction of unsigned 32-bit immediates. These don't match 501 // subc because we prefer addc for constants. 502 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 503 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 504 505 // Subtraction of memory. 506 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load>; 507 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32>; 508 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load>; 509} 510defm : ZXB<subc, GR64, SLGFR>; 511 512// Subtraction producing and using a carry. 513let Defs = [PSW], Uses = [PSW] in { 514 // Subtraction of a register. 515 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 516 def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 517 518 // Subtraction of memory. 519 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load>; 520 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load>; 521} 522 523//===----------------------------------------------------------------------===// 524// AND 525//===----------------------------------------------------------------------===// 526 527let Defs = [PSW] in { 528 // ANDs of a register. 529 let isCommutable = 1 in { 530 def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>; 531 def NGR : BinaryRRE<"ngr", 0xB980, and, GR64, GR64>; 532 } 533 534 // ANDs of a 16-bit immediate, leaving other bits unaffected. 535 let isCodeGenOnly = 1 in { 536 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 537 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 538 } 539 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>; 540 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>; 541 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>; 542 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>; 543 544 // ANDs of a 32-bit immediate, leaving other bits unaffected. 545 let isCodeGenOnly = 1 in 546 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 547 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>; 548 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>; 549 550 // ANDs of memory. 551 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load>; 552 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load>; 553 554 // AND to memory 555 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>; 556} 557defm : RMWIByte<and, bdaddr12pair, NI>; 558defm : RMWIByte<and, bdaddr20pair, NIY>; 559 560//===----------------------------------------------------------------------===// 561// OR 562//===----------------------------------------------------------------------===// 563 564let Defs = [PSW] in { 565 // ORs of a register. 566 let isCommutable = 1 in { 567 def OR : BinaryRR <"or", 0x16, or, GR32, GR32>; 568 def OGR : BinaryRRE<"ogr", 0xB981, or, GR64, GR64>; 569 } 570 571 // ORs of a 16-bit immediate, leaving other bits unaffected. 572 let isCodeGenOnly = 1 in { 573 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 574 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 575 } 576 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>; 577 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>; 578 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>; 579 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>; 580 581 // ORs of a 32-bit immediate, leaving other bits unaffected. 582 let isCodeGenOnly = 1 in 583 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 584 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>; 585 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>; 586 587 // ORs of memory. 588 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load>; 589 def OG : BinaryRXY<"og", 0xE381, or, GR64, load>; 590 591 // OR to memory 592 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>; 593} 594defm : RMWIByte<or, bdaddr12pair, OI>; 595defm : RMWIByte<or, bdaddr20pair, OIY>; 596 597//===----------------------------------------------------------------------===// 598// XOR 599//===----------------------------------------------------------------------===// 600 601let Defs = [PSW] in { 602 // XORs of a register. 603 let isCommutable = 1 in { 604 def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>; 605 def XGR : BinaryRRE<"xgr", 0xB982, xor, GR64, GR64>; 606 } 607 608 // XORs of a 32-bit immediate, leaving other bits unaffected. 609 let isCodeGenOnly = 1 in 610 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 611 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>; 612 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>; 613 614 // XORs of memory. 615 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load>; 616 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load>; 617 618 // XOR to memory 619 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>; 620} 621defm : RMWIByte<xor, bdaddr12pair, XI>; 622defm : RMWIByte<xor, bdaddr20pair, XIY>; 623 624//===----------------------------------------------------------------------===// 625// Multiplication 626//===----------------------------------------------------------------------===// 627 628// Multiplication of a register. 629let isCommutable = 1 in { 630 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 631 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 632} 633def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 634defm : SXB<mul, GR64, MSGFR>; 635 636// Multiplication of a signed 16-bit immediate. 637def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 638def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 639 640// Multiplication of a signed 32-bit immediate. 641def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 642def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 643 644// Multiplication of memory. 645defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16>; 646defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load>; 647def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32>; 648def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load>; 649 650// Multiplication of a register, producing two results. 651def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>; 652 653// Multiplication of memory, producing two results. 654def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load>; 655 656//===----------------------------------------------------------------------===// 657// Division and remainder 658//===----------------------------------------------------------------------===// 659 660// Division and remainder, from registers. 661def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 662def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>; 663def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>; 664def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>; 665defm : SXB<z_sdivrem64, GR128, DSGFR>; 666 667// Division and remainder, from memory. 668def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem64, GR128, sextloadi32>; 669def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load>; 670def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load>; 671def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load>; 672 673//===----------------------------------------------------------------------===// 674// Shifts 675//===----------------------------------------------------------------------===// 676 677// Shift left. 678let neverHasSideEffects = 1 in { 679 def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>; 680 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>; 681} 682 683// Logical shift right. 684let neverHasSideEffects = 1 in { 685 def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>; 686 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>; 687} 688 689// Arithmetic shift right. 690let Defs = [PSW] in { 691 def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>; 692 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>; 693} 694 695// Rotate left. 696let neverHasSideEffects = 1 in { 697 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>; 698 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>; 699} 700 701// Rotate second operand left and inserted selected bits into first operand. 702// These can act like 32-bit operands provided that the constant start and 703// end bits (operands 2 and 3) are in the range [32, 64) 704let Defs = [PSW] in { 705 let isCodeGenOnly = 1 in 706 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 707 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 708} 709 710//===----------------------------------------------------------------------===// 711// Comparison 712//===----------------------------------------------------------------------===// 713 714// Signed comparisons. 715let Defs = [PSW] in { 716 // Comparison with a register. 717 def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>; 718 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 719 def CGR : CompareRRE<"cgr", 0xB920, z_cmp, GR64, GR64>; 720 721 // Comparison with a signed 16-bit immediate. 722 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>; 723 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>; 724 725 // Comparison with a signed 32-bit immediate. 726 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>; 727 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>; 728 729 // Comparison with memory. 730 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16>; 731 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load>; 732 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16>; 733 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32>; 734 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load>; 735 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>; 736 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>; 737 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>; 738 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>; 739 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>; 740 741 // Comparison between memory and a signed 16-bit immediate. 742 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>; 743 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>; 744 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>; 745} 746defm : SXB<z_cmp, GR64, CGFR>; 747 748// Unsigned comparisons. 749let Defs = [PSW] in { 750 // Comparison with a register. 751 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 752 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 753 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 754 755 // Comparison with a signed 32-bit immediate. 756 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 757 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 758 759 // Comparison with memory. 760 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load>; 761 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32>; 762 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load>; 763 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 764 aligned_zextloadi16>; 765 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 766 aligned_load>; 767 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 768 aligned_zextloadi16>; 769 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 770 aligned_zextloadi32>; 771 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 772 aligned_load>; 773 774 // Comparison between memory and an unsigned 8-bit immediate. 775 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>; 776 777 // Comparison between memory and an unsigned 16-bit immediate. 778 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>; 779 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 780 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 781} 782defm : ZXB<z_ucmp, GR64, CLGFR>; 783 784//===----------------------------------------------------------------------===// 785// Atomic operations 786//===----------------------------------------------------------------------===// 787 788def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 789def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 790def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 791 792def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 793def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 794def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 795def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 796def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 797def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 798def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 799def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 800 801def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 802def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 803def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 804 805def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 806def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 807def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 808def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>; 809def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>; 810def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 811def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 812def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>; 813def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>; 814def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>; 815def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>; 816def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>; 817def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>; 818 819def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 820def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 821def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 822def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 823def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 824def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 825def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 826def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 827def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 828def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 829def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 830def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 831def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 832 833def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 834def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 835def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 836def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 837def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 838def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 839def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 840 841def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 842def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 843 imm32lh16c>; 844def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 845def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 846 imm32ll16c>; 847def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 848 imm32lh16c>; 849def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 850def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 851def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 852 imm64ll16c>; 853def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 854 imm64lh16c>; 855def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 856 imm64hl16c>; 857def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 858 imm64hh16c>; 859def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 860 imm64lf32c>; 861def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 862 imm64hf32c>; 863 864def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 865def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 866def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 867 868def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 869def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 870def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 871 872def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 873def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 874def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 875 876def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 877def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 878def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 879 880def ATOMIC_CMP_SWAPW 881 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 882 ADDR32:$bitshift, ADDR32:$negbitshift, 883 uimm32:$bitsize), 884 [(set GR32:$dst, 885 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 886 ADDR32:$bitshift, ADDR32:$negbitshift, 887 uimm32:$bitsize))]> { 888 let Defs = [PSW]; 889 let mayLoad = 1; 890 let mayStore = 1; 891 let usesCustomInserter = 1; 892} 893 894let Defs = [PSW] in { 895 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 896 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 897} 898 899//===----------------------------------------------------------------------===// 900// Miscellaneous Instructions. 901//===----------------------------------------------------------------------===// 902 903// Read a 32-bit access register into a GR32. As with all GR32 operations, 904// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 905// when a 64-bit address is stored in a pair of access registers. 906def EAR : InstRRE<0xB24F, (outs GR32:$dst), (ins access_reg:$src), 907 "ear\t$dst, $src", 908 [(set GR32:$dst, (z_extract_access access_reg:$src))]>; 909 910// Find leftmost one, AKA count leading zeros. The instruction actually 911// returns a pair of GR64s, the first giving the number of leading zeros 912// and the second giving a copy of the source with the leftmost one bit 913// cleared. We only use the first result here. 914let Defs = [PSW] in { 915 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 916} 917def : Pat<(ctlz GR64:$src), 918 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>; 919 920// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 921def : Pat<(i64 (anyext GR32:$src)), 922 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 923 924// There are no 32-bit equivalents of LLILL and LLILH, so use a full 925// 64-bit move followed by a subreg. This preserves the invariant that 926// all GR32 operations only modify the low 32 bits. 927def : Pat<(i32 imm32ll16:$src), 928 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>; 929def : Pat<(i32 imm32lh16:$src), 930 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>; 931 932// Extend GR32s and GR64s to GR128s. 933let usesCustomInserter = 1 in { 934 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 935 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 936 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 937} 938 939//===----------------------------------------------------------------------===// 940// Peepholes. 941//===----------------------------------------------------------------------===// 942 943// Use AL* for GR64 additions of unsigned 32-bit values. 944defm : ZXB<add, GR64, ALGFR>; 945def : Pat<(add GR64:$src1, imm64zx32:$src2), 946 (ALGFI GR64:$src1, imm64zx32:$src2)>; 947def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 948 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 949 950// Use SL* for GR64 subtractions of unsigned 32-bit values. 951defm : ZXB<sub, GR64, SLGFR>; 952def : Pat<(add GR64:$src1, imm64zx32n:$src2), 953 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 954def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 955 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 956