SystemZInstrInfo.td revision 79e2ed4d838354d8aeaadbbfe0a3779d63e72b25 
1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let neverHasSideEffects = 1 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction (br %r14).
36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37  def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
38
39// Unconditional branches.  R1 is the condition-code mask (all 1s).
40let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41  let isIndirectBranch = 1 in
42    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43                    "br\t$R2", [(brind ADDR64:$R2)]>;
44
45  // An assembler extended mnemonic for BRC.
46  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
47                 [(br bb:$I2)]>;
48
49  // An assembler extended mnemonic for BRCL.  (The extension is "G"
50  // rather than "L" because "JL" is "Jump if Less".)
51  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
52}
53
54// Conditional branches.  It's easier for LLVM to handle these branches
55// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56// the first operand.  It seems friendlier to use mnemonic forms like
57// JE and JLH when writing out the assembly though.
58let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61                                         brtarget16:$I2), "j$R1\t$I2",
62                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64                                           brtarget32:$I2), "jg$R1\t$I2", []>;
65  }
66  def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
67                      "brc\t$R1, $I2", []>;
68  def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
69                        "brcl\t$R1, $I2", []>;
70}
71
72// Fused compare-and-branch instructions.  As for normal branches,
73// we handle these instructions internally in their raw CRJ-like form,
74// but use assembly macros like CRJE when writing them out.
75//
76// These instructions do not use or clobber the condition codes.
77// We nevertheless pretend that they clobber CC, so that we can lower
78// them to separate comparisons and BRCLs if the branch ends up being
79// out of range.
80multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
81  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
82    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
83                                            brtarget16:$RI4),
84                       "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
85    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
86                                            brtarget16:$RI4),
87                       "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
88    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
89                                            brtarget16:$RI4),
90                       "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
91    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
92                                            brtarget16:$RI4),
93                       "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
94    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
95                                             brtarget16:$RI4),
96                        "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
97    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
98                                             brtarget16:$RI4),
99                        "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
100    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
101                                             brtarget16:$RI4),
102                        "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
103    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
104                                             brtarget16:$RI4),
105                        "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
106  }
107}
108let isCodeGenOnly = 1 in
109  defm C : CompareBranches<cond4, "$M3", "">;
110defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
111
112// Define AsmParser mnemonics for each general condition-code mask
113// (integer or floating-point)
114multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
115  let R1 = ccmask in {
116    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
117                   "j"##name##"\t$I2", []>;
118    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
119                     "jg"##name##"\t$I2", []>;
120  }
121  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
122  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
123  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
124  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
125  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
126  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
127}
128defm AsmO   : CondExtendedMnemonic<1,  "o">;
129defm AsmH   : CondExtendedMnemonic<2,  "h">;
130defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
131defm AsmL   : CondExtendedMnemonic<4,  "l">;
132defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
133defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
134defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
135defm AsmE   : CondExtendedMnemonic<8,  "e">;
136defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
137defm AsmHE  : CondExtendedMnemonic<10, "he">;
138defm AsmNL  : CondExtendedMnemonic<11, "nl">;
139defm AsmLE  : CondExtendedMnemonic<12, "le">;
140defm AsmNH  : CondExtendedMnemonic<13, "nh">;
141defm AsmNO  : CondExtendedMnemonic<14, "no">;
142
143// Define AsmParser mnemonics for each integer condition-code mask.
144// This is like the list above, except that condition 3 is not possible
145// and that the low bit of the mask is therefore always 0.  This means
146// that each condition has two names.  Conditions "o" and "no" are not used.
147//
148// We don't make one of the two names an alias of the other because
149// we need the custom parsing routines to select the correct register class.
150multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
151  let M3 = ccmask in {
152    def CR  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
153                                            brtarget16:$RI4),
154                       "crj"##name##"\t$R1, $R2, $RI4", []>;
155    def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
156                                            brtarget16:$RI4),
157                       "cgrj"##name##"\t$R1, $R2, $RI4", []>;
158    def CI  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
159                                            brtarget16:$RI4),
160                       "cij"##name##"\t$R1, $I2, $RI4", []>;
161    def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
162                                            brtarget16:$RI4),
163                       "cgij"##name##"\t$R1, $I2, $RI4", []>;
164    def CLR  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
165                                            brtarget16:$RI4),
166                        "clrj"##name##"\t$R1, $R2, $RI4", []>;
167    def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
168                                             brtarget16:$RI4),
169                        "clgrj"##name##"\t$R1, $R2, $RI4", []>;
170    def CLI  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
171                                             brtarget16:$RI4),
172                        "clij"##name##"\t$R1, $I2, $RI4", []>;
173    def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
174                                             brtarget16:$RI4),
175                        "clgij"##name##"\t$R1, $I2, $RI4", []>;
176  }
177}
178multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
179  : IntCondExtendedMnemonicA<ccmask, name1> {
180  let isAsmParserOnly = 1 in
181    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
182}
183defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
184defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
185defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
186defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
187defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
188defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
189
190// Decrement a register and branch if it is nonzero.  These don't clobber CC,
191// but we might need to split long branches into sequences that do.
192let Defs = [CC] in {
193  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
194  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
195}
196
197//===----------------------------------------------------------------------===//
198// Select instructions
199//===----------------------------------------------------------------------===//
200
201def Select32 : SelectWrapper<GR32>;
202def Select64 : SelectWrapper<GR64>;
203
204defm CondStore8  : CondStores<GR32, nonvolatile_truncstorei8,
205                              nonvolatile_anyextloadi8, bdxaddr20only>;
206defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
207                              nonvolatile_anyextloadi16, bdxaddr20only>;
208defm CondStore32 : CondStores<GR32, nonvolatile_store,
209                              nonvolatile_load, bdxaddr20only>;
210
211defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
212                    nonvolatile_anyextloadi8, bdxaddr20only>;
213defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
214                    nonvolatile_anyextloadi16, bdxaddr20only>;
215defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
216                    nonvolatile_anyextloadi32, bdxaddr20only>;
217defm CondStore64 : CondStores<GR64, nonvolatile_store,
218                              nonvolatile_load, bdxaddr20only>;
219
220//===----------------------------------------------------------------------===//
221// Call instructions
222//===----------------------------------------------------------------------===//
223
224// The definitions here are for the call-clobbered registers.
225let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
226                        F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC] in {
227  def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
228                        [(z_call pcrel32:$I2)]>;
229  def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
230                        [(z_call ADDR64:$R2)]>;
231}
232
233// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
234// are argument registers and since branching to R0 is a no-op.
235let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
236  def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
237                     [(z_sibcall pcrel32:$I2)]>;
238  let Uses = [R1D] in
239    def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
240}
241
242// Define the general form of the call instructions for the asm parser.
243// These instructions don't hard-code %r14 as the return address register.
244def BRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
245                   "bras\t$R1, $I2", []>;
246def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
247                    "brasl\t$R1, $I2", []>;
248def BASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
249                   "basr\t$R1, $R2", []>;
250
251//===----------------------------------------------------------------------===//
252// Move instructions
253//===----------------------------------------------------------------------===//
254
255// Register moves.
256let neverHasSideEffects = 1 in {
257  // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
258  def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
259              Requires<[FeatureHighWord]>;
260  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
261  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
262}
263let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
264  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
265  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
266}
267
268// Move on condition.
269let isCodeGenOnly = 1, Uses = [CC] in {
270  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
271  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
272}
273let Uses = [CC] in {
274  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
275  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
276}
277
278// Immediate moves.
279let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
280    isReMaterializable = 1 in {
281  // 16-bit sign-extended immediates.
282  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
283  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
284
285  // Other 16-bit immediates.
286  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
287  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
288  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
289  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
290
291  // 32-bit immediates.
292  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
293  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
294  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
295}
296
297// Register loads.
298let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
299  // Expands to L, LY or LFH, depending on the choice of register.
300  def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
301             Requires<[FeatureHighWord]>;
302  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
303  def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
304            Requires<[FeatureHighWord]>;
305  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
306
307  // These instructions are split after register allocation, so we don't
308  // want a custom inserter.
309  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
310    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
311                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
312  }
313}
314let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
315  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
316  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
317}
318
319let canFoldAsLoad = 1 in {
320  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
321  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
322}
323
324// Load on condition.
325let isCodeGenOnly = 1, Uses = [CC] in {
326  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
327  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
328}
329let Uses = [CC] in {
330  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
331  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
332}
333
334// Register stores.
335let SimpleBDXStore = 1 in {
336  // Expands to ST, STY or STFH, depending on the choice of register.
337  def STMux : StoreRXYPseudo<store, GRX32, 4>,
338              Requires<[FeatureHighWord]>;
339  defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
340  def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
341             Requires<[FeatureHighWord]>;
342  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
343
344  // These instructions are split after register allocation, so we don't
345  // want a custom inserter.
346  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
347    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
348                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
349  }
350}
351def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
352def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
353
354// Store on condition.
355let isCodeGenOnly = 1, Uses = [CC] in {
356  def STOC  : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
357  def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
358}
359let Uses = [CC] in {
360  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
361  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
362}
363
364// 8-bit immediate stores to 8-bit fields.
365defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
366
367// 16-bit immediate stores to 16-, 32- or 64-bit fields.
368def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
369def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
370def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
371
372// Memory-to-memory moves.
373let mayLoad = 1, mayStore = 1 in
374  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
375
376// String moves.
377let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
378  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
379
380//===----------------------------------------------------------------------===//
381// Sign extensions
382//===----------------------------------------------------------------------===//
383//
384// Note that putting these before zero extensions mean that we will prefer
385// them for anyextload*.  There's not really much to choose between the two
386// either way, but signed-extending loads have a short LH and a long LHY,
387// while zero-extending loads have only the long LLH.
388//
389//===----------------------------------------------------------------------===//
390
391// 32-bit extensions from registers.
392let neverHasSideEffects = 1 in {
393  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
394  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
395}
396
397// 64-bit extensions from registers.
398let neverHasSideEffects = 1 in {
399  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
400  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
401  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
402}
403let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
404  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
405
406// Match 32-to-64-bit sign extensions in which the source is already
407// in a 64-bit register.
408def : Pat<(sext_inreg GR64:$src, i32),
409          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
410
411// 32-bit extensions from 8-bit memory.  LBMux expands to LB or LBH,
412// depending on the choice of register.
413def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
414            Requires<[FeatureHighWord]>;
415def LB  : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
416def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
417          Requires<[FeatureHighWord]>;
418
419// 32-bit extensions from 16-bit memory.  LHMux expands to LH or LHH,
420// depending on the choice of register.
421def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
422            Requires<[FeatureHighWord]>;
423defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
424def  LHH  : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
425            Requires<[FeatureHighWord]>;
426def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
427
428// 64-bit extensions from memory.
429def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
430def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
431def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
432def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
433def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
434let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
435  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
436
437//===----------------------------------------------------------------------===//
438// Zero extensions
439//===----------------------------------------------------------------------===//
440
441// 32-bit extensions from registers.
442let neverHasSideEffects = 1 in {
443  // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
444  def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
445                Requires<[FeatureHighWord]>;
446  def LLCR    : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
447  // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
448  def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
449                Requires<[FeatureHighWord]>;
450  def LLHR    : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
451}
452
453// 64-bit extensions from registers.
454let neverHasSideEffects = 1 in {
455  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
456  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
457  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
458}
459
460// Match 32-to-64-bit zero extensions in which the source is already
461// in a 64-bit register.
462def : Pat<(and GR64:$src, 0xffffffff),
463          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
464
465// 32-bit extensions from 8-bit memory.  LLCMux expands to LLC or LLCH,
466// depending on the choice of register.
467def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
468             Requires<[FeatureHighWord]>;
469def LLC  : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
470def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
471           Requires<[FeatureHighWord]>;
472
473// 32-bit extensions from 16-bit memory.  LLHMux expands to LLH or LLHH,
474// depending on the choice of register.
475def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
476             Requires<[FeatureHighWord]>;
477def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
478def LLHH  : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
479            Requires<[FeatureHighWord]>;
480def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
481
482// 64-bit extensions from memory.
483def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
484def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
485def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
486def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
487def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
488
489//===----------------------------------------------------------------------===//
490// Truncations
491//===----------------------------------------------------------------------===//
492
493// Truncations of 64-bit registers to 32-bit registers.
494def : Pat<(i32 (trunc GR64:$src)),
495          (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
496
497// Truncations of 32-bit registers to 8-bit memory.  STCMux expands to
498// STC, STCY or STCH, depending on the choice of register.
499def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
500             Requires<[FeatureHighWord]>;
501defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
502def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
503           Requires<[FeatureHighWord]>;
504
505// Truncations of 32-bit registers to 16-bit memory.  STHMux expands to
506// STH, STHY or STHH, depending on the choice of register.
507def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
508             Requires<[FeatureHighWord]>;
509defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
510def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
511           Requires<[FeatureHighWord]>;
512def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
513
514// Truncations of 64-bit registers to memory.
515defm : StoreGR64Pair<STC, STCY, truncstorei8>;
516defm : StoreGR64Pair<STH, STHY, truncstorei16>;
517def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
518defm : StoreGR64Pair<ST, STY, truncstorei32>;
519def  : StoreGR64PC<STRL, aligned_truncstorei32>;
520
521//===----------------------------------------------------------------------===//
522// Multi-register moves
523//===----------------------------------------------------------------------===//
524
525// Multi-register loads.
526def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
527
528// Multi-register stores.
529def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
530
531//===----------------------------------------------------------------------===//
532// Byte swaps
533//===----------------------------------------------------------------------===//
534
535// Byte-swapping register moves.
536let neverHasSideEffects = 1 in {
537  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
538  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
539}
540
541// Byte-swapping loads.  Unlike normal loads, these instructions are
542// allowed to access storage more than once.
543def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
544def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
545
546// Likewise byte-swapping stores.
547def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
548def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
549                     GR64, 8>;
550
551//===----------------------------------------------------------------------===//
552// Load address instructions
553//===----------------------------------------------------------------------===//
554
555// Load BDX-style addresses.
556let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
557    DispKey = "la" in {
558  let DispSize = "12" in
559    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
560                    "la\t$R1, $XBD2",
561                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
562  let DispSize = "20" in
563    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
564                      "lay\t$R1, $XBD2",
565                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
566}
567
568// Load a PC-relative address.  There's no version of this instruction
569// with a 16-bit offset, so there's no relaxation.
570let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
571    isReMaterializable = 1 in {
572  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
573                     "larl\t$R1, $I2",
574                     [(set GR64:$R1, pcrel32:$I2)]>;
575}
576
577//===----------------------------------------------------------------------===//
578// Absolute and Negation
579//===----------------------------------------------------------------------===//
580
581let Defs = [CC] in {
582  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
583    def LPR  : UnaryRR <"lp",  0x10,   z_iabs32, GR32, GR32>;
584    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>;
585  }
586  let CCValues = 0xE, CompareZeroCCMask = 0xE in
587    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
588}
589defm : SXU<z_iabs64, LPGFR>;
590
591let Defs = [CC] in {
592  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
593    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs32, GR32, GR32>;
594    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs64, GR64, GR64>;
595  }
596  let CCValues = 0xE, CompareZeroCCMask = 0xE in
597    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
598}
599defm : SXU<z_inegabs64, LNGFR>;
600
601let Defs = [CC] in {
602  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
603    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
604    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
605  }
606  let CCValues = 0xE, CompareZeroCCMask = 0xE in
607    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
608}
609defm : SXU<ineg, LCGFR>;
610
611//===----------------------------------------------------------------------===//
612// Insertion
613//===----------------------------------------------------------------------===//
614
615let isCodeGenOnly = 1 in
616  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
617defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
618
619defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
620defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
621
622defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
623defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
624
625// Insertions of a 16-bit immediate, leaving other bits unaffected.
626// We don't have or_as_insert equivalents of these operations because
627// OI is available instead.
628def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
629def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
630def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
631def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
632def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
633def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
634
635// ...likewise for 32-bit immediates.  For GR32s this is a general
636// full-width move.  (We use IILF rather than something like LLILF
637// for 32-bit moves because IILF leaves the upper 32 bits of the
638// GR64 unchanged.)
639let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in
640  def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
641def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
642def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
643
644// An alternative model of inserthf, with the first operand being
645// a zero-extended value.
646def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
647          (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
648                imm64hf32:$imm)>;
649
650//===----------------------------------------------------------------------===//
651// Addition
652//===----------------------------------------------------------------------===//
653
654// Plain addition.
655let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
656  // Addition of a register.
657  let isCommutable = 1 in {
658    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
659    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
660  }
661  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
662
663  // Addition of signed 16-bit immediates.
664  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
665  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
666
667  // Addition of signed 32-bit immediates.
668  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
669  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
670
671  // Addition of memory.
672  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
673  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
674  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
675  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
676
677  // Addition to memory.
678  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
679  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
680}
681defm : SXB<add, GR64, AGFR>;
682
683// Addition producing a carry.
684let Defs = [CC] in {
685  // Addition of a register.
686  let isCommutable = 1 in {
687    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
688    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
689  }
690  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
691
692  // Addition of signed 16-bit immediates.
693  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
694                Requires<[FeatureDistinctOps]>;
695  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
696                Requires<[FeatureDistinctOps]>;
697
698  // Addition of unsigned 32-bit immediates.
699  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
700  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
701
702  // Addition of memory.
703  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
704  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
705  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
706}
707defm : ZXB<addc, GR64, ALGFR>;
708
709// Addition producing and using a carry.
710let Defs = [CC], Uses = [CC] in {
711  // Addition of a register.
712  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
713  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
714
715  // Addition of memory.
716  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
717  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
718}
719
720//===----------------------------------------------------------------------===//
721// Subtraction
722//===----------------------------------------------------------------------===//
723
724// Plain substraction.  Although immediate forms exist, we use the
725// add-immediate instruction instead.
726let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
727  // Subtraction of a register.
728  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
729  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
730  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
731
732  // Subtraction of memory.
733  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
734  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
735  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
736  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
737}
738defm : SXB<sub, GR64, SGFR>;
739
740// Subtraction producing a carry.
741let Defs = [CC] in {
742  // Subtraction of a register.
743  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
744  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
745  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
746
747  // Subtraction of unsigned 32-bit immediates.  These don't match
748  // subc because we prefer addc for constants.
749  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
750  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
751
752  // Subtraction of memory.
753  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
754  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
755  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
756}
757defm : ZXB<subc, GR64, SLGFR>;
758
759// Subtraction producing and using a carry.
760let Defs = [CC], Uses = [CC] in {
761  // Subtraction of a register.
762  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
763  def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
764
765  // Subtraction of memory.
766  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
767  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
768}
769
770//===----------------------------------------------------------------------===//
771// AND
772//===----------------------------------------------------------------------===//
773
774let Defs = [CC] in {
775  // ANDs of a register.
776  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
777    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
778    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
779  }
780
781  let isConvertibleToThreeAddress = 1 in {
782    // ANDs of a 16-bit immediate, leaving other bits unaffected.
783    // The CC result only reflects the 16-bit field, not the full register.
784    def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
785    def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
786    def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
787    def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
788    def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
789    def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
790
791    // ANDs of a 32-bit immediate, leaving other bits unaffected.
792    // The CC result only reflects the 32-bit field, which means we can
793    // use it as a zero indicator for i32 operations but not otherwise.
794    let CCValues = 0xC, CompareZeroCCMask = 0x8 in
795      def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
796    def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
797    def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
798  }
799
800  // ANDs of memory.
801  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
802    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
803    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 
804  }
805
806  // AND to memory
807  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
808
809  // Block AND.
810  let mayLoad = 1, mayStore = 1 in
811    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
812}
813defm : RMWIByte<and, bdaddr12pair, NI>;
814defm : RMWIByte<and, bdaddr20pair, NIY>;
815
816//===----------------------------------------------------------------------===//
817// OR
818//===----------------------------------------------------------------------===//
819
820let Defs = [CC] in {
821  // ORs of a register.
822  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
823    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
824    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
825  }
826
827  // ORs of a 16-bit immediate, leaving other bits unaffected.
828  // The CC result only reflects the 16-bit field, not the full register.
829  def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
830  def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
831  def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
832  def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
833  def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
834  def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
835
836  // ORs of a 32-bit immediate, leaving other bits unaffected.
837  // The CC result only reflects the 32-bit field, which means we can
838  // use it as a zero indicator for i32 operations but not otherwise.
839  let CCValues = 0xC, CompareZeroCCMask = 0x8 in
840    def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
841  def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
842  def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
843
844  // ORs of memory.
845  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
846    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
847    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
848  }
849
850  // OR to memory
851  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
852
853  // Block OR.
854  let mayLoad = 1, mayStore = 1 in
855    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
856}
857defm : RMWIByte<or, bdaddr12pair, OI>;
858defm : RMWIByte<or, bdaddr20pair, OIY>;
859
860//===----------------------------------------------------------------------===//
861// XOR
862//===----------------------------------------------------------------------===//
863
864let Defs = [CC] in {
865  // XORs of a register.
866  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
867    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
868    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
869  }
870
871  // XORs of a 32-bit immediate, leaving other bits unaffected.
872  // The CC result only reflects the 32-bit field, which means we can
873  // use it as a zero indicator for i32 operations but not otherwise.
874  let CCValues = 0xC, CompareZeroCCMask = 0x8 in
875    def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
876  def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
877  def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
878
879  // XORs of memory.
880  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
881    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
882    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
883  }
884
885  // XOR to memory
886  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
887
888  // Block XOR.
889  let mayLoad = 1, mayStore = 1 in
890    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
891}
892defm : RMWIByte<xor, bdaddr12pair, XI>;
893defm : RMWIByte<xor, bdaddr20pair, XIY>;
894
895//===----------------------------------------------------------------------===//
896// Multiplication
897//===----------------------------------------------------------------------===//
898
899// Multiplication of a register.
900let isCommutable = 1 in {
901  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
902  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
903}
904def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
905defm : SXB<mul, GR64, MSGFR>;
906
907// Multiplication of a signed 16-bit immediate.
908def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
909def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
910
911// Multiplication of a signed 32-bit immediate.
912def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
913def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
914
915// Multiplication of memory.
916defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
917defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
918def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
919def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
920
921// Multiplication of a register, producing two results.
922def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
923
924// Multiplication of memory, producing two results.
925def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
926
927//===----------------------------------------------------------------------===//
928// Division and remainder
929//===----------------------------------------------------------------------===//
930
931// Division and remainder, from registers.
932def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
933def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
934def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
935def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
936
937// Division and remainder, from memory.
938def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
939def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
940def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
941def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
942
943//===----------------------------------------------------------------------===//
944// Shifts
945//===----------------------------------------------------------------------===//
946
947// Shift left.
948let neverHasSideEffects = 1 in {
949  defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
950  def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
951}
952
953// Logical shift right.
954let neverHasSideEffects = 1 in {
955  defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
956  def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
957}
958
959// Arithmetic shift right.
960let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
961  defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
962  def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
963}
964
965// Rotate left.
966let neverHasSideEffects = 1 in {
967  def RLL  : ShiftRSY<"rll",  0xEB1D, rotl, GR32>;
968  def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
969}
970
971// Rotate second operand left and inserted selected bits into first operand.
972// These can act like 32-bit operands provided that the constant start and
973// end bits (operands 2 and 3) are in the range [32, 64).
974let Defs = [CC] in {
975  let isCodeGenOnly = 1 in
976    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
977  let CCValues = 0xE, CompareZeroCCMask = 0xE in
978    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
979}
980
981// Forms of RISBG that only affect one word of the destination register.
982// They do not set CC.
983def RISBLL : RotateSelectAliasRIEf<GR32,  GR32>,  Requires<[FeatureHighWord]>;
984def RISBLH : RotateSelectAliasRIEf<GR32,  GRH32>, Requires<[FeatureHighWord]>;
985def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>,  Requires<[FeatureHighWord]>;
986def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>, Requires<[FeatureHighWord]>;
987def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
988             Requires<[FeatureHighWord]>;
989def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
990             Requires<[FeatureHighWord]>;
991
992// Rotate second operand left and perform a logical operation with selected
993// bits of the first operand.  The CC result only describes the selected bits,
994// so isn't useful for a full comparison against zero.
995let Defs = [CC] in {
996  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
997  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
998  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
999}
1000
1001//===----------------------------------------------------------------------===//
1002// Comparison
1003//===----------------------------------------------------------------------===//
1004
1005// Signed comparisons.  We put these before the unsigned comparisons because
1006// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1007// of the unsigned forms do.
1008let Defs = [CC], CCValues = 0xE in {
1009  // Comparison with a register.
1010  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
1011  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1012  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
1013
1014  // Comparison with a signed 16-bit immediate.
1015  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
1016  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1017
1018  // Comparison with a signed 32-bit immediate.
1019  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
1020  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1021
1022  // Comparison with memory.
1023  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1024  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
1025  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1026  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1027  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
1028  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
1029  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
1030  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1031  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1032  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
1033
1034  // Comparison between memory and a signed 16-bit immediate.
1035  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1036  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
1037  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1038}
1039defm : SXB<z_scmp, GR64, CGFR>;
1040
1041// Unsigned comparisons.
1042let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1043  // Comparison with a register.
1044  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
1045  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1046  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
1047
1048  // Comparison with a signed 32-bit immediate.
1049  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
1050  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1051
1052  // Comparison with memory.
1053  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1054  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1055  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1056  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1057                             aligned_azextloadi16>;
1058  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1059                             aligned_load>;
1060  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1061                             aligned_azextloadi16>;
1062  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1063                             aligned_azextloadi32>;
1064  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1065                             aligned_load>;
1066
1067  // Comparison between memory and an unsigned 8-bit immediate.
1068  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1069
1070  // Comparison between memory and an unsigned 16-bit immediate.
1071  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1072  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1073  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1074}
1075defm : ZXB<z_ucmp, GR64, CLGFR>;
1076
1077// Memory-to-memory comparison.
1078let mayLoad = 1, Defs = [CC] in
1079  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1080
1081// String comparison.
1082let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1083  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1084
1085// Test under mask.
1086let Defs = [CC] in {
1087  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1088  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1089
1090  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>;
1091  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>;
1092
1093  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1094}
1095def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>;
1096def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>;
1097
1098//===----------------------------------------------------------------------===//
1099// Prefetch
1100//===----------------------------------------------------------------------===//
1101
1102def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1103def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1104
1105//===----------------------------------------------------------------------===//
1106// Atomic operations
1107//===----------------------------------------------------------------------===//
1108
1109def ATOMIC_SWAPW        : AtomicLoadWBinaryReg<z_atomic_swapw>;
1110def ATOMIC_SWAP_32      : AtomicLoadBinaryReg32<atomic_swap_32>;
1111def ATOMIC_SWAP_64      : AtomicLoadBinaryReg64<atomic_swap_64>;
1112
1113def ATOMIC_LOADW_AR     : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1114def ATOMIC_LOADW_AFI    : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1115def ATOMIC_LOAD_AR      : AtomicLoadBinaryReg32<atomic_load_add_32>;
1116def ATOMIC_LOAD_AHI     : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1117def ATOMIC_LOAD_AFI     : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1118def ATOMIC_LOAD_AGR     : AtomicLoadBinaryReg64<atomic_load_add_64>;
1119def ATOMIC_LOAD_AGHI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1120def ATOMIC_LOAD_AGFI    : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1121
1122def ATOMIC_LOADW_SR     : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1123def ATOMIC_LOAD_SR      : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1124def ATOMIC_LOAD_SGR     : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1125
1126def ATOMIC_LOADW_NR     : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1127def ATOMIC_LOADW_NILH   : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1128def ATOMIC_LOAD_NR      : AtomicLoadBinaryReg32<atomic_load_and_32>;
1129def ATOMIC_LOAD_NILL    : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1130def ATOMIC_LOAD_NILH    : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1131def ATOMIC_LOAD_NILF    : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1132def ATOMIC_LOAD_NGR     : AtomicLoadBinaryReg64<atomic_load_and_64>;
1133def ATOMIC_LOAD_NILL64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1134def ATOMIC_LOAD_NILH64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1135def ATOMIC_LOAD_NIHL    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1136def ATOMIC_LOAD_NIHH    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1137def ATOMIC_LOAD_NILF64  : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1138def ATOMIC_LOAD_NIHF    : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1139
1140def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1141def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1142def ATOMIC_LOAD_OR      : AtomicLoadBinaryReg32<atomic_load_or_32>;
1143def ATOMIC_LOAD_OILL    : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1144def ATOMIC_LOAD_OILH    : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1145def ATOMIC_LOAD_OILF    : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1146def ATOMIC_LOAD_OGR     : AtomicLoadBinaryReg64<atomic_load_or_64>;
1147def ATOMIC_LOAD_OILL64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1148def ATOMIC_LOAD_OILH64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1149def ATOMIC_LOAD_OIHL    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1150def ATOMIC_LOAD_OIHH    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1151def ATOMIC_LOAD_OILF64  : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1152def ATOMIC_LOAD_OIHF    : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1153
1154def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1155def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1156def ATOMIC_LOAD_XR      : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1157def ATOMIC_LOAD_XILF    : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1158def ATOMIC_LOAD_XGR     : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1159def ATOMIC_LOAD_XILF64  : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1160def ATOMIC_LOAD_XIHF    : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1161
1162def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1163def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1164                                               imm32lh16c>;
1165def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1166def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1167                                                imm32ll16c>;
1168def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1169                                                imm32lh16c>;
1170def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1171def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1172def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1173                                                imm64ll16c>;
1174def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1175                                                imm64lh16c>;
1176def ATOMIC_LOAD_NIHLi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1177                                                imm64hl16c>;
1178def ATOMIC_LOAD_NIHHi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1179                                                imm64hh16c>;
1180def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1181                                                imm64lf32c>;
1182def ATOMIC_LOAD_NIHFi   : AtomicLoadBinaryImm64<atomic_load_nand_64,
1183                                                imm64hf32c>;
1184
1185def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1186def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1187def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1188
1189def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1190def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1191def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1192
1193def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1194def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1195def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1196
1197def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1198def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1199def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1200
1201def ATOMIC_CMP_SWAPW
1202  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1203                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1204                                  uimm32:$bitsize),
1205           [(set GR32:$dst,
1206                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1207                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1208                                     uimm32:$bitsize))]> {
1209  let Defs = [CC];
1210  let mayLoad = 1;
1211  let mayStore = 1;
1212  let usesCustomInserter = 1;
1213}
1214
1215let Defs = [CC] in {
1216  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1217  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1218}
1219
1220//===----------------------------------------------------------------------===//
1221// Miscellaneous Instructions.
1222//===----------------------------------------------------------------------===//
1223
1224// Extract CC into bits 29 and 28 of a register.
1225let Uses = [CC] in
1226  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1227
1228// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1229// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1230// when a 64-bit address is stored in a pair of access registers.
1231def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1232                  "ear\t$R1, $R2",
1233                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1234
1235// Find leftmost one, AKA count leading zeros.  The instruction actually
1236// returns a pair of GR64s, the first giving the number of leading zeros
1237// and the second giving a copy of the source with the leftmost one bit
1238// cleared.  We only use the first result here.
1239let Defs = [CC] in {
1240  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1241}
1242def : Pat<(ctlz GR64:$src),
1243          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1244
1245// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1246def : Pat<(i64 (anyext GR32:$src)),
1247          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1248
1249// Extend GR32s and GR64s to GR128s.
1250let usesCustomInserter = 1 in {
1251  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1252  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1253  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1254}
1255
1256// Search a block of memory for a character.
1257let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1258  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1259
1260//===----------------------------------------------------------------------===//
1261// Peepholes.
1262//===----------------------------------------------------------------------===//
1263
1264// Use AL* for GR64 additions of unsigned 32-bit values.
1265defm : ZXB<add, GR64, ALGFR>;
1266def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1267           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1268def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1269           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1270
1271// Use SL* for GR64 subtractions of unsigned 32-bit values.
1272defm : ZXB<sub, GR64, SLGFR>;
1273def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1274           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1275def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1276           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1277
1278// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1279// for vector legalization.
1280def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1281                         (i32 31)),
1282                    (i32 31)),
1283          (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1284def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1285                                                       uimm8zx4:$cc)))),
1286                    (i32 63)),
1287               (i32 63)),
1288          (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1289
1290// Peepholes for turning scalar operations into block operations.
1291defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1292                      XCSequence, 1>;
1293defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1294                      XCSequence, 2>;
1295defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1296                      XCSequence, 4>;
1297defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1298                      OCSequence, XCSequence, 1>;
1299defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1300                      XCSequence, 2>;
1301defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1302                      XCSequence, 4>;
1303defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1304                      XCSequence, 8>;
1305